EC2013E VLSI DESIGN

Course Outcomes
• CO1: Analyse static and dynamic characteristics of digital CMOS circuits.

• CO2: Design static and dynamic CMOS logic circuits for a given functionality,
speed, power consumption and area requirements.

• CO3: Demonstrate the performance of CMOS logic circuits designed using various
logic styles with the help of CAD tools.

• CO4: Design arithmetic circuits and memories using CMOS.

2
 Evaluation Policy
— Relative Grading

— Mark Distribution: 0 Marks

o Mid Test – 30
o Assmt - 20
o Final Exam – 50

3
 Reference Books
1. J.M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits- A Design
Perspective, 2nd Edn., Pearson Education, 2016

2. N.H.E. Weste and David M. Harris, CMOS VLSI Design - a Circuits and System
Perspective, 4th Edn., Pearson Education Asia, 2010

3. S.M. Kang, Y. Leblebici and Chul Woo Kim CMOS Digital Integrated Circuits
Analysis and Design, 4th Edn., McGraw Hill, 2019

4
Introduction
 History
— MOS field-effect transistor - Lilienfeld (1925), Heil (1935)
— Invention of the transistor (BJT) 1947 - Shockley, Bardeen, Brattain – Bell Labs
— First Bipolar digital logic: Harris (1956)
— First integrated circuit flip-flop with two transistors 1958 - Jack Kilby – Texas
Instruments
— PMOS and NMOS transistors on the same substrate: Weimer (1962), Wanlass
(1965)
— PMOS-only logic until 1971 when NMOS technology emerged
— NMOS-only logic until late 1970s, when CMOS technology took over
— Invention of CMOS logic gates 1963 - Wanlass & Sah – Fairchild Semiconductor
— First microprocessor (Intel 4004) 1970 - 2,300 MOS transistors, 740 kHz clock
frequency
— Very Large Scale Integration 1978 - Chips with more than ~20,000 devices
— System on Chip (SoC) - 20 ~ 30 million transistors in 2002
— 2008: Intel Core2 Duo – 291,000,000 transistors
— 2012: NVIDIA GK110 (Kepler) ~7,000,000,000 transistors

6
 VLSI : Very Large Scale
Integration
— Moore’s Law - Transistor count doubles every 18 months.
— Integration: Integrated Circuits
o multiple devices on one substrate
— How large is Very Large?
— SSI (small scale integration) - <10 gates
o 7400 series
— MSI (medium scale) - < 100 gates
o 74161 counter
— LSI - < 1,000 gates
o 8-bit microprocessors
— VLSI (1978) > 1,000 gates
— ULSI
— SoC (System On Chip) – 20 / 30 Million transistors in 2002

7
— The 4004 had a feature size of 10 μm in 1971.
— The Core 2 Duo had a feature size of 45 nm in 2008.
— Manufacturers introduce a new process generation (also called a technology
node) every 2–3 years with a 30% smaller feature size to pack twice as many
transistors in the same area.
— Scaling can’t go on forever because transistors cannot be smaller than atoms.
— For feature sizes below 180 nm, transistors also leak a significant amount of
current even when they should be OFF. Thus, chips now draw static power even
when they are idle.
— One of the central challenges of VLSI design is making good trade-offs between
performance and power for a particular application.
— The cost of a chip includes nonrecurring engineering (NRE) expenses for the
design and masks, along with per-chip manufacturing costs related to the size of
the chip. In processes with smaller feature sizes, the per-unit cost goes down
because more transistors can be packed into a given area, but the NRE increases.
— The latest manufacturing processes are only cost-effective for chips that will sell in
huge volumes

8
Transistors in microprocessors
•20 μm – 1968
•10 μm – 1971
•6 μm – 1974
•3 μm – 1977
• 1.5 μm – 1981
•1 μm – 1984
•800 nm – 1987
•600 nm – 1990
•350 nm – 1993
•250 nm – 1996
•180 nm – 1999
•130 nm – 2001
•90 nm – 2003
•65 nm – 2005
•45 nm – 2007
•32 nm – 2009
•28 nm – 2010
•22 nm – 2012
•14 nm – 2014
•10 nm – 2016
•7 nm – 2018
•5 nm – 2020
•3 nm – 2022
•Future2 nm ~ 2024
9
Process generations

10
Clock frequencies of Intel
microprocessors

11
 Intel Core2 Duo…
— Even 291 million is a LOT of transistors

— Where are they used?

o Mostly for memory!
o Intel Core2 Duo: 4MB shared L2 cache, 32K Icache 32K Dcache on
each core
o 4*10242*8 + 2(64*1024*8) = 34,603,008 bits
o Around 6 transistors per bit of memory
o ~35,000,000 bits * 6 = ~210,000,000 transistors

12
 Why MOS/CMOS
— CMOS (complementary metal oxide semiconductor) technology
continues to be the dominant technology for fabricating
integrated circuits (ICs or chips).
o CMOS contains two MOSFETs – NMOS and PMOS

— Advantages of CMOS technology

o Low power dissipation
o High noise margins in both states
o Relatively high speed
o Low cost
o Scalability.

— Complementary MOSFET (CMOS) technology is widely used in

today’s computers, CPUs and cell phones.

14
VLSI Design Flow

16
17
18
19
 Classification of CMOS digital
circuits

Digital Circuits

Static Circuits Dynamic Circuits

Classical Transmis CVSL Domino NORA TSPC

CMOS sion-gate gates Logic Logic Logic
CMOS Circuits Circuits Circuits

CVSL – Cascade Voltage Switch Logic

TSPC – True Single-Phase Clock

20
Basics of MOS

21
 MOS Transistor
— MOSFET – Metal Oxide Semiconductor Field Effect Transistor
— Fundamental block of MOS and CMOS digital integrated circuits
— 3 Layers
o Metal Gate Electrode
— Since the 1970s, the gate has been formed from polycrystalline silicon
(polysilicon).
— Metal gates reemerged in 2007 to solve materials problems in advanced
manufacturing processes.
o Insulating Oxide Layer
o Substrate

— MOS Structure forms a capacitor

o Gate and substrate acts as two terminals (plates)
o Oxide layer acts as the dielectric.

22
 MOSFET - INTRODUCTION
— MOSFETs provide many advantages.
o They offer a very high input impedance and they are able to
consume very low levels of current.
o This is particularly important for integrated circuit technology where
power limitations are a major consideration.
o Relatively simple manufacturing process

— Hence, it is possible to realize 106/107 transistors on an

integrated circuit (IC) economically.

— MOSFETs are widely used in applications such as switches and

amplifiers. They are also able to consume very low levels of
current and as a result they are widely used in microprocessors,
logic integrated circuits and the like.

23
 MOS transistor
— Add “source” and “drain” terminals to MOS capacitor

N+ N+ P+ P+
source drain source drain
P-substrate N-substrate
NMOS PMOS

24
MOSFET structure

25
 MOSFET: Device dimensions
— Channel length (L): Distance between source-substrate junction
and drain-substrate junction near the oxide-substrate interface

— Channel Width (W): Width of the channel

— Oxide thickness (tox): Gate insulator thickness

26
 Circuit symbols forMOSFETs.

Since the body is generally connected to a dc supply that is identical for

all devices of the same type (GND for NMOS, Vdd for PMOS), it is most
often not shown on the schematics

27
 MOSFET Biasing
Type of Sign of
MOSFET
Substrate Capacitor Inversion Threshold
Type
Carriers Voltage
P - Type PMOS N-Channel Electrons +
N - Type NMOS P-Channel Holes -

— In a n-channel MOSFET (NMOSFET), source is more negatively

biased in comparison with drain

— In a p-channel MOSFET (PMOSFET), drain is more negatively

biased in comparison with source

— Generally, the applied gate voltage and drain voltage are positive
in NMOSFET and negative in a PMOSFET

28
 Types of MOSFET
— Enhancement Type (Enhancement Mode)
o A MOS transistor which has no conducting channel region at zero
gate bias

— Depletion Type (Depletion Mode)

o A MOS transistor which has a conducting channel at zero gate bias

Here, we will mainly consider Enhancement Type MOSFETs

29
 Two Terminal MOS Structure

Mass Action Law

2
• At Equilibrium np = ni (ni = 1.45x 1010 cm-3 at T = 300K)
• If the substrate is uniformly doped with NA, the equilibrium
electron and hole concentrations in the p-type substrate
ni2
pp 0 ≅ N A np 0 ≅
NA ni2
• If the substrate is uniformly doped with ND, nn 0 ≅ N D pn 0 ≅
ND
30
 Energy Band Diagrams

EC
EF
qf Fn
EF = Ei Ei Ei
qf Fp
EF
EV

Intrinsic N-type P-type

31
 Extrinsic Energy Bands

For N-type: For P-type:

( Ei −EF )/kT
n0 = N D = ni e ( EF −Ei )/kT p0 = N A = ni e
ND ni
EF − Ei = kT ln EF − Ei = kT ln
ni NA
ND ni
qφ Fn = kT ln qφ Fp = kT ln
ni NA

φ Fn , φ Fp are the Fermi Potential of n and p type semiconductors.

qφ F = EF − Ei
32
— The electron affinity, qχ, is the potential difference between the
conduction band level and the vacuum (free-space) level.

— The energy required for an electron to move from the Fermi level
into free space is called the work function, qΦ and is given by
qΦ = q χ + (EC − EF )
— The Fermi potential at the surface, called surface potential, Φs,
is smaller in magnitude than the bulk Fermi potential, ΦF. (Why?)

— The voltage which has to be applied between the gate and the
substrate, so that the bending of the energy bands near the
surface can be compensated i.e., the energy bands become flat
is called flat band voltage, VFB

VFB = Φ M − Φ S

33
 MOS Energy Band Diagram
Work function difference between Al and Si - depends on material used,
doping, etc.

qVFB

34
 Energy band diagram of
a combined MOS structure
Electric field,ε

35
MOS structure: Accumulation

38
MOS structure: Depletion, under
small gate bias.

39
 MOS structure: Strong Inversion

• When the condition is φ s = −φ F, strong inversion starts and the depletion

region has maximum depth

2ε si . 2φ F
xd =
qN A
• At the start of Strong Inversion, MOSFET starts to turn on.
41
 MOS transistor operation
— Simple case: VD = VS = VB = 0 - Operates as MOS capacitor

— When VGS<VT0, depletion region forms - No carriers in channel to

connect S and D

Vg < VT0

Vs=0 Vd=0
depletion
source drain region

P-substrate

VB = 0

42
 MOS transistor operation
— When VGS > VT0, inversion layer forms

— Source and drain connected by conducting n-type layer (for

NMOS)

Vg > VT0

Vs=0 Vd=0
depletion
source drain region

P-substrate

inversion
layer VB = 0

43
 Threshold voltage components
— The value of the gate-to-source voltage VGS needed to cause
surface inversion (to create the conducting channel) is called the
threshold voltage V.

— The 4 physical components affecting the threshold voltage of a

MOS structure
1. Work function difference between gate & channel (Flat-band
voltage)
2. Gate voltage to change surface potential
3. Gate voltage to offset depletion charge
4. Gate voltage to offset fixed charges in gate oxide and silicon-oxide
interface

44
 Threshold voltage (1)

— Work function difference VFB between gate

and channel

VT 0 = VFB + 
This accounts for built-in voltage drop

45
 Threshold voltage (2)
— Now apply additional gate voltage to achieve
inversion: change surface potential by -2fF

VT 0 = VFB - 2fF + 

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 Threshold voltage (3)

— Depletion region charge, due to fixed acceptor

ions

QB 0 = - 2qN Ae Si - 2f F (charge/area)

— To offset this charge, need voltage – QB0/Cox

where, Cox=eox/tox

47
 Threshold voltage (4)
— Finally, correct for non-ideal fixed charges - Fixed
positive charged ions at boundary between oxide and
substrate. Density = NOX (ions/cm2)

o Due to impurities, lattice imperfections at interface,

positive charge density Qox = qNox

o Correct with gate voltage = -Qox/Cox

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Threshold voltage (for NMOS):
QB 0 Qox
VT 0 = VFB - 2f F - -
Cox Cox

49
 Threshold voltage (5)
— What if substrate bias VSB is not zero?
o Depletion width W changes
o Need to account for different depletion region
charge

(VSB = 0): QB 0 = - 2qN Ae Si - 2f F

(VSB ¹ 0): QB = - 2qN Ae Si - 2fF + VSB

50
 Threshold voltage: general
QB Qox
VT = VFB - 2f F - -
Cox Cox

QB - QB 0
VT = VT 0 -
Cox

Body effect
VT = VT 0 + γ ( −2ϕ F + VSB − 2ϕ F )
coefficient 2qN Aε Si + for NMOS
γ=
Cox - for PMOS

51
 Threshold Voltage
NMOS PMOS
Substrate Fermi potential fF < 0 fF > 0
Depletion charge density QB < 0 QB > 0

Substrate bias coefficient g>0 g<0

Source to bulk voltage VSB > 0 VSB < 0

Threshold voltage
VT0 > 0 VT0 < 0
(enhancement devices)

52
Body effect

VT0

VSB (V)
53
 MOS transistor characteristics
— Cutoff: VGS < Vt and IDS » 0

— Linear: VGS > VT, VDS < VGS-VT

Inversion layer connects drain and source. Current is almost
linear with VDS

— Saturation: VGS>VT, VDS³VGS-VT Channel is “pinched-off”.

Current saturates.

57
 Linear mode
— When VGS>VT, an inversion layer forms between drain and source
- Depth of channel depends on V between gate and channel -
Drain end narrower due to larger drain voltage - Drain end depth
reduces as VDS is increased

Vg > VT0
Vs=0 Vd < VGS-VT0
Channel depletion
source drain
(inversion region
layer) P-substrate
VB = 0
58
 Saturation mode
— When VDS = VGS - VT:
o No longer a voltage drop of VT from gate to substrate at drain
o Channel is “pinched off”

Vg > VT0
Vs=0 Vd > VGS-VT0
depletion
source drain
region

pinch-off point VB = 0
61
 Saturation I/V Equation
— If VDS is further increased, no increase in current - Pinch-off point
moves closer to source - Channel between that point and drain is
depleted - High electric field in depleted region accelerates
electrons towards drain - To get saturation current, use linear
equation with VDS = VGS - VT

W
I D = µ nCox (VGS - VTN )
1 2
2
L

62
 Ideal MOS I-V Characteristics
-4
x 10
6
VGS= 2.5 V

Linear Saturation
4
VGS= 2.0 V
IDS

VDS = VGS - VT
3
I

2
VGS= 1.5 V

1
VGS= 1.0 V

0
0 0.5 VDS
1 1.5 2 2.5

63
 Channel Length Modulation
— As VDS is increased, pinch-off point moves closer to source -
Effective channel length becomes shorter - Current increases
due to shorter channel

L' = L - DL
1 1 1 DL
-> » (1 + )
L L - DL L L

1
= (1 + lVDS )
L

I D ' = I D (1+ λVDS )

64
 MOS I/V characterstics
with
VDS = VGS-VT channel-
VGS3 length
Drain current IDS

modulation
Linear VGS2

VGS1 without
channel-length
Saturation modulation
Drain voltage VDS
65
Current-voltage equations of the
n-channel MOSFET

66
Current-voltage equations of the
p-channel MOSFET

67
 Example Problem
— Measured voltage and current data for a MOSFET are given
below. Determine the type of the device, and calculate the
parameters kn, VT0, and g. Assume fF = -0.3 V.

VGS (V) VDS (V) VSB (V) ID (µA)

3 3 0 97
4 4 0 235
5 5 0 433
3 3 3 59
4 4 3 173
5 5 3 347

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69
 MOSFET As Switch
— We can view MOS transistors as electrically controlled switches

— Voltage at gate controls path from source to drain

g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

Slid
e
70
 MOSFET As a Switch
— nMOS
o connected when gate is high
o high output is degraded

— pMOS
o connected when gate is low
o low output is degraded

72
— nMOS examples (Vtn = 0.5V)
o E.g. 1: Vg = 5V, Vi = 2V
Vo = ?
o E.g. 2: Vg = 2V, Vi = 2V
Vo = ?

— pMOS examples (Vtp = –0.5V)

o E.g. 1: Vg = 2V, Vi = 5V
Vo = ?
o E.g. 2: Vg = 2V, Vi = 2V
Vo = ?

74
— nMOS examples (Vtn = 0.5V)
o E.g. 1: Vg = 5V, Vi = 2V
Vg = 5 > Vi + Vtn = 2.5 ⇒ Vo = 2V
o E.g. 2: Vg = 2V, Vi = 2V
Vg = 2 < Vi + Vtn = 2.5 ⇒ Vo = 1.5V

— pMOS examples (Vtp = –0.5V)

o E.g. 1: Vg = 2V, Vi = 5V
Vg = 2 < Vi – |Vtp| = 4.5 ⇒ Vo = 5V
o E.g. 2: Vg = 2V, Vi = 2V
Vg = 2 > Vi – |Vtp| = 1.5 ⇒ Vo = 2.5V

75
 The Depletion MOSFET
— The physical construction of a depletion MOSFET is identical to
the enhancement MOSFET, with one exception:

— The conduction channel is physically implanted (rather than

induced)!

Implanted N-channel

76
 The Depletion MOSFET (Cont..)
— Thus, for a depletion NMOS transistor, the channel conducts even
if VGS=0.

— If the value of VGS is positive, the channel is further enhanced.

That is, more free electrons are attracted to the channel, and its
conductivity increases.

— If the value of VGS is negative, free electrons are repelled from the
channel! The conductivity of the channel is thus decreased -
channel depletion.

— If the value of VGS becomes sufficiently negative, all of the free

electrons in the channel will be repelled - the channel is said to
be completely depleted, i.e., the depletion MOSFET is in cutoff!

77
 The Depletion MOSFET (Cont..)
— Thus, the negative value of VGS at which the channel is completely
depleted is the threshold voltage VT for a depletion NMOS device.

— In other words, to have a conducting channel, the gate-to source

voltage VGS must be greater than the threshold voltage VT: (Just
like the enhancement NMOS device!)
VGS > VT

78
 The Depletion MOSFET (Cont..)
— An enhancement MOSFET and a depletion MOSFET are precisely
identical in nearly every way (e.g., same modes, same equations,
same terminal names).

— 2 differences:
o The threshold voltage for a depletion NMOS device is negative (i.e., VT
< 0). While the threshold voltage for a depletion PMOS device is
positive (i.e., VT > 0).
o The depletion MOSFET has a slightly different circuit symbol.

Depletion NMOS Depletion PMOS

79
 MOSFET SCALING –
INTRODUCTION
— MOS ICs have met the world’s growing needs for electronic
devices for computing, communication, entertainment,
automotive, and other applications with steady improvements in
cost, speed, and power consumption.

— Such steady improvements in turn stimulate and enable new

applications and fuel the growth of IC sales.

— If the MOSFET can continue this trend of continuous

improvement.

— The off-state current or the leakage current of the MOSFETs.

80
 Technology Scaling - Small is
Beautiful
— Since the 1960’s the price of one bit of semiconductor memory
has dropped 100 million times and the trend continues.

— The cost of a logic gate has also undergone a similarly dramatic

drop.

— This is because of “miniaturization”.

o By making the transistors and the interconnects smaller, more
circuits can be fabricated on each silicon wafer and therefore each
circuit becomes cheaper.
o Speed and power consumption also reduced.

81
 Technology Scaling (Cont..)
— The “Moore’s Law” - Gordon Moore made an empirical
observation in the 1960’s that the number of devices on a chip
doubles every 18 months.

— Each time the minimum metal line width is reduced, a new

technology generation or technology node is introduced.
o Eg: 0.18mm, 0.13mm, 90nm, 65nm, 45nm…generations. The
numbers refer to the minimum metal line width.

— At each new node, the various feature sizes of circuit layout, such
as the size of contact holes, are 70% of the previous node.
o i.e., the circuit size is reduced by 2. (70% of previous line width
means ~50% reduction in area, i.e. 0.7 x 0.7= 0.49.)
o Since nearly twice as many circuits can be fabricated on each wafer
with each new technology node, the cost per circuit is reduced
significantly.

82
— With scaling
o Line width, MOSFET gate oxide thickness and the power supply
voltage reduces.
o The reductions are chosen such that the transistor current density
(Ion/W) increases with each new node.

— The smaller the transistors and shorter the interconnects lead to

smaller capacitances.
o This causes the circuit delays to drop.
o Integrated circuit speed has increased almost 30% at each new
technology node

83
— The reducing capacitance and, especially, the power supply
voltage lowers the power consumption.
o Due to these reduction in C and Vdd, power consumption per chip has
increased only modestly per node in spite of the rise in switching
frequency, f and the doubling of transistors per chip at each
technology node.

— If there had been no scaling, doing the job of a single PC

microprocessor chip-- running 500M transistors at 2GHz using
1970 technology would require the electrical power output of a
medium-size power generation plant.

84
 ITRS
International Technology Roadmap for Semiconductors (ITRS)
presents the industry’s annually updated projection of future
technologies and challenges

Shrinking Device Dimensions

Increasing Function Density

Increasing Clock Frequency

Decreasing Supply Voltage

85
 Scaling
— Due to a phenomenon called “scaling”

— Reduce physical dimensions such as channel length (L), width

(W) and gate oxide thickness (tox) are scaled

86
 Effects of Scaling
— If fields are not controlled properly,
o One dimension field nature in channel become multi-dimensional
o Channel charge is also controlled by drain/source voltage
o Long channel effect is lost

— Long channel device behavior è Physical dimension is not

important however, it is the electrical dimension

88
 Types of Scaling
— Traditionally Two types
o Constant Voltage Scaling
o Constant Field Scaling

— Constant voltage scaling: voltages in the device are kept constant

à fields increase exponentially causing breakdown

— Constant field/full scaling: fields in the device are kept constant

à reduction in applied voltage means takes more time to load
parasitics and thus is slower

89
 MOS Scaling
How is Doping Density Scaled?
— Parameters affected by substrate doping density:
o The depths of the source and drain depletion regions
o Possibly the depth of the channel depletion region
o Possibly VT.

— Channel depletion region and VT are not good candidates for

deriving general relationships since channel implants are used to
tune VT.

— Thus, focus our argument on depletion region depth of the

source and drain which is given by:

2ε si N A + N D kT " N A N D %
xd = Vbi − V where, Vbi = ln $ 2 '
q NA • ND q # ni &

91
 MOS Scaling
How is Doping Density Scaled? (Cont..)
— Assuming NA small compared to ND and Vbi small compared to V
(the reverse bias voltage which ranges from 0 to –VDD),
1
xd ∝ V
NA
— Assuming constant voltage scaling with scaling factor S, xd scales
as follows:
1 1 1 1 1
xd ∝ V = 2
V
S S NA S NA
— Thus, for constant voltage scaling, NA => S2NA, and ND => S2ND

— On the other hand, for full scaling, VA => V/S giving:

1 1 1 1 1 1 V
xd ∝ V = V =
S S NA S2 NA SN A S
— Thus, for full scaling, NA => SNA, and ND => SND
92
Parameters Affected in Scaling

93
Parameters Affected in Scaling

94
Parameters Affected in Scaling

95
 Generalized Scaling
— The supply voltages, while moving downwards, are not scaling as fast
as the technology
o Some of the intrinsic device voltages such as the silicon bandgap and the
built-in junction potential, are material parameters and cannot be scaled.
o The scaling potential of the transistor threshold voltage is limited. Making
the threshold too low makes it difficult to turn off the device completely.

— Therefore, a more general scaling model is needed, where

dimensions and voltages are scaled independently.

— Here, device dimensions are scaled by a factor S , while voltages are

reduced by a factor U.

— When the voltage is held constant, U = 1, and the scaling model

reduces to the fixed-voltage model.

— The general-scaling model offers a performance scenario identical to

the full- and the fixed scaling, while its power dissipation lies
between the two models (for S > U > 1).

96
 Short Channel Effects (SCE)
— Velocity saturation
— Vth roll-off
— Channel Length Modulation (CLM)
— Drain Induced Barrier Lowering (DIBL)
— Subthreshold Conduction
— Punch through
— Hot carrier degradation
— Gate Induced Drain Lowering (GIDL)
— Source-drain series resistance
— Gate oxide leakage (GOX Leakage)

100
 Velocity saturation
— Electric fields can get quite large in short channel devices. Our
simple mobility model does not work.
— If velocity of carriers becomes large enough, they can lose energy
by inelastic processes (e.g. shedding optical phonons).
— If L is long compared to the inelastic scattering length, one sees
velocity saturation
— Drift velocity of carriers (vd) saturates and becomes a constant
vdSAT = 107 cm/s for electrons and 8×106 cm/s for holes.

101
 µs E
v=
E
1+
Esat
E << Esat : v = µ s E
E >> Esat : v = µ s Esat

102
 Carrier velocity saturation
— Field along channel - As channel length is reduced, electric field
increases (if voltage is constant).

— Electron drift velocity is proportional to electric field only for

small field values - For large electric field, velocity saturates.

— Current saturates before “saturation region” – Drain current is

reduced.

103
— With VDD being fixed and as L becomes small,
o This reduces IDSAT which now depends linearly on VG–VT rather than
almost quadratically..

VDsat
vdsat = µ n Esat = µ n
L
W " 2
VDSat %
I Dsat = µ nCox $(VGS − VT )VDSat − '
L # 2 &
" V %
= WCox vdsat $VGS − VT − DSat '
# 2 &

104
 Velocity Saturation Effects
— For short channel devices and large enough VGS – VT
o VDSat < VGS – VT so the device enters saturation before VDS reaches VGS
– VT and operates more often in saturation
o IDSat has a linear dependence on VGS so current reduces for a given
control voltage

105
106
VDS = 2.5V, W/L = 1.5
107
 Drain Induced Barrier Lowering
(DIBL)
— If the gate bias voltage is not sufficient to invert the surface, i.e., VGS
< VT, the carriers (electrons) in the channel face a potential barrier
that blocks the flow.

— Increasing the gate voltage reduces this potential barrier and,

eventually, allows the flow of carriers under the influence of the
channel electric field.

— The potential barrier is controlled by both VGS and VDS.

— In long channel devices, the gate is completely responsible for
depleting the semiconductor (QB).

— In very short channel devices, part of the depletion is accomplished

by the drain and source bias.

— If the drain voltage is increased, less gate voltage is required to

deplete QB, and the barrier for electron injection from source to drain
decreases. This is known as drain induced barrier lowering (DIBL).

108
— DIBL results in an increase in drain current at a given VG.
Therefore VT↓ as L↓.

— Similarly, as VD↑, more QB is depleted by the drain bias, and

hence ID↑ and VT↓.

109
 Punch Through
— If the channel length becomes too short, the depletion region
from the drain can reach the source side and reduces the barrier
for electron injection. This is known as punch through.

— Drain current no longer controlled by gate

— Transistors won’t “turn off”

110
 Sub-threshold Current
— Circuit speed improves with increasing Ion, therefore it would be
desirable to use a small Vt.

— Vt must not be set too low, say 10mV, otherwise Ioff would be too
large.

— At Vgs < Vt, an N-channel MOSFET is in the off-state. However, an

undesirable leakage current can flow between the drain and the
source.

— The MOSFET current observed at Vgs<Vt is called the subthreshold

current.

— This is the main contributor to the MOSFET off-state current, Ioff. Ioff is
the Id measured at Vgs = 0 and Vds = Vdd.

— In the absence of a conducting channel, the n+ (source) – p (bulk) –

n+ (drain) terminals actually form a parasitic bipolar transistor.

116
 Sub-threshold Current
— The sub-threshold can be
approximated as VGS " − DS %
V
nkT /q kT /q
ID = ISe $1− e '
# &

• It is important to keep Ioff very small in order to minimize the

static power that a circuit consumes even when it is in the
standby mode.
• For example, if Ioff is a modest 100nA per transistor, a cell-phone chip
containing one hundred million transistors would consume so much
standby current (10A) that the battery would be drained in minutes without
receiving or transmitting any calls.

117
 MOSFET Capacitance
— 2 Types
o Oxide-related capacitances
o Junction capacitances

119
Cross-sectional view and top view of
a typical n-channel MOSFET.

120
 Oxide-related/Overlap
Capacitances
— Source and drain extend somewhat below the oxide by an
amount LD , called the lateral diffusion

— It gives rise to a parasitic capacitance between gate and source

(drain) that is called the overlap capacitance.

— The two overlap capacitances are called CGDO and CGSO.

CGSO = CoxWLD Cox = εox/tox

CGDO = CoxWLD

— These overlap capacitances are voltage-independent.

121
 Channel Capacitance
— The most significant MOS parasitic circuit element is the gate-to-
channel capacitance CGC.

— CGC varies in both magnitude and in its division into three

components CGCS, CGCD and CGCB (the gate-to-source, gate-to-
drain, and gate-to-body capacitances) depending upon the
operation region and terminal voltages

122
 Transistor in Cut-off
— When the transistor is off, no carriers in channel to form the other
side of the capacitor.
o Substrate acts as the other capacitor terminal
o The total capacitance CGC = W.L.Cox appears between gate and body
o Capacitance becomes series combination of gate oxide and depletion
capacitance

123
 Transistor in Linear Region
— Channel is formed and acts as the other terminal
o CGCB drops to zero (shielded by channel)

— Model by splitting oxide cap equally between source and drain,

CGCS = CGCD = WLCox/2.
o Changing either voltage changes the channel charge

124
 Transistor in Saturation Region
— Changing source voltage doesn’t change VGC uniformly
o E.g. VGC at pinch off point still VTH

— Bottom line: CGCS ≈ 2/3·W·L·Cox

— Drain voltage no longer affects channel charge
o Set by source and VDSat

— If change in charge is 0, CGCD = 0

125
Oxide Capacitance

126
 Channel capacitance of MOS
transistor for different operation
regions
Operation
CGCB CGCS CGCD CGC CG
Region
Cutoff CoxWL 0 0 CoxWL CoxWL + 2COXWLD

Resistive 0 CoxWL/2 CoxWL/2 CoxWL CoxWL + 2COXWLD

Saturation 0 (2/3)CoxWL 0 (2/3)CoxWL (2/3)CoxWL + 2COXWLD

128
 Junction Capacitance
— This capacitive component is contributed by the reverse-biased
source-body and drain-body pn junctions.

— The depletion-region capacitance is nonlinear and decreases

when the reverse bias is raised.

129
 Junction Capacitance

— Bottom Junction
o which is formed by the source region (with doping ND) and the substrate
with doping NA
o Area cap
o Cbottom = Cj·LS·W, Cj the junction capacitance per unit area

130
— Side-wall junction
o formed by the source region with doping ND and the p+ channel-stop
implant with doping level NA+.
o The doping level of the stopper is usually larger than that of the
substrate, resulting in a larger capacitance per unit area. Its
capacitance value equals
Csw = C'jsw xj (W+2Ls)
where, capacitance per unit perimeter Cjsw = C'jswxj
o No side-wall capacitance is counted for the fourth side of the source
region, as this represents the conductive channel.

— No side-wall capacitance is counted for the fourth side of the

source region, as this represents the conductive channel

131
 Capacitance Model Summary
— Gate-Channel Capacitance
o CGC ≈ Cox·W·L (|VGS| < |VT|)
o CGC = Cox·W·L (Linear)
— 50% G to S, 50% G to D
o CGC = (2/3)·Cox·W·Leff (Saturation)
— 100% G to S

— Gate Overlap Capacitance

o CGSO = CGDO = Cox·W.LD (Always)

— Total Junction/Diffusion Capacitance

o Cdiff = Cbottom + Csw = Cj x AREA + Cjsw x PERIMETER
= Cj·LS·W + Cjsw·(2LS + W) (Always)
— Cs-diff = Cs-bottom + Cs-sw = Cj x Source Bottom Area+ Cjsw x (2LS + W) of the source
side
— Cd-diff = Cd-bottom + Cd-sw = Cj x Drain Bottom Area+ Cjsw x (2LS + W) of the drain side

135
Capacitive Device Model
CGS = CGCS + CGSO

CGD = CGCD + CGDO

CGB = CGCB

CSB = Csdiff

CDB = Cddiff

CS = CGS + CSB

CD = CGD + CDB

137
 Example
— Compute the gate capacitances for an NMOS transistor. Assume
that drain and source areas are rectangular, and are 1 μm wide
and overlap is 0.5 μm long. W/L = 1/0.25. Oxide Capacitance is 6
fF/μm2.
o a. VGS = 2.5 V, VDS = 2.5 V, 0.5 V
o b. VGS = 0 V, VDS = 2.5 V, 0.5 V

138
 Example
— Consider the n-channel enhancement-type MOSFET shown below. The
process parameters are given as follows:

Both the source and the drain diffusion regions are surrounded by p+ channel-stop
diffusion. The substrate is biased at 0 V. Assuming that the drain voltage is changing
from 0.5 V to 5 V, find the average drain-substrate junction capacitance Cdb
139
 MOSFET RC Model
— Modeling MOSFET resistance and capacitance is very important for
transient characteristics of the device.

RC Model

— Time constant at drain, τD = CDRn

— Drain-Source (channel) Resistance, Rn
o Rn=VDS/ID
o Linear region
— Rn = 1/[βn (VGS-Vtn)]
o Saturation region
— Rn = 2VDS/[βn (VGS-Vtn)2]

154
 Transistor Sizing
— Channel Resistance
o “ON” resistance of transistors
1 1
Rn = Rp =
!W $ !W $
µ nCox # & (VGS − VTn ) µ pCox # & (VSG − VTp )
" L %n " L %p
Cox = ε ox / tox [F/cm 2 ], process constant

— Channel Resistance Analysis

o R ∝ 1/W (increasing W decreases R & increases Current)
o R varies with Gate Voltage
o If Vtn ≈ |Vtp|, Rn = µ p (W L ) p
Rp µ n (W L )n
— If (W/L)n = (W/L)p, then Rn < Rp
o Since μn > μp
o To match resistance, Rn = Rp
— adjust (W/L)n = (W/L)p to balance for μn > μp

155
 Transistor Sizing (Cont…)
— Matching Channel Resistance
o there are performance advantage to setting Rn = Rp
o To set Rn = Rp
— define mobility ratio, r = μn /μp

(W L ) p
= r (W L )n
(W L ) p µn
=
(W L ) n
µp
o pMOS must be larger than nMOS for same resistance/current

— Negative Impact
o CGp = rCGn
o larger gate = higher capacitance

156