LAB FILE OF

DIGITAL ELECTRONICS AND COMPUTER ORGANIZATION

(CSE207)

SUBMITTED BY: SUBMITTED TO:

NAME: Nirbhay Kashyap
CLASS:
ENROLLMENT NUMBER:

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

AMITY SCHOOL OF ENGINEERING AND TECHNOLOGY
AMITY UNIVERSITY, NOIDA
SESSION: ODD SEM(2024-25)
 INDEX

S.NO EXPERIMENT NAME SIGNATURE

1. Simulation using ORCAD

2. To implement logic gates.

3. To simulate half adder circuit.

4. To simulate full adder circuit.

5. To simulate half subtractor circuit.

6. To simulate full subtractor circuit.

7. To implement digital comparator circuit.

8. To implement binary adder/subtractor

circuit.

9. To implement binary incrementor circuit.

10. To implement logical part of a simple

Arithmetic logical unit

11. To simulate one digit BCD Adder.

12. To simulate and study the tristate buffer.

13. To simulate the common bus using tri-

state buffers and decoder.

14. To simulate the common bus using

multiplexers.

15. To study 8085 microprocessors.

EXPERIMENT- 1
AIM: Simulation using ORCAD
THEORY:
ORCAD is a popular software used in electronics for designing, simulating, and analyzing
both analog and digital circuits. In this experiment, we focus on digital circuit simulation
using PSpice, a key part of ORCAD that helps verify circuit behavior before creating
physical hardware. This tool is vital for engineers because it allows circuits to be tested and
optimized virtually, saving time and reducing costs.

Key Concepts:
• Combinational Circuits: These circuits, such as AND, OR, and NOT gates, give
outputs based solely on their current inputs.

• Sequential Circuits: These circuits, like flip-flops and counters, depend on both
current inputs and previous states. They often use clock signals to control changes in
the system.

Simulation Process in ORCAD:

1. Schematic Capture:
• Design the circuit by placing and connecting logic components like gates and flip-
flops.
2. Simulation Setup:
• Define input signals, test conditions, and choose simulation models.
3. Run Simulation:
• Analyze the output waveforms or values to ensure the circuit performs correctly.
4. Result Analysis:
• Verify if the circuit meets the desired logic and timing specifications. If issues are
detected, make necessary adjustments to improve performance.

Benefits of Using ORCAD for Digital Circuit Simulation:

• Early Error Detection: Simulation allows engineers to spot design flaws early,
such as timing issues or incorrect logic. This reduces the risk of costly errors during
the hardware implementation phase.

• Cost and Time Savings: Virtual testing means you can modify and optimize
circuits without needing physical prototypes.
 • Efficient Design Process: Engineers can visualize real-time circuit behavior and
make changes quickly, streamlining the development process.

Conclusion:
This experiment provides a hands-on understanding of how to simulate digital circuits using
ORCAD, including combinational and sequential logic systems. The use of PSpice for
simulation helps ensure that the circuits perform as expected and meet design requirements
before moving to actual hardware implementation. This approach is essential in modern
electronics design, as it enhances the reliability and efficiency of the development process.
EXPERIMENT-2
AIM: To study logic gates (AND, OR, NOT, NAND, NOR, XOR, XNOR)
THEORY:
The experiment with logic gates demonstrates their fundamental operations in digital circuits.
Each gate performs a specific logical function, allowing for the construction of complex
circuits. Understanding their behavior, represented by truth tables and Boolean expressions, is
crucial for digital design. Universal gates like NAND and NOR can replicate any other gate,
highlighting their significance in building optimized circuits.
- AND GATE
If any input is low, the output is low.

- OR GATE
If any input is high, the output is high.

- NOT GATE
The output will be complement to the input.

- NAND GATE
If any input is low, the output will be high.
-NOR GATE
If any input is high, then the output will be low.

- Ex-OR GATE
If both inputs are same, the output is low.

- Ex-NOR GATE
If both inputs are same, the output is high.

TRUTH TABLE:
AND GATE
INPUT OUTPUT
A B X=A.B
0 0 0
0 1 0
1 0 0
1 1 1

OR GATE:
INPUT OUTPUT
A B X=A+B
0 0 0
0 1 1
1 0 1
1 1 1
NOT GATE:
INPUT OUTPUT
A A'
1 0
0 1

NAND GATE:
INPUT OUTPUT
A B X=(A.B)'
0 0 1
0 1 1
1 0 1
1 1 0

NOR GATE:
INPUT OUTPUT
A B X=(A+B)'
0 0 1
0 1 0
1 0 0
1 1 0

EX-OR GATE:
INPUT OUTPUT
A B Y=(A'B+B'A)
0 0 0
0 1 1
1 0 1
1 1 0
EX-NOR GATE:
INPUT OUTPUT
A B Y=AB+(A'B')
0 0 1
0 1 0
1 0 0
1 1 1
CIRCUIT DIAGRAM:
AND GATE:

OR GATE:
NOT GATE:

NAND GATE:

NOR GATE:
EX-OR GATE:

EX-NOR GATE:
EXPERIMENT-3
AIM: To implement half adder circuit.
THEORY:
Adders are digital circuits that carry out addition of numbers. Adders are a key component of
arithmetic logic unit. Adders can be constructed for most of the numerical representations like
Binary Coded Decimal (BCD), Excess – 3, Gray code, Binary etc. out of these, binary
addition is the most frequently performed task by most common adders. Apart from addition,
adders are also used in certain digital applications like table index calculation, address
decoding etc.

The Half Adder is a basic combinational circuit used to perform the addition of two single-bit
binary numbers. It has two inputs, typically labeled `A` and `B`, and two outputs: Sum and
Carry. The Sum output is generated using an XOR gate, while the Carry output is obtained
using an AND gate. The Half Adder does not account for carry input from a previous stage,
making it suitable for adding the least significant bits in binary addition. This circuit is
foundational for building more complex adders like Full Adders, which are used in arithmetic
operations.
STATEMENT: It is a logic circuit that adds two input digits and generates the output in the
form of carry and sum.

TRUTH TABLE:

INPUT OUTPUT
A B SUM(S) CARRY(C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
CIRCUIT DIAGRAM:
EXPERIMENT-4
AIM: To implement full adder circuit.
THEORY:
A full adder is a digital circuit that adds three binary digits: two main bits (A and B) and a
carry-in bit (Cin). It produces two outputs: the sum (S) and the carry-out (Cout). The sum is
calculated using XOR on the three inputs, handling the binary addition without a carry. The
carry-out is determined using AND and OR gates, which account for cases where the sum
exceeds 1. Full adders are key components in arithmetic logic units, allowing multi-bit
addition by linking several full adders to process larger numbers.

Statement: It is a logic circuit that produces a two-bit output, sum and carry, from three input
bits.

TRUTH TABLE:
INPUT OUTPUT
A B Cin SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
CIRCUIT DIAGRAM:
EXPERIMENT-5
AIM: To implement half subtractor circuit.
THEORY:
The Half Subtractor is a combinational circuit used to subtract two single-bit binary numbers,
`A` and `B`. It has two outputs: Difference and Borrow. The Difference is calculated using an
XOR gate, and the Borrow is determined using an AND gate with an inverted input. The Half
Subtractor does not handle a borrow from the previous stage, making it suitable only for
subtracting the least significant bits. This circuit forms the basis for building more complex
subtractors like Full Subtractors, used in multi-bit binary subtraction.
STATEMENT: It is a logic circuit that subtracts two input digits and generates the output in
the form of difference and borrow.

TRUTH TABLE:
INPUT OUTPUT
X Y DIFFERENCE BORROW
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

CIRCUIT DIAGRAM:
EXPERIMENT-6
AIM: To implement full subtractor circuit.
THEORY:
A full subtractor is a combinational circuit that performs subtraction involving three bits,
namely A (minuend), B (subtrahend), and Bin (borrow-in). It accepts three inputs: A
(minuend), B (subtrahend) and a Bin (borrow bit) and it produces two outputs: D (difference)
and Bout (borrow out). The logic symbol and truth table are shown below.

D = A ⊕ B ⊕ Bin
Bout = A' Bin + A' B + B Bin

TRUTH TABLE:
X Y Z(Bin) DIFFERENCE BORROW(Bout)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
CIRCUIT DIAGRAM:
EXPERIMENT-7
AIM: To implement digital comparator circuit.
THEORY:
A digital comparator is a combinational logic circuit used to compare two binary numbers
and determine their relative magnitudes. It outputs signals indicating whether one number is
greater than, less than, or equal to the other. The comparison is performed by analyzing the
bits of both numbers simultaneously using logic gates. The most common comparators are 1-
bit and multi-bit types. In a multi-bit comparator, the circuit consists of a series of full
subtractors or logic gates that compare corresponding bits, starting with the most significant
bit (MSB) and moving toward the least significant bit (LSB).

The outputs generally indicate "A > B," "A < B," or "A = B." The equality condition is
typically determined using XOR gates, while the greater-than and less-than conditions are
derived through combinations of AND, OR, and NOT gates based on the comparison results
of each bit. Digital comparators are essential components in systems like arithmetic logic
units (ALUs), digital signal processors, and decision-making circuits in computing and
control systems, where quick and accurate comparisons between binary values are needed.

TRUTH TABLE:

INPUT OUTPUT
A B A<B A=B A>B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
CIRCUIT DIAGRAM:
EXPERIMENT-8
AIM: To implement binary adder/subtractor circuit.
THEORY:
A Binary Adder-Subtractor is one which is capable of both addition and subtraction of binary
numbers in one circuit itself. The operation being performed depends upon the binary value
the control signal holds. It is one of the components of the ALU (Arithmetic Logic Unit).
A 4-bit binary full adder accepts two 4-bit binary words A3, A2, A1, A0 and B3, B2, B1, B0
and a carry input (C0) as inputs and produces a 4-bit binary sum output S3, S2, S1, S0 and a
carry output C4.

To implement a 4 bit adder/subtractor using 2's complement number system. If ADD/SUB =

"0" normal addition S = A + B is performed. On the other hand if ADD/SUB = "1" then S = A
+ [B] + 1 where [B] = 1's complement of B. For example, if A = 0111 and B = 0101 then [B]
= 1010 and S = 0010 or 2 neglecting carry out C4. If however A = 0101 and B = 0111 then B
= 1000; or S = 1110 which represents -2 in 2's complement number system.
CIRCUIT DIAGRAM:
ADDITION(M=0) OF 1100 AND 0111

SUBTRACTION(M=1) OF 1100 AND 0111

EXPERIMENT-9
AIM: To implement 4 bit binary incrementor circuit.
THEORY:
A binary incrementor is a digital circuit designed to increase a binary number by one. It
works by evaluating each bit of the number, starting with the least significant bit (LSB). If the
LSB is 0, it is simply changed to 1, and the operation is complete. However, if the LSB is 1, it
is flipped to 0, and a carry is passed to the next bit. This process continues through the bits,
with the carry moving forward until a 0 is encountered, which is then flipped to 1, completing
the increment.

The circuit is commonly constructed using a series of full adders, which manage both the
addition of bits and the propagation of the carry signal. The carry moves through each bit
position, ensuring the correct binary increment. For larger binary numbers, a lookahead carry
mechanism may be employed to reduce delay and enhance operational efficiency, allowing
the circuit to perform faster by predicting the carry propagation in advance. Binary
incrementors are essential in counters, arithmetic operations, and various digital systems
requiring precise value adjustments.

CIRCUIT DIAGRAM:
EXPERIMENT-10
AIM: Simulation of one digit BCD Adder.

THEORY:

BCD stand for binary coded decimal. Suppose we have two 4-bit numbers A and B. The
value of A and B can varies from 0(0000 in binary) to 9(1001 in binary) because we are
considering decimal numbers.

A 4-bit binary adder that is capable of adding two 4-bit words having a BCD (binary-coded
decimal) format. The result of the addition is a BCD-format 4-bit output word, representing
the decimal sum of the addend and augend, and a carry that is generated if this sum exceeds a
decimal value of 9. Decimal addition is thus possible using these devices.
If the sum of two number is less than or equal to 9, then the value of BCD sum and binary
sum will be same otherwise they will differ by 6(0110 in binary). Now, let’s move to the table
and find out the logic when we are going to add “0110”.
CIRCUIT DIAGRAM:
EXPERIMENT-11
AIM: To implement the logical part of a simple Arithmetic logical unit.
THEORY:
An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic
operations. It represents the fundamental building block of the central processing unit (CPU)
of a computer. Modern CPUs contain very powerful and complex ALUs. In addition to
ALUs, modern CPUs contain a control unit (CU).
The purpose of the ALU is to perform mathematical operations such as addition, subtraction,
multiplication and division. Additionally, the ALU processes basic logical operations like
AND/OR calculations. It serves as the computational hub of the Central Processing Unit
(CPU) for a computer system.
Input = M0,M1(select lines) & Output = Operation

Now you can take up the 1 bit ALU as block and construct a 4 bit ALU, which performs all
the functions of the 1 bit ALU on the 4 bit inputs. Thus a single building block can be
constructed and used recursively. The inputs A and B are four bits and the output is 4 bit as
well. Figure below illustrates it:
CIRCUIT DIAGRAM:
EXPERIMENT-12
AIM: To simulate and study the tristate buffer.
THEORY:
A Tri-state Buffer can be thought of as an input controlled switch with an output that can be
electronically turned “ON” or “OFF” by means of an external “Control” or “Enable” ( EN )
signal input. This control signal can be either a logic “0” or a logic “1” type signal resulting
in the Tri-state Buffer being in one state allowing its output to operate normally producing the
required output or in another state were its output is blocked or disconnected.
Then a tri-state buffer requires two inputs. One being the data input and the other being the
enable or control input as shown.
Tri-state Buffer Switch Equivalent

When activated into its third state it disables or turns “OFF” its output producing an open
circuit condition that is neither at a logic “HIGH” or “LOW”, but instead gives an output
state of very high impedance, High-Z, or more commonly Hi-Z. Then this type of device has
two logic state inputs, “0” or a “1” but can produce three different output states, “0”, “1” or
” Hi-Z ” which is why it is called a “Tri” or “3-state” device.
Note that this third state is NOT equal to a logic level “0” or “1”, but is an high impedance
state in which the buffers output is electrically disconnected from the rest of the circuit. As a
result, no current is drawn from the supply.
There are four different types of Tri-state Buffer, one set whose output is enabled or disabled
by an “Active-HIGH” control signal producing an inverted or non-inverted output, and
another set whose buffer output is controlled by an “Active-LOW” control signal producing
an inverted or non-inverted output as shown below.
TRUTH TABLE:
ENABLE A B
0 0 X
0 1 X
1 0 0
1 1 1

CIRCUIT DIAGRAM:
EXPERIMENT-13
AIM: To simulate the common bus using tri-state buffers and decoder.
THEORY:
A common bus using tri-state buffers, and a decoder serves as a shared communication
pathway that enables multiple devices, such as registers or memory units, to connect and
communicate over the same set of lines without interference. This architecture is fundamental
in digital systems, as it efficiently manages data transfer among various components while
preventing signal conflicts.
Tri-state buffers are crucial components in this setup, as they are connected to each device's
output and control when that device can send data to the bus. Each buffer can operate in one
of three states: transmitting a logic `0`, transmitting a logic `1`, or being in a high-impedance
state, which effectively disconnects it from the bus. This design ensures that only one device's
buffer is enabled at any given time, allowing that device to place its data onto the bus while
keeping all other buffers in high-impedance mode. This prevents signal conflicts and ensures
reliable data transmission.
The decoder plays a vital role in managing which device can place its data on the bus. It takes
a binary input known as selection lines and activates one of its outputs corresponding to a
specific device. This output controls the enabled inputs of the tri-state buffers. When the
decoder selects a device based on the provided binary address, it enables the corresponding
buffer, allowing the device's data to drive onto the bus. Consequently, all other buffers remain
in the high-impedance state, effectively disconnecting them from the bus and ensuring that
only the selected device is actively communicating.
In summary, the common bus system facilitates efficient data sharing among multiple devices
by utilizing tri-state buffers and a decoder. The architecture supports seamless data transfer
by selecting the appropriate device for communication while preventing interference from
inactive devices, making it a fundamental aspect of digital circuit design.
A common bus system is scalable, enabling easy addition or removal of devices without
redesign. Control signals manage the decoder to prevent bus contention by ensuring only one
tri-state buffer is active at a time. Timing is crucial for data integrity, often utilizing
synchronization mechanisms. This architecture is prevalent in modern systems, including
microcontrollers and FPGAs, and may include error detection to maintain data accuracy,
enhancing the robustness of digital designs.
CIRCUIT DIAGRAM:
EXPERIMENT-14
AIM: To simulate the common bus using multiplexers.
THEORY:
A common bus system using multiplexers serves as a crucial communication pathway that
enables multiple data sources to share a single output line. In this configuration, multiplexers
(MUX) are used to select which data source is connected to the bus based on control signals.
Each data source is connected to one of the MUX inputs, and the MUX outputs the selected
input to the common bus. This method efficiently manages data transfer, allowing only one
data source to communicate with the bus at a time while isolating the others.
The operation of a multiplexer is based on its ability to route data from multiple inputs to a
single output, controlled by selection lines. The selection lines determine which input is
directed to the output, effectively enabling the bus to carry data from the chosen source. For
instance, a 4-to-1 multiplexer has four inputs and two selection lines, allowing it to connect
any one of the four inputs to the output, thus facilitating the sharing of data among multiple
devices.
Using multiplexers in a common bus architecture helps prevent data collisions that could
occur if multiple devices attempted to drive the bus simultaneously. By ensuring that only
one input is active at a time, multiplexers maintain data integrity and simplify the design of
complex digital systems. This architecture is widely used in computer systems, allowing
various components like registers, memory units, and input/output devices to communicate
effectively over a shared bus. Overall, the use of multiplexers in a common bus design
enhances efficiency and simplifies data management in digital circuits.
TRUTH TABLE:

CIRCUIT DIAGRAM:
EXPERIMENT-15
AIM: To study the 8085 microprocessor.
THEORY:
The Intel 8085 is an 8-bit microprocessor introduced by Intel in 1977. It was binary
compatible with the more-famous Intel 8080 but required less supporting hardware, thus
allowing simpler and less expensive microcomputer systems to be built. The "5" in the model
number came from the fact that the 8085 requires only a +5-Volt (V) power supply rather
than the +5 V, −5 V and +12 V supplies the 8080 needed. The main features of 8085 μP are:
- It is an 8-bit microprocessor.
- It is manufactured with N-MOS technology.
- It has 16-bit address bus and hence can address up to 216= 65536 bytes (64KB) memory
locations through A0–A15.
- The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0–AD7
- Data bus is a group of 8 lines D0–D7.
- It supports external interrupt request.
- A 16-bit program counter (PC)
- A 16-bit stack pointer (SP)
- Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
- It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock.
- It is enclosed with 40 pins DIP (Dual in line package).

8085 consists of various units as shown in Fig. 1 and each unit performs its own functions.
The various units of a microprocessor are listed below:
Accumulator: A special register used to store the results of arithmetic and logical
operations.

Arithmetic and Logic Unit (ALU): Performs all arithmetic (addition, subtraction) and
logical (AND, OR, NOT) operations.

General Purpose Registers: Temporary storage for data and operands; includes registers B,
C, D, E, H, and L.

Program Counter (PC): Holds the address of the next instruction to be executed, guiding
the microprocessor's execution flow.

Stack Pointer (SP): Points to the top of the stack, used to store return addresses and data
temporarily during function calls.

Temporary Register: A non-user-accessible register used internally by the processor for

intermediate results.

Flags: A set of status bits (such as Zero, Carry, Sign, etc.) that reflect the outcome of ALU
operations.

Instruction Register and Decoder: The instruction register holds the current instruction,
while the decoder interprets the instruction and initiates the necessary operations.

Timing and Control Unit: Generates timing signals and controls the operations of the
microprocessor, coordinating communication with external devices.

Interrupt Control: Manages interrupts (external signals) to temporarily halt the current
process and execute a high-priority task.

Address Buffer and Address-Data Buffer: Temporarily holds addresses and data before
transferring them between the processor and external memory or peripherals.

Address Bus: Carries memory addresses from the microprocessor to other components
(unidirectional).

Data Bus: Transfers actual data between the microprocessor, memory, and input/output
devices (bidirectional).

These components work together to process and execute instructions within the 8085
microprocessor system.