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LAB Report 4 (AC)

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LAB Report 4 (AC)

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© © All Rights Reserved
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AMERICAN INTERNATIONAL UNIVERSITY BANGLADESH

Faculty of Engineering
Laboratory Report Cover Sheet

Students must complete all details except the faculty use part.

Please submit all reports to your subject supervisor or the office of the concerned faculty.

Laboratory Title:
Experiment Number: Due Date: Semester:
Subject Code: EEE Subject Name: Section:
Course Instructor: Degree Program:

Declaration and Statement of Authorship:


1. I/we hold a copy of this report, which can be produced if the original is lost/ damaged.
2. This report is my/our original work and no part of it has been copied from any other student’s work or from
any other source except where due acknowledgement is made.
3. No part of this report has been written for me/us by any other person except where such collaboration has
been authorized by the lecturer/teacher concerned and is clearly acknowledged in the report.
4. I/we have not previously submitted or currently submitting this work for any other course/unit.
5. This work may be reproduced, communicated, compared and archived for the purpose of detecting
plagiarism.
6. I/we give permission for a copy of my/our marked work to be retained by the School for review and
comparison, including review by external examiners.
I/we understand that
7. Plagiarism is the presentation of the work, idea or creation of another person as though it is your own. It is a
form of cheating and is a very serious academic offence that may lead to expulsion from the University.
Plagiarized material can be drawn from, and presented in, written, graphic and visual form, including
electronic data, and oral presentations. Plagiarism occurs when the origin of the material used is not
appropriately cited.
8. Enabling plagiarism is the act of assisting or allowing another person to plagiarize or to copy your work

Group Number (if applicable): Individual Submission Group Submission

No. Student Name Student Number Student Signature Date


Submitted by:
1 Jahidul Hoque Jewel 20-43382-1
Group Members:
2 Ajijol Haque Bhuiyan Badhon 23-55302-3
3 Taohidul Islam 23-55382-3
4 Washimul Hasan Nibir 23-55458-3
5

For faculty use only:


Total Marks: Marks Obtained:

Faculty comments
Objective:

The objective of this report is to analyze and verify key electrical circuit theorems through both
practical experimentation and theoretical calculations. Specifically, the report aims to determine the
Thevenin’s equivalent circuit for a given electrical network and measure the load voltage and load
current to validate theoretical predictions. Additionally, it investigates the application of the
superposition theorem to circuits with multiple AC sources by measuring both voltage and current.
By verifying the accuracy and applicability of Thevenin’s theorem and the superposition theorem,
the report seeks to demonstrate their effectiveness in simplifying and analyzing complex electrical
circuits, thereby enhancing the understanding of fundamental electrical principles and their practical
applications in circuit design and analysis.

Theory and Methodology:

Thevenin theorem
In circuit theory terms, Thevenin theorem allows any two-port network to be reduced to a simple
series circuit having a single voltage source and a single impedance. The theorem applies to both DC
as well as frequency domain AC circuits consisting of reactive elements (inductive and capacitive)
and resistive elements, in general called impedances. It means that the theorem applies for AC in an
exactly the same way to DC except that resistances are generalized to impedances.

The Thevenin theorem is a process by which a complex circuit is reduced to an equivalent series
circuit consisting of a single voltage source, VTH, a series impedance, ZTH, and a load impedance, ZL.
After creating the Thevenin’s equivalent circuit, you may then easily determine the load voltage, VL
and the load current, IL. The theorem was independently derived in 1883 by Léon Charles Thevenin
(1857–1926), an electrical engineer while working with the then National Posts et Telegraphs
telecommunications organization, France. Thevenin’s theorem is widely used to make circuit
analysis simpler and to study a circuit’s initial-conditions and steady-state responses.

Thevenin theorem states that,


For any linear electrical network containing only voltage sources, current sources and
impedances can be replaced at its load terminals by an equivalent circuit called Thevenin
circuit with a combination of a voltage source called Thevenin voltage (Vth) in a series
connection with an impedance (Zth).

Consider an RLC series-parallel complex circuit of Fig. 1. To find the Thevenin’s equivalent circuit
between the terminals, A and B, open the terminals between A and B by removing the load
impedance, ZL as shown in Fig. 2. But before that measure the load voltage between the terminals A
and B with the phase angle difference between the input and output signals.
L1 R1
A
ZL

R2 RL

vi(t) = Vmsint
C1 LL

B
Figure 1: An RLC series-parallel complex circuit with the load impedance
1
To measure the Thevenin voltage, we need to measure the open circuit voltage, VOC (red marked)
using the oscilloscope with the phase angle difference with the input voltage, vi(t) across the
terminals, A and B of Fig. 2. This is our Thevenin voltage, VTH. That is, 𝑉𝑇𝐻 = 𝑉𝑂𝐶
L1 R1
A

R2

vi(t) = Vmsint VOC


C1

B
Figure 2: An RLC series-parallel complex circuit after removing the load impedance to measure VOC

To measure the Thevenin impedance, we need to measure the open circuit impedance across the
terminals, A and B of Fig. 3 with the voltage source shorted at the input side (red marked solid line).
This is used for theoretical computation of the Thevenin’s impedance.

L1 R1
A

R2

C1

B
ZTH
Figure 3: An RLC series-parallel complex circuit after removing the load impedance to measure the
Thevenin’s impedance theoretically

However, to obtain the Thevenin’s impedance practically, we need to measure the short circuit
current flowing between the terminals, A and B as in Fig. 4 with the input source voltage connected.
After that, we need to take the ratio of the open voltage, VOC measured from Fig. 2 and the short
𝑉
circuit current, ISC to get the Thevenin’s impedance. That is, 𝑍𝑇𝐻 = 𝐼 𝑂𝐶
𝑆𝐶

2
L1 R1
A

R2
ISC
vi(t) = Vmsint
C1

B
Figure 4: An RLC series-parallel complex circuit after removing the load impedance to measure the
Thevenin’s impedance practically

Now, construct the Thevenin’s equivalent circuit as per Fig. 5 and measure the voltage between the
terminals A and B with the phase angle difference between the input and output signals for the same
input signals applied as per the measured open circuit voltage.

LTH RTH
A
ZL

RL
voc(t) = 1.414VOC(sint-)

LL

B
Figure 5: Thevenin’s equivalent circuit of an RLC series-parallel complex circuit with the load impedance
back to its place, i.e. between the terminals A and B

Superposition theorem
The superposition theorem is a derived result of the superposition principle suited to the network
analysis of electrical circuits. The principle of superposition is applicable only for linear systems.
The concept of superposition can be explained mathematically by the following response and
excitation principle:
i1 → v1
i2 → v2
i1 + i2 → v1 + v2

Then, the quantity to the left of the arrow indicates the excitation and to the right indicates the system
response. Thus, we can state that a device, if excited by a current, i1 will produce a response, v1.
Similarly, an excitation, i2 will cause a response, v2. Then if we use an excitation, i1 + i2, we will find
a response, v1 + v2 as per principle of superposition.

The Superposition theorem is applicable to linear networks (time varying or time invariant)
consisting of independent sources, linear dependent sources, linear passive elements (resistors,
inductors, capacitors) and linear transformers. The principle of superposition has the ability to reduce
a complicated problem to several easier problems each containing only a single independent source.
3
Superposition theorem states that,
For a linear system (notably including the sub-category of time-invariant linear systems)
the response (voltage or current) in any branch of a linear bilateral electrical circuit having
more than one independent sources equals the algebraic sum of the responses caused by
each independent source acting alone, where all the other independent sources are replaced
by their internal impedances.

When we try to find the responses using the Superposition theorem all the remaining voltage sources
are made zero by replacing them with short circuits and all remaining current sources are made zero
by replacing them with open circuits.

To ascertain the contribution of each individual independent source, first all of the other independent
sources must be turned off (set to zero) or disabled by:

• Replacing all other independent voltage sources with a short circuit, thereby, eliminating
difference of potential i.e. V = 0; internal impedance of ideal voltage source is zero (short circuit).
• Replacing all other independent current sources with an open circuit, thereby, eliminating current
i.e. I = 0; internal impedance of ideal current source is infinite (open circuit).

This procedure is followed for each source in turn, then the resultant responses are summed
algebraically to determine the true response of the circuit.

The superposition theorem is very important in circuit analysis. It is used in converting any circuit
into its Norton equivalent or Thevenin equivalent.

Now, consider an RLC series-parallel complex circuit of Fig. 6, which has two AC voltage sources
having different amplitudes but the same frequency. To verify the superposition theorem between
the terminals, A and B, measure the load voltage between the terminals A and B with the phase angle
difference between the input (input 1 and input 2) and output signals. Use oscilloscope to measure
peak or rms voltage and phase angle difference and multimeter to measure rms voltage only.

L1 R1 R2
A
ZL
RL

vi1(t) = Vm1sint vi2(t) = Vm2sint

CL

B
Figure 6: An RLC series-parallel complex circuit with the capacitive load impedance with two ac sources
Now, replace the first input with a short circuit as per Fig. 7 and measure the voltage between the
terminals A and B with the phase angle difference between the input (input 2 only) and the output
signal for the same input signals applied as per the circuit of Fig. 6 using the same technique.

4
L1 R1 R2
A
ZL
RL

vi2(t) = Vm2sint

CL

B
Figure 7: An RLC series-parallel complex circuit with the capacitive load impedance with input 2 shorted

Now, replace the second input with a short circuit as per Fig. 8 and measure the voltage between the
terminals A and B with the phase angle difference between the input (input 1 only) and the output
signal for the same input signals applied as per the circuit of Fig. 6 using the same technique.

L1 R1 R2
A
ZL
RL

vi1(t) = Vm1sint

CL

B
Figure 8: An RLC series-parallel complex circuit with the capacitive load impedance with input 1 shorted

Apparatus:

1. Oscilloscope
2. Function generators (2)
3. Multimeter
4. Resistors (100 , 200 , 1 k, and as per your ZTH computation)
5. Inductors (2.4 mH, and as per your ZTH computation)
6. Capacitors (1 F, and as per your ZTH computation)
7. Connecting wires
8. Breadboard

5
Data Table:

Table 1: Data table of the experiment on Thevenin’s Theorem for a RLC series-parallel complex circuit
VL VOC ISC RTH
f
Original Equivalent Measured Calculated Measured Calculated Measured Calculated
1 kHz 3.53V 3.56V 1.14V 1.09V 6mA 6.33mA 0.27kΩ 0.20kΩ

Table 2: Data table of the experiment on Superposition Theorem for a RLC series-parallel complex circuit
VL VL1 VL2 VL1 + VL2
f
Computed Measured Computed Measured Computed Measured Computed Measured
1 kHz 2.07 2.4V 2.03 2.02V 0.05 0.06V 2.05 2.08

Calculations:

Given that,
v = 5sinωt
Vrms = 5/√2 = 3.53
R1=100Ω
R2=200Ω
L=100mH
C=1µF
f=1 KHz

Inductor
XL=2πfL
=2π×1× 103 × 2.42 × 10−3 = 15.072Ω

Capacitor
1 1
𝑋𝑐 = = = 159.15Ω
2πfL 2 × 3.1416 × 1 × 103 × 1 × 10−6

Thevenin calculation
𝑍𝑇 = 300 + 𝑖(628.32 − 159.15) = 556.88 ∠ 57.40
𝑉 3.53
𝐼𝑠𝑐 = 𝑍 = 556.88 ∠ 57.40 = 6.33 × 10−3 ∠ − 57.40
𝑇
𝑉𝑡ℎ = 𝐼𝑠𝑐 × (𝑅2 + 𝑖𝑋𝑐 ) = 6.33 × 10−3 < −57.40 × (200 + 628.32) = 1.62 ∠ − 18.89

Superposition calculation
Given that,
vi1 = 15sinωt L=1mH
vi1 = 5sinωt C=1µF
R1=100Ω f=1 KHz
R2=0.98Ω

(15.072∠90 + 100) × 77.53∠ − 4.20


𝑍𝑇𝑜𝑡𝑎𝑙 = = 44.13∠1.3
(15.072∠90 + 100) + 77.53∠ − 4.20
3.5
𝐼𝑠 = = 0.413∠ − 1.3
200 + 44.13∠1.3
0.413∠ − 1.3 × 4.13∠1.3
𝐼𝐿1𝑅1 = = 0.42∠ − 5.24
4.13∠1.3 + 15.072∠90 + 100
𝑉𝐿1 = 0.42∠ − 5.24 × 15.072∠90 = 2.03∠34.2
6
77.53∠ − 4.20 × 3.5
𝑉𝐿 = = 2.07∠9.09
200 + 77.53∠ − 4.20

For 1KHz
𝑍𝑡𝑜𝑡𝑎𝑙 = (200∠0) × 77.53∠ − 4.20 (200) + 77.53∠ − 4.20 = 55.90∠ − 3.03
𝐼𝑠 = 2.1 15.072∠90 + 100 + 55.90∠ − 3.03 = 0.213∠ − 4.43
𝑉𝐿1 = 0.213∠ − 4.43 × 15.072∠90 = 0.05∠85.57
𝑉𝐿 = 77.53∠ − 4.20 × 2.1 5.072∠90 + 100 + 77.53∠ − 4.20 = 2.07∠9.09

Simulation and Measurement:

7
Discussion:

The experiment aimed to verify Thevenin's and Superposition theorems in a complex RLC series-
parallel circuit at 1 kHz. For Thevenin's theorem, there's close agreement between calculated and
measured values for VOC, ISC, and RTH, suggesting good compliance with theoretical predictions.
However, a discrepancy in VL suggests potential measurement error or circuit complexity not fully
accounted for. For Superposition theorem, computed and measured values for VL1, VL2, and VL1
+ VL2 are reasonably close, indicating successful application of the theorem. Possible mistakes could
include inaccuracies in component values, improper grounding, or insufficient consideration of
parasitic elements. Improvements could involve more precise measurement instruments, clearer
circuit diagrams, and rigorous error analysis to enhance experimental accuracy and reliability.

Reference(s):

[1] Electrical Circuits 2 (AC) lab manual, EEE, FE, AIUB.


[2] Russel M. Kerchner and George F. Corcoran, “Alternating Current Circuits,” John Wiley & Sons, 4th
Edition, New York, USA, 1960, ISBN 0 85226408 9.
[3] Robert L. Boylestad, “Introductory Circuit Analysis”, Prentice Hall, 12th Edition, New York, 2010,
ISBN 9780137146666.

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