0% found this document useful (0 votes)
20 views18 pages

Finite Word Length

Uploaded by

sam torent
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
20 views18 pages

Finite Word Length

Uploaded by

sam torent
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 18

ECE 3203

Digital Signal Processing

Finite Word Length Effect

Shah Muhammad Azmat Ullah


Lecturer,
Dept. of ECE, KUET.
Khulna University of Engineering & Technology
Introduction

• When digital system are implemented either in hardware or in system, the


filter coefficients are stored in binary registers.
• These registers can accommodate only a finite number of bits and hence ,
the filter coefficients have to truncated or rounded-off in order to fit into
these registers.
• Truncation or rounding of the data results in degradations of system
performance.

• Also, in digital processing systems, a continuous-time input signal is


sampled and quantized in order to get digital signal.
• The process of quantization introduces an error in the signal.

Department of Electronics and Communication Engineering (ECE) 2


Types of Number Representation

Computers store numbers not with infinite precision but rather in some
approximation that can be packed into a fixed number of bits or bytes.
Almost all computers allow the programmer a choice among several different
such representations or data types. Data types can differ in the number of
bits utilized, but also in the more fundamental respect of whether the stored
number is represented in fixed-point or floating-point format.

There are two common forms that are used to represent the numbers in a
digital or any other digital hardware.
1. Fixed point representation
2. Floating point representation

Department of Electronics and Communication Engineering (ECE) 3


Fixed point representation

In the fixed point arithmetic, the position of the binary point is fixed. The bit
to the right represents the fractional part of the number and to those to the
left represents the integer part.

For example, the binary number 01.1100 has the value 1.75 in decimal.

Department of Electronics and Communication Engineering (ECE) 4


Fixed point representation

A number in fixed point representation is exact. Arithmetic between


numbers in fixed point representation is also exact, with the conditions that
(i) the answer is not outside the range of integers that can be represented,
and
(ii) that division is interpreted as producing an integer result, throwing away
any integer remainder.

There are many formats to represent fixed point numbers like, Sign-
magnitude, One’s compliment and Two’s compliment, etc.

Department of Electronics and Communication Engineering (ECE) 5


Floating point representation

Department of Electronics and Communication Engineering (ECE) 6


Compare floating point with fixed point arithmetic

Department of Electronics and Communication Engineering (ECE) 7


Errors

• Only Finite numbers of bits are used to perform arithmetic


operations. Typical word length is 16 bits, 24 bits, 32 bits etc.

• This finite word length introduces an error which can affect the
performance of the DSP system.

• The main errors are


1. Input quantization error / Sampling/Digitization Error
2. Co-efficient (parameter) quantization error
3. Product Quantization error / Round off noise in multiplication
4. Overflow in addition
5. Limit cycles
Department of Electronics and Communication Engineering (ECE) 8
Errors

Input quantization error


• The conversion of continuous-time input signal into digital value
produces an error which is known as input quantization error.

• This error arises due to the representation of the input signal by a


fixed number of digits in A/D conversion process.

Overflow in addition
• Overflow in addition of two or more binary numbers occurs when the
sum exceeds the word size available in the digital implementation of
the system.

Department of Electronics and Communication Engineering (ECE) 9


Errors
Co-efficient quantization error
• The filter coefficients are compared to infinite precision. If they are
quantized the frequency response of the resulting filter may differ
from the desired frequency response. i.e poles of the desired filter
may change leading to instability.

Product Quantization error


• It arises at the output of the multiplier
• When a ‘b’ bit data is multiplied with another ‘b’ bit coefficient the
product (‘2b’ bits) should be stored in ‘b’ bits register. The multiplier
Output must be rounded or truncated to ‘b’ bits. This known as
overflow and round off error.
Department of Electronics and Communication Engineering (ECE) 10
Errors
Limit cycles
Since quantization inherent in the finite precision arithmetic operations
render the system nonlinear, in recursive system these nonlinearities
often cause periodic oscillation to occur in the output, even when input
sequence is zero or some nonzero value. Such an oscillation in recursive
systems are called limit cycles.

There are two type of limit cycles:

1. Zero input limit cycle


2. Overflow limit cycle

Department of Electronics and Communication Engineering (ECE) 11


Zero input limit cycle
Zero input limit cycles are usually of lower amplitudes in comparison
with overflow limit cycles. Let us consider a system with the difference
equation
𝑦 𝑛 = 0.8𝑦 𝑛 − 1 + 𝑥(𝑛)

With zero input i.e. x(n)=0 n y(n)-unquantized y(n)-quantized


and initial condition y(-1)=10. -1 10.0 10
0 8.0 8
1 6.4 6
2 5.12 5
3 4.096 4
4 3.2768 3
5 2.62144 2
Department of Electronics and Communication Engineering (ECE) 12
Overflow limit cycle
Consider a casual , all pole second order IIR digital filter implemented
using two’s complement arithmetic with a rounding of the sum of
products by a single quantizer. The difference equation is describing the
system as
𝑦 𝑛 = 𝑄𝑅 −𝑎1 𝑦 𝑛 − 1 − 𝑎2 𝑦 𝑛 − 2 + 𝑥(𝑛)

𝑄𝑅 . represents the rounding operations

Let 𝑎1 = 1.0012 = 0.8751𝑑 and 𝑎1 = 0.1112 = 0.875𝑑

The initial conditions: 𝑦(−1) = 0.1102 = 0.75𝑑 and 𝑦 −2 = 1.0112 = −0.75𝑑

For zero input: x 𝑛 = 0 and for 𝑛 ≥ 0


Department of Electronics and Communication Engineering (ECE) 13
Overflow limit cycle
For zero input: x 𝑛 = 0 and for 𝑛 ≥ 0

n y(n-1) y(n-2) −𝑎1 𝑦 𝑛 − 1 𝒚 𝒏 = 𝑄𝑅 . Y(n) in


− 𝑎2 𝑦 𝑛 − 2 decimal
0 𝑦(−1) = 0.1102 𝑦 −2 = 1.0112 1.010100 1.011 -0.625
1 𝑦(0) = 1.0112 𝑦(−1) = 0.1102 10.110011 0.110 +0.75
2 𝑦(1) = 0.1102 𝑦(0) = 1.0112 1.001101 1.010 -0.75
3 𝑦(2) = 1.0112 𝑦(1) = 0.1102 10.101100 0.110 +0.75
4 𝑦(3) = 0.1102 𝑦(2) = 1.0112 1.010100 1.011 -0.625

Department of Electronics and Communication Engineering (ECE) 14


Limit Cycles
What are importance of limit cycle in signal processing?

1. In a communication environment, when no signal is transmitted,


limit cycle can occur which is extremely undesirable. For example in
a telephone no one would like to hear unwanted noise when no
signal is put in from the other hand. Consequently , when digital
filters are used in telephone exchanges, care must be taken regarding
this problem.

2. The second reasons for studying limit cycles is that this effect can
effectively used in digital waveform generators. By producing
desirable limit cycles in a reliable manner, these limit cycles can be
used as a source in digital signal processing.
Department of Electronics and Communication Engineering (ECE) 15
Effects of Error in DSP

The effect of error introduced by a signal process depend upon number


of factors including the

1. Type of arithmetic
2. Quality of input signal
3. Type of algorithm implemented

Self Study: Effects of coefficient quantization in IIR system

Department of Electronics and Communication Engineering (ECE) 16


Find the purpose of your life!!

Department of Electronics and Communication Engineering (ECE) 17


Department of Electronics and Communication Engineering (ECE) 18

You might also like