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DSDV Module1

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0% found this document useful (0 votes)
17 views35 pages

DSDV Module1

Uploaded by

tejut9246
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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Dept.

of ECE, AJIET, Mangaluru Digital System Design using Verilog

Module - 1

PRINCIPLES OF COMBINATIONAL LOGIC

Introduction
 The logic networks described by a Boolean algebra are divided into two general
categories namely combinational circuits and sequential circuits.
 Combinational networks are categorized by the fact that the outputs at any instant are
functions of the inputs at any instants. Combinational network does not have a memory.
 Sequential networks are categorized by the fact that the outputs at any instant are not only
a function of the current inputs but, in addition depend upon the past history of the inputs.
Sequential network has a memory.

Definition of Combinational Logic


 Combinational logic deals with the technique of combining the basic gates, into circuits
that perform desired function.
 Some of the useful combinational logic functions are adders, subtractors, decoders,
encoders, multiplexers, demultiplexers, display drivers, keyboard encoders etc.
 Logic circuits without feedback from output to the input, constructed from a functionally
complete gate set, are said to be combinational. Combinational network does not have a
memory.
 Let X be the set of all input variables {x0, x1,……xn} and Y be the set of all output
variables {y0, y1,……yn}. Then the output is related to the input as
Y = F(x)

x0 y0
Combinational logic
function (F)
xn yn
Fig.1.1: Combinational Logic Model

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Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog

 For any combinational logic system can be designed it must be defined. The fig.1.2
illustrates the sequence of design tasks in general way.

Truth Switching
Problem
table equations
Statement
written

Logic Logic Equations


circuit diagram simplified
Fig.1.2: General Combinational Logic Design Sequence
 The first task is to define the problem to be solved. The problem is then rewritten in the
form of truth table. From the truth table, the switching equations can be written,
simplified and logic diagram drawn.
 Logic can be stated in several ways such as in truth table, in logic diagrams and by
Boolean equations. Each input variable combination that produces logic 1 in the output
column of the truth table can form a term in the Boolean switching Equations.

Truth Table Representation


 A truth table is a logical representation of a problem statements (or verbal descriptions of
problems) in a tabular form which specifies number of inputs, outputs and a logic
between input and output.
Problem:
1. Develop a truth table for a system which accepts two 2-bit binary number and
generates three outputs. The first output indicates when the two numbers differ by 2
or more, the second output indicates when the two numbers are identical and the
third output indicates when the first number exceeds the second number.
Let first number be AB (A is MSB (Most Significant Bit) and B is LSB (Least Significant Bit))
and second number be CD (C is MSB and D is LSB). Let X, Y, Z be the outputs. The truth table
is represented as

Inputs Outputs
A B C D X Y Z
0 0 0 0 0 1 0

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Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog

0 0 0 1 0 0 0
0 0 1 0 1 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 0 0 0
0 1 1 1 1 0 0
1 0 0 0 1 0 1
1 0 0 1 0 0 1
1 0 1 0 0 1 0
1 0 1 1 0 0 0
1 1 0 0 1 0 1
1 1 0 1 1 0 1
1 1 1 0 0 0 1
1 1 1 1 0 1 0

2. Give the truth table representation of a system which takes two 2-bit binary number
as its inputs and generates an output to indicate when the sum of the two numbers is
odd.
Let first number be AB (A is MSB (Most Significant Bit) and B is LSB (Least Significant Bit))
and second number be CD (C is MSB and D is LSB). Let Y be the output. The truth table is
represented as

Inputs Output
A B C D Y
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1

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Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog

0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0

3. Write a truth table for a four input system indicating when majority of inputs are
true.
Let A, B, C, D be inputs and let Y be the output. The truth table is represented as

Inputs Output
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1

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Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog

1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

Definitions of the logic terms related to boolean expression

Literal:
A literal is a Boolean variable or its complement.
For example: If X is a Boolean variable then both X and X̄ are literal.
Product term:
A product term is a literal or logical product (AND) of multiple literals.
For example: If X, Y and Z are Boolean variables then X, XY, X̄YZ are some of the
product terms
Sum term:
A sum term is a literal or logical OR of multiple literals.
For example: If X, Y and Z are Boolean variables then X, X + Y, X̄ + Y + Z are some
of the sum terms
Sum of products (SOP):
It is logical OR of multiple product terms.
For example: If X, Y and Z are Boolean variables then F(X, Y, Z) = XY + X̄ Ȳ + YZ is a
sum of product expression.
Product of Sum (POS):
It is logical AND of multiple sum terms.
For example: If X, Y and Z are Boolean variables then F(X, Y, Z) = (X + Y)(X + Y + Z)
is product of sum expression.
Minterms:
It is a product term where all the input variables appear once either in complemented or
uncomplemented form.
For example: if X, Y and Z are Boolean variables then XYZ, X̄ Y Z are some of the
minterms
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Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog

Maxterms:
It is a sum term where all the input variables appear once either in complemented or
uncomplemented form.
For example: if X, Y and Z are Boolean variables then X+Y+Z, X̄ + Y + Z are some of
the maxterms
Canonical sum of products:
It is a complete set of minterms that defines when an output variable is logic 1.
For example: if X, Y and Z are Boolean variables then
F(X, Y, Z) = X̄YZ + XȲZ + XYZ is a canonical sum of product.
Canonical product of sums:
It is a complete set of maxterms that defines when an output variable is logic 0.
For example: if X, Y and Z are Boolean variables then
F(X, Y, Z) = (X̄ + Y + Z)(X + Ȳ + Z̄)(X + Y + Z) is a canonical sum of product.
Prime Implicant:
It is a permitted group of minterms or maxterms
Essential prime implicant:
A prime implicant that contains one or more minterms or maxterms that is unique i.e.
terms not present in any other implicant

Canonical Forms
 Canonical form or standard form of Boolean function will contain all the variables in
either true form or complemented form
 Canonical form or standard form can be expressed as either Sum of minterms or Product
of maxterms.
 Procedure to convert a SOP expression into standard canonical form
i. Identify the missing variables in the each AND term.
ii. AND the missing term and its complement with the original AND term.
iii. Expand the term by property of distribution.
 Procedure to convert a POS expression into standard canonical form
i. Identify the missing variables in the each OR term.
ii. OR the missing term and its complement with the original OR term.

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Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog

iii. Expand the term by property of distribution.

Problems:
1. Convert the following SOP equation into proper or standard canonical form
𝐘 = 𝐟(𝐚, 𝐛, 𝐜) = 𝐚𝐛 + 𝐛𝐜 + 𝐚𝐜
In the first term ab̄ the missing variable is c, so AND (c + c̄) with first term.
i.e. ab̄(c + c̄) = ab̄c + abc̄
In the second term bc the missing variable is a, so we AND (a + ā) with second term.
i.e. bc(a + ā) = bca + bcā
In the third term ac̄ the missing variable is b, so AND (b + b̄) with third term.
i.e. ac̄(b + b̄) = ac̄b + ac̄b̄
Therefore, the standard canonical form is,
Y = ab̄c + abc̄ + abc + ābc + abc̄ + ab̄c̄
Y = ab̄c + abc̄ + abc + ābc + ab̄c̄

2. Convert the following POS equation into proper or standard canonical form
𝐘 = 𝐟(𝐚, 𝐛, 𝐜) = (𝐚 + 𝐛 )(𝐛 + 𝐜)
In the first term a + b̄ the missing variable is c, so OR (cc̄) with first term.
i.e. a + b̄ + cc̄ = (a + b̄ + c)(a + b̄ + c̄) [x + yz = (x + y)(x + z)]
In the second term b̄ + c the missing variable is a, so OR (aā) with second term.
i.e. b̄ + c + aā = (b̄ + c + a)(b̄ + c + ā)
Therefore, the standard canonical form is,
Y = (a + b̄ + c) (a + b̄ + c̄)(ā + b̄ + c)

Generation of switching equation from truth tables


 Switching equations can be written more conveniently by using the minterm or maxterm
representation. For an n-variable logical function there are 2n minterms and 2n maxterms.
 For example, consider a truth table for 3-variable logical function.
Table 1.1: Minterm and maxterm of 3 variables

i/p Variables Minterm Maxterm

Page 7
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog

A B C Representation Representation

0 0 0 Ā B̄ C̄ = m0 A + B + C = M0
0 0 1 Ā B̄ C = m1 A + B + C̄ = M1
0 1 0 Ā B C̄ = m2 A + B̄ + C = M 2
0 1 1 Ā B C = m3 A + B̄ + C̄ = M3
1 0 0 A B̄ C̄ = m4 Ā + B + C = M 4
1 0 1 A B̄ C = m5 Ā + B + C̄ = M 5
1 1 0 A B C̄ = m6 Ā + B̄ + C = M6
1 1 1 A B C = m7 Ā + B̄ + C̄ = M 7
 Each minterm is represented by mi and each maxterm by Mi where i is the decimal
equivalent of the binary number.
 The logic expression in standard sum of product form can be written for the
corresponding truth table by writing one product term for each input that produces an
output of 1.

i/p Variables o/p


A B C Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
 Sum of product form for the above truth table can be expressed as,
Y = f(A, B, C) = ĀBC̄ + ĀBC + ABC̄
or
Y = f(A, B, C) = ∑ m(2, 3, 6)
or
Y = f(A, B, C) = ∑ (m2, m3, m6)

Page 8
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog

 Σ-Notation is used to represent the minterms in a simple way using decimal numbers.
 Similarly, the logic expression in standard product of sum form can be written for the
corresponding truth table by writing one sum term for each input that produces an output
of 0.
 Product of sum form can be expressed as,
Y = f(A, B, C) = (A + B + C)( A + B + C̄)( Ā + B + C)( Ā + B + C̄)( Ā + B̄ + C̄)
or
Y = f(A, B, C) = π M(0, 1, 4, 5, 7)
or
Y = f(A, B, C) = π (M0, M1, M4, M5, M7)
 π-Notation is used to represent the maxterms in a simple way using decimal numbers.

Karnaugh Maps (K-map)


 Simplification of switching equations reduces the amount of hardware needed to realize a
given function.
 Boolean algebra can be used to simplify the boolean expression or switching equations
but it is lengthy process. A better approach is to use Karnaugh Maps (K-map).
 K-map is a matrix of squares where each square represents a minterm or maxterm from a
Boolean equation.
 K-map is a graphical method, which consists of 2n cells for ‘n’ variables. The adjacent
cells are differed only in single bit position.
 K-Map method is most suitable for minimizing Boolean functions of 2 variables to 5
variables.
 Literal or Product terms are assigned to the cells of K- map labelling each row and each
column of the k-map with a variable, with its complement, or with a combination of
variables and complements. Fig. 1.1 shows the way to label rows and columns of
different K-maps.
 It is important to note that from one cell to the next cell along any row or from one cell to
next cell along any column, only one variable in the product term should change.

1- Variable K-Map

Page 9
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

 For 1-variable there will be 21 = 2 cells in the K-map as shown in the fig.

 Cells should be grouped separately.


2- Variable K-Map
 For 2-variables there will be 22 = 4 cells in the K-map as shown in the fig.

 There is only one possibility of grouping 4 adjacent min terms.


 The possible combinations of grouping 2 adjacent min terms are {(m0, m1), (m2, m3),
(m0, m2) and (m1, m3)}.
3- Variable K-Map
 For 3-variables there will be 23 = 8 cells in the K-map as shown in the fig.

 There is only one possibility of grouping 8 adjacent min terms.


 The possible combinations of grouping 4 adjacent min terms are {(m0, m1, m3, m2), (m4,
m5, m7, m6), (m0, m1, m4, m5), (m1, m3, m5, m7), (m3, m2, m7, m6) and (m2, m0, m6, m4)}.

Deepashree A P Page 10
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

 The possible combinations of grouping 2 adjacent min terms are {(m0, m1), (m1, m3), (m3,
m2), (m2, m0), (m4, m5), (m5, m7), (m7, m6), (m6, m4), (m0, m4), (m1, m5), (m3, m7) and
(m2, m6)}.
4- Variable K-Map
 For 4-variables there will be 24 = 16 cells in the K-map as shown in the fig.

 There is only one possibility of grouping 16 adjacent min terms.


 Let R1, R2, R3 and R4 represents the min terms of first row, second row, third row and
fourth row respectively. Similarly, C1, C2, C3 and C4 represents the min terms of first
column, second column, third column and fourth column respectively. The possible
combinations of grouping 8 adjacent min terms are {(R1, R2), (R2, R3), (R3, R4), (R4, R1),
(C1, C2), (C2, C3), (C3, C4), (C4, C1)}.

5- Variable K-Map
 For 5-variables there will be 25 = 32 cells in the K-map as shown in the fig.

Deepashree A P Page 11
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

 There is only one possibility of grouping 32 adjacent min terms.


 There are two possibilities of grouping 16 adjacent min terms. i.e., grouping of min terms
from m0 to m15 and m16 to m31.
In the above all K-maps, we used exclusively the min terms notation. Similarly, you can use
exclusively the Max terms notation.

Simplifying Minterm Equation (SOP expressions) using K-Maps


 The procedure to simplify SOP expressions are as follows:
1. Plot the K-map and place 1's in those cells corresponding to the 1's in the truth
table or SOP expression. Place 0's in other cells.
2. Check the K-map for all possible valid adjacent 1's and form a group of 2n 1's and
encircle those 1's which are not adjacent to any other 1's. They are called isolated
1's.
3. While grouping make sure that there is minimum no. of groups.
4. Then form the simplified expression by summing product terms of all the groups.

Problems:
1. Simplify the following expression using K-map
¯𝐂 + 𝐀
𝐘 = 𝐀𝐁 ¯𝐁¯𝐂 + 𝐀
¯ 𝐁𝐂 + 𝐀𝐁
¯ 𝐂¯ + 𝐀
¯𝐁¯ 𝐂¯
Procedure
 Plot 3-variable K-map for given expression.
 Place 1's in the cell 0, 1, 3, 4, 5 and 0's in the remaining cells.
 1's in cell 3 and cell 1 are adjacent which can be grouped (group 1)
 1's in cells 0, 1, 4 and 5 are adjacent which can be grouped (group 2)
 When all the 1's are grouped, the minimized expression can be generated. In group1 B is
eliminated and in group2 variable A and C are eliminated.
 Therefore, the minimized expression is
Y = ĀC + B̄

Deepashree A P Page 12
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

2. Simplify the following expression using K-map


¯ 𝐁 𝐂¯ 𝐃
𝐘=𝐀 ¯ +𝐀
¯ 𝐁 𝐂¯ 𝐃 + 𝐀 𝐁 𝐂¯ 𝐃
¯ + 𝐀 𝐁 𝐂¯ 𝐃 + 𝐀 𝐁
¯ 𝐂¯ 𝐃 + 𝐀
¯𝐁¯𝐂𝐃
¯
Procedure
 Plot 4-variable K-map for given expression.
 Place 1's in the cell 2, 4, 5, 9, 12, 13 and 0's in the remaining cells.
 1's in cell 2 is not adjacent to other 1's therefore it is grouped separately (group 1)
 1's in cells 9, and 13 are adjacent which can be grouped (group 2)
 1's in cells 4, 5, 12 and 13 are adjacent which can be grouped (group 3)
 When all the 1's are grouped, the minimized expression can be generated. In group1 no
variable can be eliminated, in group2 variable B is eliminated and in group3 variable A
and D are eliminated.
 Therefore, the minimized expression is
Y = ĀB̄CD̄ + AC̄D + BC̄

Deepashree A P Page 13
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

Problems:
1. Simplify the following function in SOP form using K-map
¯𝐁
𝐘=𝐀 ¯ 𝐂¯ + 𝐀
¯𝐁¯𝐂+𝐀
¯𝐁𝐂+𝐀𝐁
¯ 𝐂¯ + 𝐀 𝐁
¯ 𝐂 + 𝐀 𝐁 𝐂¯

Simplified boolean expression is


¯+𝐀
𝐘=𝐁 ¯ 𝐂 + 𝐀𝐂¯

2. Simplify the following function in SOP form using K-map


¯ 𝐁𝐂 + 𝐀𝐁
𝐘=𝐀 ¯ 𝐂¯ + 𝐀𝐁𝐂

Simplified boolean expression is


¯ 𝐂¯ + 𝐁𝐂
𝐘 = 𝐀𝐁

3. Simplify the following function in SOP form using K-map


Y = f(A, B, C) = ∑m (1, 3, 5, 6, 7)

Deepashree A P Page 14
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

Simplified boolean expression is


𝐘 = 𝐀𝐁 + 𝐂

4. Simplify the following function in SOP form using K-map


Y = f(A, B, C) = ∑m (0, 2, 3, 4, 5, 7)

Simplified boolean expression is


¯ 𝐂¯ + 𝐀𝐂 + 𝐀
𝐘=𝐁 ¯𝐁

5. Simplify the following function in SOP form using K-map


Y = f(A, B, C, D) = ∑m (0, 2, 8, 10)

Simplified boolean expression is


¯𝐃
𝐘= 𝐁 ¯

Deepashree A P Page 15
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

6. Simplify the following function in SOP form using K-map


Y = f(A, B, C, D) = ∑m (0, 2, 5, 7, 8, 10, 13, 15)

Simplified boolean expression is


¯𝐃
𝐘= 𝐁 ¯ + 𝐁𝐃

7. Simplify the following function in SOP form using K-map


Y = f(A, B, C, D) = ∑m (1, 3, 4, 6, 9, 11, 12, 14)

Simplified boolean expression is


¯ 𝐃 + 𝐁𝐃
𝐘= 𝐁 ¯

Incompletely specified functions (don’t care terms)


 When an output value is known for every possible combination of input variables, the
function said to be completely specified.

Deepashree A P Page 16
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

 When an output value is not known for every possible combination of input variables, the
function said to be incompletely specified i.e. the truth table does not generate an output
value for every possible combination of input variables.
 The minterms or maxterms that are not used as a part of the output functions are called
don’t care terms denoted by 'x' or 'd' or '–' in the k-map.
 If a don’t care term can be used to create a larger group of minterms then it is assigned 1
otherwise it is assigned 0.
 For example, consider the three variable truth table the output Y is incompletely specified
for input conditions 110 and 111.

A B C Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 -
1 1 1 -
 From the truth table the expression is written as
Y = f(A, B, C) = ∑m(1, 3, 5) + ∑d(6, 7)

𝐘=𝐂
 Don’t care term in cell 7 is considered as 1 and group of four (cell 1, 3, 5, 7) is done to
get expression Y = C.

Deepashree A P Page 17
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

Problems:
1. Simplify the following function in SOP form using K-map
Y = f(A, B, C, D) = ∑m(1, 2, 3, 5, 9, 12, 14, 15) + ∑d(4, 8, 11)

Simplified boolean expression is


¯𝐁
𝐘=𝐀 ¯𝐂+𝐀
¯ 𝐂¯ 𝐃 + 𝐀𝐁𝐂 + 𝐁
¯ 𝐃 + 𝐀𝐁𝐃
¯

2. Simplify the following function in SOP form using K-map


Y = f(A, B, C, D) = ∑m(0, 1, 4, 8, 9, 10) + d(2, 11)

Simplified boolean expression is


¯ 𝐂¯ 𝐃
𝐘=𝐀 ¯ +𝐁
¯ 𝐂¯ + 𝐀𝐁
¯

Deepashree A P Page 18
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

3. Simplify the following function in SOP form using K-map


Y = f(A, B, C, D) = ∑m(2, 3, 4, 5, 13, 15) + d(8, 9, 10, 11)

Simplified boolean expression is


¯ 𝐁𝐂¯ + 𝐁
𝐘=𝐀 ¯ 𝐂 + 𝐀𝐃

4. Simplify the following function in SOP form using K-map


Y = f(A, B, C, D) = ∑m(1, 5, 7, 9, 13, 15) + d(8, 10, 11, 14)

Simplified boolean expression is


𝐘 = 𝐂¯𝐃 + 𝐁𝐃

Deepashree A P Page 19
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

5. Simplify the following function in SOP form using K-map


Y = f(A, B, C, D) = ∑m(0, 2, 4, 8, 10, 14) + d(5, 6, 7, 12)

Simplified boolean expression is


¯
𝐘=𝐃

6. Simplify the following expression using K-map


Y = F(A, B, C, D, E) = ∑m(1, 4, 8, 10, 11, 20, 22, 24, 25, 26) + d(0, 12, 16, 17)
 Group 1 (cell 0, 4, 8, 12) is formed within the first 16 cell map.
 Group 2 (cell 10, 11) is formed within the first 16 cell map.
 Group 3 (cell 0, 1, 16, 17) is formed by combination of two pairs from two
different 16 cell maps.
 Group 4 (cell 20, 22) is formed within the second 16 cell map.
 Group 5 (cell 8, 10, 24, 26) is formed by combination of two pairs from two
different 16 cell maps.
 Group 6 (cell 16, 17, 24, 25) is formed within the second 16 cell map.

Deepashree A P Page 20
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

Simplified boolean expression is


¯𝐃
𝐘 = 𝐟(𝐀, 𝐁, 𝐂, 𝐃, 𝐄) = 𝐀 ¯ 𝐄¯ + 𝐀
¯ 𝐁𝐂¯𝐃 + 𝐁
¯ 𝐂¯ 𝐃
¯ + 𝐀𝐁
¯ 𝐂𝐄¯ + 𝐁 𝐂¯ 𝐄¯ + 𝐀 ¯𝐂 𝐃
¯

7. Simplify the following function in SOP form using K-map


Y = f(A, B, C, D, E) = ∑m(1, 3, 4, 6, 9, 11, 12, 14, 17, 19, 20, 22, 25, 27, 28, 30)
+ d(8, 10, 24, 26)

Simplified boolean expression is


𝐘 = 𝐂¯𝐄 + 𝐂𝐄¯

8. Simplify the following function in SOP form using K-map


Y = f(A, B, C, D, E) = ∑m(0, 2, 8, 10, 16, 18, 24, 26)

Deepashree A P Page 21
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

Simplified boolean expression is


𝐘 = 𝐂¯ 𝐄¯

Simplifying Maxterm Equations (POS expressions


 The procedure to simplify POS expressions are as follows:
1. Plot the K-map and place 0s in those cells corresponding to the 0s in the truth
table or POS expression. Place 1s in other cells.
2. Check the K-map for all possible valid adjacent 0s and form a group of 2 n 0s and
encircle those 0s which are not adjacent to any other 0. They are called isolated
0s.
3. While grouping make sure that there are minimum no. of groups.
4. Then form the simplified expression by taking product of sum terms of all the
groups.
Problems:
1. Simplify the following expression using K-map
𝐘 = (𝐀 + 𝐁 + 𝐂¯) (𝐀 + 𝐁
¯ + 𝐂¯)(𝐀
¯+𝐁
¯ + 𝐂¯)(𝐀
¯ + 𝐁 + 𝐂)(𝐀 + 𝐁 + 𝐂)
Procedure
 Plot 3-variable K-map for given expression.
 Place 0s in the cell 0, 1, 3, 4, 7 and 1s in the remaining cells.
 0s in cells 0, and 4 are adjacent which can be grouped (group 1)
 0s in cells 1, and 3 are adjacent which can be grouped (group 2)

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Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

 0s in cells 3 and 7 are adjacent which can be grouped (group 3)


 When all the 0s are grouped, the minimized expression can be generated. In group1
variable A can be eliminated, in group2 variable B is eliminated and in group3 variable A
is eliminated.

 Therefore the minimized expression is


𝐘 = (𝐁 + 𝐂)(𝐀 + 𝐂¯)(𝐁
¯ + 𝐂¯)

2. Simplify the following expression using K-map


Y = f(A, B, C, D) = πM(0, 2, 3, 8, 9, 12, 13, 15)

Simplified boolean expression is


𝐘 = (𝐀 + 𝐁 + 𝐃)(𝐀 + 𝐁 + 𝐂¯)(𝐀
¯+𝐁
¯+𝐃
¯ )(𝐀
¯ + 𝐂)

Quine McCluskey Minimization technique

Deepashree A P Page 23
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

 For many applications the number of variables in a problem is too large to simplify
manually using K-maps.
 The Quine McCluskey Minimization technique is an algorithm that uses the same
Boolean algebra postulates that were used with k-map but in a form suitable for computer
solution.
Procedure to use Quine McCluskey Minimization technique:
1. Arrange all the minterms, in a list of increasing order, make groups such that it contains
same number of 1s.
2. Create a new table showing the minterms in group n that matched with those from group
n + 1 such that they differ in only one position. This process is repeated until all of the
minterms in each group have been compared to those in the next higher group. When a
minterm in a group is combined with a minterm in an adjacent group, a dash (-) is used to
indicate an eliminated variable. As each minterm from a group combines with it is now
part of a larger group. If a minterm did not combine with another, then no check would
be made. If a term doesn’t simplify it is a prime implicant.
3. All of the adjacent minterm groups, are compared to see if groups of four can be made.
4. Repeat the process until step 3. In this case both dashes must be in the same bit position
with only one other variable allowed to change. The creation of a new table further
groups the sets of minterms. This same process is repeated until no further combination
of minterm group is possible.
5. All non checked minterm groups are now considered to be prime impliants.
6. All of the prime implicants are formed into a prime implicant table.
7. Evaluate the prime implicants by circling those minterms that are contained in only one
prime implicant. Circled minterms represent essential prime implicants.

Problems:
1. Simplify the following Boolean function by using a Quine McCluskey minimization
technique
Y = f(A, B, C, D) = ∑m (0, 1, 2, 3, 6, 7, 8, 9, 14, 15)
 Arrange all the minterms in increasing order and make a group such that each minterm in
the group contain same number of 1s as shown in table 1.2. Group 0 contains only those

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Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

minterms with no 1s, Group 1 contains only those minterms with single 1s, Group 2
contains only those minterms with two 1s, Group 3 contains only those minterms with
three 1s, Group 4 contains only those minterms with four 1s as shown in table below.
Table 1.2: Grouping of minterms according to numbers of 1s

Group Minterm Binary representation Check


0 0 0000 ✔
1 0001 ✔
1 2 0010 ✔
8 1000 ✔
3 0011 ✔
2 6 0110 ✔
9 1001 ✔
7 0111 ✔
3
14 1110 ✔
4 15 1111 ✔

 Create a new table showing the minterms in group n that matched with those from group
n + 1 such that they differ in only one position. This process is repeated until all of the
minterms in each group have been compared to those in the next higher group. When a
minterm in a group is combined with a minterm in an adjacent group, a dash (-) is used to
indicate an eliminated variable. The combined minterm are grouped together as shown in
table 1.3.
¯𝐁
i.e. 𝐀 ¯ 𝐂¯ 𝐃
¯ + 𝐀
¯𝐁¯ 𝐂¯ 𝐃 = 𝐀
¯𝐁¯ 𝐂¯(𝐃 + 𝐃
¯) = 𝐀
¯𝐁¯ 𝐂¯ −
 When all of the minterm in group 0 is compared with those in group 1 then compare the
minterms in group1 with those in group 2.
 This process is repeated until all the minterm in each group is compared with those in the
next higher group.
 When a minterm from a group combines with a minterm in the next higher group then it
is checked (✔). If a minterm does not combine with another then no check would be
made. If a term does not simplify then it is a prime implicant

Deepashree A P Page 25
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

Table 1.3: Creation of minterm groups of two

Group Minterm Binary representation Check


0, 1 000– ✔
0 0, 2 00–0 ✔
0, 8 –000 ✔
1, 3 00–1 ✔
1, 9 –001 ✔
1 2, 3 001– ✔
2, 6 0–10 ✔
8, 9 100– ✔
3, 7 0–11 ✔
2 6, 7 011– ✔
6, 14 –110 ✔
7, 15 –111 ✔
3
14, 15 111– ✔
 All of the adjacent minterm groups in table 1.4 is compared with the next higher group to
see if groups of four can be made. When group of four is made the dashes (–) in the
groups of two must be in the same bit position and only one variable change (0 in one
group and 1 in another group) is allowed
Table 1.4: Creation of minterm groups of four

Group Minterm Binary representation


0, 1, 2, 3 00––
0
0, 1, 8, 9 –00–
1 2, 6, 3, 7 0–1–
2 6, 7, 14, 15 –11–

 Repeat the previous steps until no further combination of minterms groups is possible.
When further grouping is made the dashes must be in the same bit position with only one

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Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

other variable is allowed to change. The creation of a new table further groups the sets of
minterms.
 All the non-checked minterm groups are prime implicants.
 Prime implicant table is prepared using all the non-checked minterm groups as shown in
table 1.5.
 Each prime implicant is listed vertically in two forms: PI terms and the decimal notation
of minterms.
Table 1.5: Prime implicant table

PI terms Minterm 0 1 2 3 6 7 8 9 14 15
Ā B̄ 0, 1, 2, 3 x x x x
B̄ C̄ 0, 1, 8, 9 x x ⊗ ⊗
Ā C 2, 6, 3, 7 x x x x
BC 6, 7, 14, 15 x x ⊗ ⊗

 Evaluate the prime implicants by circling those minterms that are present in only one
prime implicant i.e. only one x in a column. Circled minterm represent essential prime
implicant (EPI).
 To represent the simplified boolean expression select all the essential prime implicants
are considered along with the other prime implicants such that all the minterms should be
covered. Minterm (2, 3) are present in both the prime implicants so select any one of
these prime implicant to cover all the minterms in the equation but not both.
 Therefore, the simplified boolean expression is
¯ 𝐂¯ + 𝐁 𝐂 + 𝐀
𝐘=𝐁 ¯𝐁¯
or
¯ 𝐂¯ + 𝐁 𝐂 + 𝐀
𝐘=𝐁 ¯𝐂

2. Simplify the following Boolean function by using a Quine McCluskey minimization


technique
Y = f(A, B, C, D) = ∑m (0, 2, 3, 6, 7, 8, 10, 12, 13)
Grouping of minterms according to numbers of 1s

Deepashree A P Page 27
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

Group Minterm Binary representation Check


0 0 0000 ✔
2 0010 ✔
1
8 1000 ✔
3 0011 ✔
6 0110 ✔
2
10 1010 ✔
12 1100 ✔
7 0111 ✔
3
13 1101 ✔
Creation of minterm groups of two

Group Minterm Binary representation Check


0, 2 00–0 ✔
0
0, 8 –000 ✔
2, 3 001– ✔
2, 6 0–10 ✔
1 2, 10 – 010 ✔
8, 10 10–0 ✔
8, 12 1–00
3, 7 0–11 ✔
2 6, 7 011– ✔
12, 13 110–
Creation of minterm groups of four

Group Minterm Binary representation


0 0, 2, 8, 10 –0–0
1 2, 3, 6, 7 0–1–

Prime implicant table

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Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

PI terms Minterm 0 2 3 6 7 8 10 12 13
B̄ D̄ 0, 2, 8, 10 ⊗ x x ⊗
Ā C 2, 3, 6, 7 x ⊗ ⊗ ⊗
A C̄ D̄ 8, 12 x x
A B C̄ 12, 13 x ⊗
Therefore, the simplified boolean expression is
¯𝐃
𝐘=𝐁 ¯ +𝐀
¯ 𝐂 + 𝐀𝐁𝐂¯

Quine McCluskey using don’t care terms


 The same rules that are applied for using don’t care terms with the K-map can be used for
Quine McCluskey.
1. Construct a list of minterms and don’t care terms classified according to the number
of 1s. Indicate the don’t care terms by *.
2. Compare the terms in group n, including don’t care terms, with terms in group n+1,
looking for a single variable change. Treat don’t care terms as 1 in finding prime
implicants.
3. Repeat step2 for creating an additional table indicating groups of four minterms/
don’t care term groups. Repeat step3 until no further grouping can occur.
4. Construct a prime implicant chart and determine essential prime implicants. The
don’t care terms are used to find the prime implicants but it is not compulsory to
include don’t care terms in the final expression.

Problems:
1. Simplify the following Boolean function by using a Quine McCluskey minimization
technique
Y = f(A, B, C, D) = ∑m (1, 3, 13, 15) + ∑d (8, 9, 10, 11)
Grouping of minterms according to numbers of 1s

Group Minterm Binary representation Check


1 0001 ✔
1
8* 1000 ✔

Deepashree A P Page 29
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

3 0011 ✔
2 9* 1001 ✔
10* 1010 ✔
11* 1011 ✔
3
13 1101 ✔
4 15 1111 ✔
Creation of minterm groups of two

Group Minterm Binary representation Check


1, 3 00–1 ✔
1, 9* –001 ✔
1
8*, 9* 100– ✔
8*, 10* 10–0 ✔
3, 11* –011 ✔
9*, 11* 10–1 ✔
2
9*, 13 1–01 ✔
10*, 11* 101– ✔
11*, 15 1–11 ✔
3
13, 15 11–1 ✔
Creation of minterm groups of four

Group Minterm Binary representation


1, 3, 9*, 11* –0–1
1
8*, 9*, 10*, 11* 10––
2 9*, 13, 11*, 15 1––1
Prime implicant table

PI terms Minterm 1 3 13 15
B̄ D 1, 3, 9*, 11* ⊗ ⊗
AD 9*, 13, 11*, 15 ⊗ ⊗
Since the all minterms in the minterm group (8, 9, 10, 11) are don’t cares it is not considered for
creating prime implicant table.

Deepashree A P Page 30
Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

Therefore the simplified boolean expression is


¯𝐃+𝐀𝐃
𝐘=𝐁

2. Simplify the following Boolean function by using a Quine McCluskey minimization


technique
Y = f(A, B, C, D) = ∑m (1, 2, 3, 5, 9, 12, 14, 15) + ∑d (4, 8, 11)
Grouping of minterms according to numbers of 1s

Group Minterm Binary representation Check


1 0001 ✔
2 0010 ✔
1
4* 0100 ✔
8* 1000 ✔
3 0011 ✔
5 0101 ✔
2
9 1001 ✔
12 1100 ✔
11* 1011 ✔
3
14 1110 ✔
4 15 1111 ✔
Creation of minterm groups of two

Group Minterm Binary representation Check


1, 3 00–1 ✔
1, 5 0–01
1, 9 –001 ✔
2, 3 001–
1
4*, 5 010–
4*, 12 –100
8*, 9 100–
8*, 12 1–00

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Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

3, 11* –011 ✔
2 9, 11* 10–1 ✔
12, 14 11–0
11*, 15 1–11
3
14, 15 111–
Creation of minterm groups of four

Group Minterm Binary representation


1 1, 3, 9, 11* –0–1
Prime implicant table

PI terms Minterm 1 2 3 4 5 8 9 11 12 14 15
B̄ D 1, 3, 9, 11* x x x x
Ā C̄ D 1, 5 x x
Ā B̄ C 2, 3 ⊗ x
Ā B C̄ 4*, 5 x x
B C̄ D̄ 4*, 12 x x
A B̄ C̄ 8*, 9 x x
A C̄ D̄ 8*, 12 x x
A B D̄ 12, 14 x x
ACD 11*, 15 x x
ABC 14, 15 x x

Essential prime implicant has two minterms (2, 3) and is included in the final expression.
Minterm 1 is present in two prime implicant group therefore to add minterm 1 to the final
expression select the prime implicant group which has more number of minterms (i.e. 1, 3, 9,
11).
Minterm 5 is present in two prime implicant group therefore to add minterm 5 to the final
expression select the minterm group (1, 5).

Minterm 12 is present in three prime implicant group therefore to add minterm 12 to the final
expression select the minterm group (12, 14).

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Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

Minterm 15 is present in two prime implicant group therefore to add minterm 15 to the final
expression select the minterm group (14, 15).
Therefore, the simplified boolean expression is
¯𝐃+𝐀𝐁𝐃
𝐘=𝐁 ¯ +𝐀𝐁𝐂+𝐀
¯ 𝐂¯ 𝐃 + 𝐀
¯𝐁¯𝐂

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Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

Question Bank
1. Define the following terms:
i. Minterm
ii. Maxterm
iii. Canonical SOP
iv. Canonical POS
v. Prime implicants
vi. Essential prime implicants
vii. Incompletely specified functions
2. Design a combinational logic circuit which takes two, 2-bit binary numbers as its input
and generates an output equal to 1, when the sum of the two number is odd.
3. Design a 3-input,1-output minimal Combinational network that has a logical-1 output
when the majority of its inputs are logic-1 and has a logic-0 when majority of inputs are
logic-0
4. Convert the given boolean function into canonical minterm form and canonical maxterm
form
i. f(A, B, C) = (A + B)(B + C)
ii. f(A, B, C) = A + AC(B + C)
iii. f(A, B, C) = ĀB + BC
iv. f(A, B, C) = (Ā + B)(B + C̄)
v. f(A, B, C) = A + B̄C
5. Find all the prime implicants and essential prime implicants for the given function using
k-Map method.
i. f(A, B, C, D) = ∑m(0, 3, 6, 7, 8, 9, 10) + d(2, 5, 11, 12, 15)
ii. f(A, B, C, D) = ∑m (0, 2, 5, 7, 8, 10, 13, 15) + d(1, 4, 11, 14)
iii. f(A, B, C, D) = πM(4, 5, 6, 7, 8, 12, 13) + d(1, 15)
iv. f(A, B, C, D) = πM(0, 1, 4, 5, 6, 7, 9, 14) + d(13, 15)
v. f(A, B, C, D, E) = ∑m(3, 7, 11, 12, 13, 14, 15, 16, 18)
+ d(24, 25, 26, 27, 28, 29, 30, 31)
vi. f(A, B, C, D, E) = ∑m(3, 7, 8, 10, 11, 12, 14, 15, 17, 19, 21, 23, 25, 27, 29, 31) +

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Dept. of ECE, AJIET, Mangaluru Digital System Design using Verilog[21EC32]

d(2, 6, 26, 30)


vii. f(A, B, C, D, E) = ∑m (0, 2, 4, 6, 8, 16, 18, 20, 22, 24, 26, 28, 30) +
d(3, 7, 11, 15, 19, 23, 27, 31)
6. Find the prime implicants and essential prime implicants using Quine-McCusky method
and verify the result using k-map.
i. F(A, B, C, D) = ∑m (7, 9, 12, 13, 14, 15) + d(4, 11)
ii. Y =∑m (1, 3, 8, 6, 10, 12, 14) + d(7, 13)
iii. f(A, B, C, D) = ∑m (1, 2, 3, 5, 9, 12, 14, 15) + d(4, 8, 11)
iv. Y = ∑m (1, 4, 7, 9, 12, 14) + d(2, 13)
7. Simplify the following Expression using 3-variable MEV
i. f(A, B, C, D) = ∑m (1, 3, 7, 11, 15) + d(0, 2, 5)
ii. f(A, B, C, D) = ∑m (1, 4, 7, 9, 12, 14) + d(2, 13)
iii. f(A, B, C, D) = ∑m (0, 2, 3, 8, 9, 12, 13, 15) + d(2, 13)
iv. f(A, B, C, D) = ∑m (1, 5, 7, 10, 11) + d(2, 3, 6, 13)
v. f(A, B, C, D) = ∑m (2, 3, 4, 10, 13, 14, 15) + d(7, 9, 11)
8. Simplify the following Expression using K-map
i. Y = Ā B̄ + Ā B C̄ + A B̄ D
ii. Y = Ā B C + A B̄ C̄ + A B C
iii. Y = Ā B C + A D̄ + A B D̄

Deepashree A P Page 35

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