cs330 Endsems 2023
cs330 Endsems 2023
The exam is open books, notes, printed materials, No electronic device should be used during the
examination. Consulting/discussing with anyone during the exam is strictly prohíbited. Unless specified
etplicitly, assume 64-bit X&86 architecture with multiple CPUs and an 05 uith no bugs
Best of luckl
Q16 Q2 Q3 O Q4
5 245
Q5
6 Q6 Q7 TOTAL
Which of the following is/are possible output (s) if one thread executes string () and the other thread
executes pamber) concurrently?
1A2B3C
B. lAB23C
e123ABC
D. 12ABC3
E. 12A3BC
(d) Assuming
Consider two threads T; and T; of a process P ereated using the pthread API in the Linuz syaten
X86 system with split-mode addressing, which of the following statement(s) is/are false.
A. If T is in kerncl mode, T, is not nllowed to enter the kernel mode
BThe kernel stack used by T and T; are different
C.)The OS page fault handler must handle the page faults caused by TË and T; in a serial manner.
D. When the OS scheduler performs a context switch between T; and T2, the page table base pointer
(CR3) register is not changed
IWhen the OS scheduler perform8 acoutext switch between T and P,the page table base pointer
(CR3) register is changed
(e) Consider that there is a page fault or virtual address V of a multi-threaded process orn a singe CPU
system. When the OS page fault lhandler inspects the page table mappings, it finds that the page tabie
entries are correct for all the levels before the leaf Jevel, Note that, the leaf level is the level-4 PTE in a
4-level page table where the page table base register (e... CR3 in X86) points to the level-1 PTE, In the
leaf-level page table entry (PTE),
A, the present bit can be zero
B. the present bit can be one
O the write bit can be one (both read-write allowed)
D. the content can be correct in all aspects if interrupts are disabled during page fault handling
E) the content can be correct in all aspects if interrupts are enabled during page fault handling
2. True or False with justification. Justification should be a precise argument supporting your verdict. No marks2x5= 10
without proper reasoning.
(a) Physical memory usage of a system will decrease on successful execution of the exec systen call.
(b) If a file system always performs non-cached I/O, there will be no consistency issues.
never result in
sequence, LRUand Belady's optimal (MIN) page replacement will
(d) For any memory access
the FIFO page replacement.
more number of page faults than
L,2;3, Ly 4, 2,3 ’ LRU
False, o #frowes =3 md seqene
2
(e) Afull TLBfAush is necessary during aprocess context switch.
Falee, he same TB
return b;
registers)
1/Disassembly (R1, R2, R3 and A are
b' -->R2
argument 'a' --> R1 and
//function d_calc,
.function d_calc ('ctr'--> R3)
Oxx7FFO01080000: mov $0, R3 //Load R3 with zero
//Comparectr' with 'a'
Ox7FFO01080004: cmp R3, R1 0x7FFO010800018 if ctr' >= 'a'
Ox7FFO01080008: jge (+0xC) //Jump to += 'a')
//Add R2 = R2 + R1 ('b'
Ox7FFO0108000C: add R2, R1 7/Increment counter ('ctr'++)
Ox7FFO01080010: inc R3
//Jump to 0x7FF001080004 value)
Ox7FFO01080014: jmp (-0x14) register A (return
Ox7FF001080018: mov R2, A /7 mov R2 to the
Ox7FF00108001C: ret 1/ Return
executed in one
and only the above function is +2=1
execution
page faults during theAnswer the following questions. |2 +3 + 2 +2
Assume that there are no context switches.
scheduling interval without any final answer)
mention the calculation steps along with the mnemory accesses to perforn
address trans
(Briefly be the number of
TLB support, what will
(a) In a MMU with no executed?
100) is
lation if d_calc (0,
trans
memory accesses to perform addre ss
TLB support, what will be the number of
(b) In a MMUwith no 100) is executed?
lation if d_calc (5,
42=11
tatal beteh= sx3
(c) Write an expression for the number of memory accesses to perform address traslation in terms of a and
bfor a MMUwith no TLB (no explanation required).
2
() What will be the minimum number of menory accesses reauired to performaddress trarslation if dcalc(5,
100) is executed for a MMUwith a TLB (a8sUming an emptyTLB at the start of the function)? 2
loo-s)
(41) XS 3
(e) Write an expression for the minimum number of memory accesses required to perform address translation
in terms of a and b for a MMU with a TLB (assuming an empty TLB at the start of the function, no
explanation required). 2
Il+ 3(4-) t2 = 344 |0
4. Consider the following implementation as a solution to critical section problem for two threads To and T.
int flag [2] = {0,0};
int turn = 0;
void lock (int id) /*id = 0 or 1 */
flag [id] = 1;
while(flag [id 1] && turn == (id 1)); /* is the bit-wise XOR*/
turn = id 1; // (1)
flag [id] = 0; // (S2)
Does the above implementation guarantee mutual exclusion? If yes, provide a formal argument for
corTectness.
If not, show a concrete example when the mutual exclusion is violated.
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(b) If all threads complete without any deadlock, what will be the minimum number of nalloc cals lat s
#5) and why?
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to osss lme qd o we wee s22 nud pen-bl are by
(c) If all threads complete without any deadlock and print the value of ("ptr) at the end of the
will be the minimum value of ("ptr) (across all function, what
possible execution orders) and wy 15
he muw male
struct dentryl
u32 inode-number ;
char mame [252]:
Assume that the disk I/O operations are performed in units of block size i.e., 1KB. Answer the following
questions (no explanation required). |1+1+3+3=8
(a) What is the maximum disk size supported by the file sxstem?
42
(b) You have written a program to create as many files as possible under an initially empty directory. How
many files your program can successfully create?
4
A user process opens and successfully reads an existing file at /h ome/user/courses/os/notes . txt of size
one kilobyte, where / is the file system mount point. Asume that, the super block, all the inodes and
index meta-data required to access the file and directory are present in memory. What is the minimum
and maximum number of disk block accesses required to complete the read operation?
(d) In the above
(with the pathquestioh,
sane as
assme thst the fle otes t t is o sie 1MB and e
(offset is a msltiple of 1KB)
ptevios qeto), sfter that i readie one Bock (1KB)
the prosopens the fle
at # randont blncke offet
cached. However, the fle stessfelly, Frshe see hat. the siper 5linrlk all inedes are always
dizectory are not cached. indesesisand ditectory COnten hery o y Be esched Data blncks of fle as
complete the read operaton?Whst the minimom and maYi sby of dilk Block aeeeeses pnnied to
7. Memory is a precious resource and you want to augment the virtual mermoty subeystem of the 05 to compr the
Lsed physical memory to increase the degtee of multiprog amming withost ing swapping Assme that there
3an existing compression logic in the O8 which provides funetionalities lilke commpresion á deeompesion
Specifically, you can axSumethe followáng two OS level funetions are already noable,
int compressPFN (u32 srcpfn, void *outPTR):Compresses 4096 bytes of data in the page frame srcpfs and
stores the compressed stream into outPTR. The length of compressed data is returned by this funetio
void decompressPFN (void *inPTR, u32 dstpfn, u32 size): Decompresses conpressed data of length =
size stored at inPTR and stores the decompressed data in the dstpfn. The caller of this funeticn shonldcasure
that the decompressed data is of length 4096 bytes.
The solution framework is as follows: There is a background user space process (a daemon, sy capserr vhich
invokes a new system call i.e., compress in a periodic manner. The design of compress system call (paraeters
tãe
return value and implenentation) is to be discussed as part of the answer. You are required to disess
implementation of the compress system call-both the mechanisn and policy.
effects on other OS
Mechanism: How exactly the compress system call is implemented? What are the sideYour implementation
handling them.
subsystems (like virtual memory etc.) and your proposed methods of
should handle both correctness and efficiency.
questions like which memory pages to compress,
Policy: In this part, you are required to discuss answers to resource tradeof?
time etc. Note that, you should discuss the
how many memory pages to compress at what
savings.
implications of yyour policy e.g., CPUusage vs. memory Assume page size
memory pages because of performance reasons.
Hint: you may not want to compress all the
of 4KB and X86 like paging support.
ador ttual adls