TSV Redundancy: Architecture and Design

Issues in 3D IC
Ang-Chih Hsieh† , TingTing Hwang† , Ming-Tung Chang‡, Min-Hsiu Tsai‡ , Chih-Mou Tseng‡ and Hung-Chun Li‡
† Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 300
‡ Global Unichip Corporation, Hsinchu, Taiwan 300

Abstract—3D technology provides many benets including box is required for each group to select which 4 TSVs
high density, high band-with, low-power, and small form-factor. are actually used to transfer signals. The advantage of this
Through Silicon Via (TSV), which provides communication links structure is that the delays of all signals are almost identical.
for dies in vertical direction, is a critical design issue in 3D
This is an attractive property for DRAM designs. Although
integration. Just like other components, the fabrication and
bonding of TSVs can fail. A failed TSV may cause a number this structure is suitable to the dedicated layout style of
of known-good-dies that are stacked together to be discarded. memory designs, the cost is too expensive for ASICs. Another
This can severely increase the cost and decrease the yield as fault tolerance scheme that utilizes redundant TSVs targets on
the number of dies to be stacked increases. A redundant TSV 3D network-on-chip (3DNoC) links [7]. Though signicant
architecture with reasonable cost for ASICs is proposed in this yield improvement is achieved, the analysis and design ow
paper. Design issues including recovery rate and timing problem
are based on the dedicated network structure of 3DNoC. For
are addressed. Based on probabilistic models, some interesting
ndings are reported. First, the probability that three or more ASICs, the analysis and design ow may not be suitable. In
TSVs are failed in a tier is less than 0.002%. Assumption of this paper, a redundant TSV architecture and related design
that there are at most two failed TSVs in a tier is sufcient to issues are discussed. The proposed redundant TSV design can
cover 99.998% of all possible faulty free and faulty cases. Next, successfully recover most of the failed chips and increase the
with one redundant TSV allocated to one TSV block, limiting yield to 99.99% based on probabilistic models.
the number of TSVs in each TSV block to be no greater than
The rest of this paper is organized as follows. First, in Sec-
50 and 25 leads to 90% and 95% recovery rates when 2 failed
TSVs are assumed. Finally, analysis on overall yield shows that tion II, the yield of TSV bonding is discussed. In Section III,
the proposed design can successfully recover most of the failed the proposed architecture for TSV redundancy is introduced.
chips and increase the yield of TSV bonding to 99.99%. This can Next, in Section IV, the recovery rate and the number of
effectively reduce the cost of manufacturing 3D ICs. redundant TSVs required for the proposed architecture is an-
alyzed. Probabilistic model is used for evaluation. The design
I. I NTRODUCTION
issues for timing and required design ow are explained in
3D integration techniques are proposed as solutions to Section V. Finally the conclusion of this work is given in
overcome the scaling limit [1]. 3D technology provides many Section VI.
benets including high density, high band-with, low-power,
and small form-factor [2]. Through-Silicon Via (TSV) [3], II. FAILURE R ATE A NALYSIS FOR TSV
which provides communication links for dies in vertical The fabrication of TSV-based 3D ICs can be partitioned
direction, is a critical design issue in 3D integration. In current into following stages. First, dies of each tier are fabricated
manufacturing process for 3D designs, each die to be inte- individually. The fabrication of TSVs in each tier takes place
grated is manufactured individually. When TSV technology in this stage. Depending on the technology (TSV rst/last),
is applied, TSVs and bond pads are fabricated inside each either reactive-ion etching (RIE) or laser drilling is performed
die [4][5]. Then, bonding technology is used for die stacking. before TSV metallization process. According to the diameter
Just like other components, the fabrication and bonding of and aspect ratio of TSV, proper material (Cu or W [5]) is
TSVs can fail. A failed TSV may cause a number of known- selected for metallization. In general, the size of a TSV is
good-dies that are stacked together to be discarded. This can much larger than other on-chip devices. This leads to certain
severely increase the cost and decrease the yield as the number unique defect features for TSV forming [8]. For example, void
of dies to be stacked increases. may be formed in TSV and causae a TSV to fail [10]. After the
To improve the yield, some recovery mechanism is needed. fabrication of TSVs, wafer thinning is performed. Presently,
A simple but effective solution is to add redundant TSVs most 3D IC processes require each tier to be less than 100
which can be used to replace failed TSVs. This idea has been microns [5]. The surface roughness is an important factor to
realized in 3D DRAM designs [6]. In the proposed scheme, for the yield of later bonding stage. When the dies of consecutive
every 4 signals, 6 TSVs are allocated as a group. A switching tiers are stacked, the TSVs of the die in upped tier need to be
bonded to the bond pads of the die on lower tier, as shown in
This work was supported in parts by National Science Council of Taiwan,
Republic of China, under grant NSC 98-2220-E-007-024, NSC 98A052
Figure 1. Due to the alignment problem, a bond pad is required

978-3-9810801-6-2/DATE10 © 2010 EDAA

 p Stacks with no Failed
100.00%

TSV TSV 95.00%

Upper Tier
90.00%

TSV
85.00%

80 00%
80.00% f = 0 0001 #tier = 2
f=0.0001,#tier=2

% of Chip
TSV TSV
f=0.0001,#tier=5
Lower Tier 75.00% f=0.00002,#tier=2
f=0.00002,#tier=5
70.00%
Fig. 1. Bonding between TSVs and Bond Pads
300 350 400 450 500

for each TSV [9][10]. In addition to misalignments, TSVs #TSV

can also fail in the soldering process [11]. For example, short Fig. 2. Yield Analysis
circuits between two distinct TSVs or open circuits between a small portion of TSVs are failed. If these failed TSVs can be
TSV and its corresponding bonding pad may be formed. Other recovered with circuits of reasonable cost, the yield can be
failure mechanisms such as dislocation, process variations or largely improved. The redundant TSV design to be proposed
mechanical stress also decrease the fabrication yield of TSVs. in this paper provides a solution to this problem.
Above all, misalignment and failures on bonding are pri-
mary failure mechanisms for TSVs [11]. Both of the tech- III. R EDUNDANT TSV A RCHITECTURE
nologies used for alignment and bonding are very similar In this section, the architecture of our proposed redundant
to the packaging methods used in current IC industry [5]. TSV design is introduced in Section III-A. Next, a brief
Although the exact failure rate of TSVs is still not clear, it introduction to the oorplan of 3D IC and its relation to our
is possible to use the failure rates of alignment and bonding proposed architecture are given in Section III-B.
to perform a failure rate analysis for TSV. Considering the
TSV diameter and the size of bond pads, the failure rate of A. Architecture Design
a single TSV may ranges between 10−4 and 10−5 based on The proposed architecture for redundant TSV is depicted
current packaging technology. This assumption roughly meets in Figure 3. For each TSV, 2 MUXs are added to shift the
the yields of TSVs from the process technologies of HRI, signal to neighboring TSV when one TSV is failed. To reduce
IMEC and IBM [12][13][14]. the timing effect caused by the loading capacitance of the
According to the applications and network styles, the num- additional wires used for signal shifting, a pair of buffers are
ber of TSVs in each tier can be quite different. For many-core added to each TSV. The TSVs are connected as a chain where
processors or NoC-based designs, thousands of TSVs may be the redundant TSV is placed at the last position of the chain.
required in each tier. On the contrary, hundreds of TSVs may When no TSV is failed, all signals are transferred by original
be sufcient for smaller IP-based designs. In this work, we TSVs as shown in Figure 4(a). When a TSV is failed, the
focus on IP-based designs where TSVs are mainly used for signal of the failed TSV needs to be shifted. This in term
connections between modules on different tiers. Considering causes all signals between the failed TSV and the redundant
the area of bond pads and oorplan problems, we assume that TSV to be shifted. For example, let TSV 1 be failed. The
the number of TSVs to be placed in a tier ranges from 300 signal paths after shifting are shown in Figure 4(b). When a
to 500. signal is shifted, larger delay is introduced due to larger wire
An analysis between failure rate and yield is given in length and buffers. For signals that are timing critical, this
Figure 2. Assume that all dies to be stacked are known-good- may become a problem. We will discuss it in Section V-A.
dies. Thus, only the failure rate of TSV bonding needs to be In this architecture, only one failed TSV can be recovered in
considered. Let f stands for the failure rate of bonding one each chain. If two or more TSVs are failed in a chain, only
TSV and #tier stands for the number of tiers to be stacked. one of them can be recovered. Therefore, how to determine the
Note that the actual number of tiers that contain TSVs to be number of TSVs in a chain so that an acceptable recovery rate
bonded is equal to #tier - 1. For example, when #tier = 2, only can be achieved is an important design issue. This issue will
the top tier contains TSVs to be bonded. The x-axis represents be discussed in Section IV. For simplicity, the term TSV-chain
the number of TSVs to be placed in each tier (#TSV). Since a is used to refer to the structure of the proposed redundant TSV
good chip stack requires all TSVs to be successfully bonded, architecture.
the binding yield can be computed as (1−𝑓 )#𝑇 𝑆𝑉 ×(#𝑡𝑖𝑒𝑟−1) . The MUXs in the proposed architecture are connected to an
The analysis results for 𝑓 = {0.0001, 0.00002} and #𝑡𝑖𝑒𝑟 = e-fuse array which can be programmed by a scan-chain. By
{2 , 5} are shown in Figure 2. Without any redundant TSVs, default, all signals connect to MUXs are set to 0. When the
the average yield is 94.35%. And when #𝑇 𝑆𝑉 = 500 and testing for TSV connectivity is done, signals are scanned in to
#𝑡𝑖𝑒𝑟 = 5, the yield degrades to 81.8%. Note that dies to program the e-fuses so that each MUX receives an appropriate
be stacked are all known-good-dies. Therefore, the cost of control signal.
discarding chip stacks that are failed due to TSV bonding is
very expensive. In fact, in most failed chip stacks, only a very
 out_0 out_1 out_2 out_3 out_0 out_1 out_2 out_3
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

R_TSV

R_TSV
TSV_0

TSV_1

TSV_2

TSV_3

TSV_0

TSV_1

TSV_2

TSV_3
FAILED

0 1 0 1 0 1 0 1 0 1 0 1

in_0 in_1 in_2 in_3 in_0 in_1 in_2 in_3

(a) (b)
Fig. 4. TSV Recovery Mechanism: (a) Normal operations of TSVs; (b) TSV 1 is failed and TSV 1, TSV 2, and TSV 3 are shifted right one position

out_0 out_1 out_2 out_3

as follows:
0 1 0 1 0 1 0 1
reciever ∙ Determine the number of TSVs in each TSV block
∙ Determine the path to link the TSVs in a TSV block as
R_TSV
TSV_0

TSV_1

TSV_2

TSV_3

a chain
The rst problem is related to the recovery of a 3D design.
In Section IV, an analysis based on probabilistic model is
0 1 0 1 0 1 sender
performed to answer this question. The second problem is
related to the timing behavior of shifted signals. Discussions
in_0 in_1 in_2 in_3 on timing issues and guidelines for TSV-chain design are
Fig. 3. Architecture for Redundancy TSV presented in Section V.
IV. R ECOVERY R ATE A NALYSIS
In this section, the relation between the number of TSVs
in each TSV block and recovery rate is analyzed based on
probabilistic models. First, based on the failure rate of a single
TSV, the expected number of TSVs that may fail in a tier
is discussed in Section IV-A. The result of Section IV-A
determines the maximum number of failed TSVs that are
expected to be recovered by our proposed TSV-chains. Next,
for an expected number of failed TSVs in each tier, the
Fig. 5. TSV Blocks
required number of TSV-chains as well as the size limit of
B. TSV Block and TSV-Chain each TSV block are discussed in Section IV-B.
Due to manufacturing and physical design issues, TSVs are A. Analysis on the Expected Number of TSVs to be Recovered
not recommended to be placed arbitrarily on a plane. From
the aspect of manufacturing, a regular placement of TSVs Let 𝐹 stand for the failure rate of a single TSV and 𝑁
improves the exposure quality of the lithographic process stand for the number of TSVs in a tier. The probability that
and therefore improves the yield. In real designs, TSVs are exact 𝑛 TSVs are failed in a tier can be expressed as
suggested to be placed regularly in TSV blocks which are 𝑃𝑓 𝑡𝑠𝑣=𝑛 = 𝐶𝑛𝑁 × (𝐹 𝑛 ⋅ (1 − 𝐹 )𝑁 −𝑛 )
determined in oorplan stage. Inside each TSV block, TSVs
are arranged in a grid-based structure to satisfy the pitch where 𝐶𝑛𝑁 represents the number of combinations of 𝑁 TSVs
constraint of bond pads. Examples of TSV blocks are shown with 𝑛 of them failed and 𝐹 𝑛 ⋅ (1 − 𝐹 )𝑁 −𝑛 represents the
in Figure 5. Obviously, it is undesirable for a TSV-chain to probability of 𝑛 chosen TSVs are failed while other 𝑁 − 𝑛
contain TSVs of different TSV blocks due to long wires TSVs are not. Next, the term 𝐶 𝑅𝑎𝑡𝑖𝑜𝑛 is dened as the
for signal shifting. Therefore, a TSV-chain in our design probability that the number of failed TSVs is no greater than
is suggested to contains TSVs in the same TSV block. 𝑛, including the faulty free condition (that is, 𝑛 = 0). This can
Moreover, we let each TSV block contain only one redundant be computed by accumulating 𝑃𝑓 𝑡𝑠𝑣=𝑖 for 0 ≤ 𝑖 ≤ 𝑛 and
TSV. This means, for each TSV block, only one TSV-chain is can be expressed as
dened. Nevertheless, in terms of recovery rate, the number of 𝑛
∑
TSVs in a TSV-chain needs to be limited. In case the number 𝐶 𝑅𝑎𝑡𝑖𝑜𝑛 = 𝑃𝑓 𝑡𝑠𝑣=𝑖 .
of TSVs in a TSV block is too large for one TSV-chain, the 𝑖=0
TSV block needs to partitioned to a number of smaller TSV The values of 𝑃𝑓 𝑡𝑠𝑣=𝑛 and 𝐶 𝑅𝑎𝑡𝑖𝑜𝑛 for 𝐹 = 0.0001 and
blocks. 𝑁 = {300, 400, 500} are listed in Table I.
The design issues for our the proposed TSV-chain are listed
 TABLE I 100.00%
𝑃𝑓 𝑡𝑠𝑣=𝑛 AND 𝐶 𝑅𝑎𝑡𝑖𝑜𝑛 WHEN 𝐹 = 0.0001 90.00%

80.00%
𝑁 𝑛 𝑃𝑓 𝑡𝑠𝑣=𝑛 𝐶 𝑅𝑎𝑡𝑖𝑜𝑛

ecovery Rate
70.00%
0 97.0444% 97.0444%
300 1 2.9116% 99.9560% 60.00%

Recovery
2 0.0435% 99.9996% 50.00%

0 96.0788% 96.0788% 40.00%

400 1 3.8435% 99.9223% 30.00%
2 0.0767% 99.9990%
20.00%
0 95.1227% 95.1227% 10.00%
500 1 4.7566% 99.8793%
2 0.1187% 99.9980% 0.00%
25 26 27 29 31 33 35 38 41 45 50 55 62 71 83 100 125 166 250

Number of TSVs in a TSV Block

Table I shows that, when 𝑛 = 2, the values of 𝐶 𝑅𝑎𝑡𝑖𝑜𝑛 for Fig. 6. Recovery Rate when 𝑁 = 500, 𝑛 = 2
𝑁 = {300, 400, 500} are all greater than 99.998%. A smaller
𝐹 will result in a larger 𝐶 𝑅𝑎𝑡𝑖𝑜𝑛 . This means, as long as combinations that satises this requirement can be computed
the failure rate 𝐹 is no greater than 0.0001, the probability as
that three or more TSVs are failed is less than 0.002%. 𝐶𝑛#𝐵𝑙𝑜𝑐𝑘 .
Therefore, when designing TSV-chains, we can assume that
Inside each TSV block that contains one failed TSV, the
the maximum number of failed TSVs in a tier is 2. This
failed TSV can be located at #𝐵 𝑇 𝑆𝑉 possible positions.
assumption covers 99.998% of all possible faulty free and
Therefore, the #𝑅𝑒𝑐𝑜𝑣𝑒𝑟𝑎𝑏𝑙𝑒 𝐶𝑜𝑚𝑏𝑖𝑛𝑎𝑖𝑜𝑛𝑠 for 𝑛 = 2 can
faulty situations.
be computed as
B. Analysis on Recovery Rate 2
𝐶2#𝐵𝑙𝑜𝑐𝑘 ⋅ (#𝐵 𝑇 𝑆𝑉 ) .
As mentioned in Section III, each TSV-chain is capable of
recovering at most one failed TSV in a TSV block. As the The relation between #𝐵 𝑇 𝑆𝑉 and recovery rate for 𝑁 =
number of TSVs in a TSV block increases, the probability 500 and 𝑛 = 2 is shown in Figure 6. For different values of
that all failed TSVs can be recovered decreases. To achieve #𝐵 𝑇 𝑆𝑉 that result in the same #𝐵𝑙𝑜𝑐𝑘, only the smallest
an expected recovery rate, the number of TSVs in each TSV #𝐵 𝑇 𝑆𝑉 is shown in the gure since the recovery rates of
block must be limited. To simplify the analysis, we assume them are the same.1
that the number of TSVs in all TSV blocks are identical. Let According to Figure 6, to achieve 90% recovery rate,
#𝐵 𝑇 𝑆𝑉 stand for the number of TSVs in each TSV block #𝐵 𝑇 𝑆𝑉 needs to be no greater than 50. By limiting the
and 𝑛 stand for the number of failed TSVs. For a given value number of TSVs in each TSV block to be less than or equal
of 𝑛, we want to analyze the relation between #𝐵 𝑇 𝑆𝑉 and to 50, the recovery rate is greater than 90%. To achieve a
recovery rate. The discussion in Section IV-A indicates that higher recovery rate, the gure shows that with 95% recovery
assuming 𝑛 ≤ 2 is sufcient to covers 99.998% of all possible rate, the number of TSVs in each TSV block cannot be greater
faulty free and faulty situations. Therefore, we will perform than 25. In realistic ASIC designs, the number of TSVs in a
the analysis for 𝑛 = 1 and 𝑛 = 2 only. TSV block is usually less than 50. Therefore, in most cases,
Let 𝑁 stand for the number of TSVs in a tier. The TSV block partitioning is not required.
number of combinations of 𝑁 TSVs with 𝑛 failed TSVs can A further analysis is to compute the overall yield. In
be computed as 𝐶𝑛𝑁 . The number of combinations that all Table I, when 𝑁 = 500, 𝑃𝑓 𝑡𝑠𝑣=0 , 𝑃𝑓 𝑡𝑠𝑣=1 , and 𝑃𝑓 𝑡𝑠𝑣=2
failed TSVs can be recovered by TSV-chains is referred as are 95.1227%, 4.7566%, and 0.1187%, respectively. The dis-
#𝑅𝑒𝑐𝑜𝑣𝑒𝑟𝑎𝑏𝑙𝑒 𝐶𝑜𝑚𝑏𝑖𝑛𝑎𝑡𝑖𝑜𝑛𝑠. The recovery rate discussed cussion above indicates that the recovery rate for 𝑛 = 1 is
in this section is dened as always 100% based on our proposed architecture. Thus, let
#𝑅𝑒𝑐𝑜𝑣𝑒𝑟𝑎𝑏𝑙𝑒 𝐶𝑜𝑚𝑏𝑖𝑛𝑎𝑡𝑖𝑜𝑛𝑠 the recovery rate for 𝑛 = 2 be set to 90%. The overall yield
. can be computed as
𝐶𝑛𝑁
When 𝑛 = 1, only one failed TSV needs to be recovered. 𝑃𝑓 𝑡𝑠𝑣=0 +𝑃𝑓 𝑡𝑠𝑣=1 ×100%+𝑃𝑓 𝑡𝑠𝑣=2 ×90% = 99.98613%.
Since one TSV block contains one redundant TSV, regardless This value is high enough for most applications.
of the number of TSVs in each TSV block, one failed TSV can
always be recovered. Therefore, the recovery rate for 𝑛 = 1 V. D ESIGN F LOW AND TSV-Chain D ESIGN
is 100%. The discussion in Section IV focuses on the recovery of
The recovery rate analysis for 𝑛 = 2 is more complicated. failed TSVs in terms of connectivity. Timing issues are not
Let the term #𝐵𝑙𝑜𝑐𝑘 represent the number of TSV blocks in concerned. As mentioned in Section III-A, when a signal is
a tier. Under our assumptions, #𝐵𝑙𝑜𝑐𝑘 can be computed as shifted in a TSV-chain, extra delay will be incurred. For signals
𝑁
#𝐵 𝑇 𝑆𝑉 . To successfully recover all failed TSVs, each failed that are timing critical, the delay caused by signal shifting may
TSVs must be located in different TSV blocks. That is, 𝑛 TSV
1 The actual computation of #𝑅𝑒𝑐𝑜𝑣𝑒𝑟𝑎𝑏𝑙𝑒𝐶𝑜𝑚𝑏𝑖𝑛𝑎𝑖𝑜𝑛𝑠 is a little more
blocks are selected from #𝐵𝑙𝑜𝑐𝑘 TSV blocks. Each selected
complicated since sizes of TSV blocks may differ by one due to the division
TSV block contains exactly one failed TSV. The number of operation to compute #𝐵𝑙𝑜𝑐𝑘
 100%
tsv_4 tsv_3 tsv_2 tsv_1 tsv_0 tsv_r

ity for the Timing Critical

Failed
90%
TSV Unaware
80%

ignal to be shifted
tsv_0 70%
Timing Aware

tsv_1 60%
50%
tsv_2
40%

Signal
Probability
tsv_3 30%
20%
tsv_4
10%
1/5 2/5 3/5 4/5 5/5 0%
10 20 30 40 50 60 70 80 90 100
Fig. 7. All Possible Shifting Situations for a TSV-chain of Size 6 when 1
TSV is Failed # of TSVs in a TSV-Chain
Fig. 8. Evaluation on the Possibility for the Timing Sensitive Signal to Be
not be acceptable. In this section, timing issues for TSV-chain Shifted
design are discussed in Section V-A. The discussion leads signal to the head of a TSV-chain, the probability is reduced to
to the guidelines to link TSVs in a TSV block as a chain. 2.93% in average. Based on the evaluation, timing sensitive
Candidate TSV-chain structures are proposed in Section V-B. signals should always be routed through the TSVs located
In Section V-C, design issues in each stage of 3D design ow at the head of TSV-chains. This is one of the guideline that
are discussed. should be followed when designing TSV-chains.
A. Design Issues for Timing The next issue is to minimize the delay caused by sig-
nal shifting. This can be done by minimizing the distance
As explained in Section III-A, when a TSV is failed,
between the connected TSVs in a TSV-chain. As mentioned
according to the position of the failed TSV in a TSV-chain,
in Section III-B, TSVs in each block are placed in a grid-
one or more signals need to be shifted. Due to the chaining
based structure. Therefore, by requiring the connected TSVs
structure, even under the assumption that each TSV has
in a TSV-chain to be neighbors in the grid-based structure,
identical failure rate, the probability for each TSV in a TSV-
minimal and xed shifting delay can be guaranteed. This also
chain to be shifted varies. Figure 7 shows this situation.
makes the shifting delay predictable in early design stages.
Assume that 1 TSV is failed in a TSV-chain of size 6,
Thus, the second guideline for TSV-chain design is that any
all possible shifting situations are enumerated in Figure 7.
two connected TSVs in a TSV-chain must be next to each
When no TSV is failed and no shifting is required, the TSV-
other in the grid-based structure.
chain is shown in the right column of the rst row where
the redundant TSV is denoted as tsv r. For each row below, B. TSV-chain Design Problem
the left column indicates the failed TSV and the right column For each TSV block in a plane, the structure of the TSV-
shows the shifting situation. The last row lists the shifting chain needs to be considered. The analysis in Section V-A
probabilities of the TSVs in the TSV-chain when 1 TSV is indicates that timing critical signals should always be routed
failed. For tsv 0, no matter which TSV in the TSV-chain is through the TSVs located at the head parts of TSV-chains.
failed, it is always shifted because it is on the position next to In current design ow, signals that are assigned to each TSV
the redundant TSV. On the contrary, tsv 4, which is at the head block are roughly determined in oorplan stage. However, the
position of the TSV-chain, need not to be shifted unless itself exact assignment of signals to TSVs is not necessarily to be
is failed. In terms of extra delays introduced by signal shifting, done in this stage. From the perspective of physical design,
this property of TSV-chain indicates that the probability that leaving the assignment of signals to TSVs to be done in
the delay of a signal linked by a TSV is increased depends routing stage is benecial to minimize wire length. Therefore,
on the position of the TSV in the TSV-chain. This means, for in addition to the guidelines obtained in Section V-A, the
signals that are timing critical, it is preferable to assign these design of TSV-chain should also consider routing issues.
signals at the head parts of TSV-chains. Based on the concept of bounding box, discussion on wire
An evaluation for an extreme case where only one signal is length is given rst. For two pins on two different tiers to
timing critical is shown in Figure 8. The x-axis stands for the be connected, the relation between the bounding box of these
number of TSVs in a TSV-chain and the y-axis stands for the two pins and a TSV block can be listed as follows. First, the
probability that the timing critical signal is shifted. The line bounding box and the TSV block can be non-overlapped. In
denoted as “Unaware” represents that the timing critical signal this situation, only going through a TSV on the boundary of
has equal probability to be located at any position of a TSV- the TSV block can result in minimum wire length. Next, the
chain. And the line denoted as “Timing Aware” represents that TSV block can be either partially or completely overlapped by
the timing ctitical signal is always located at the beginning the bounding box. In this situation, any TSV that is overlapped
of a TSV-chain. Assume that the failure rate of each TSV by the bounding box can result in minimum wire length.
is identical and there is only one failed TSV. The result in Unless the bounding box is completely contained in the TSV
Figure 8 shows that, in “Unaware” cases, the probabilities for block, a TSV on the boundary of the TSV block can always
the timing critical signal to be shifted are greater than 50% be found for minimum wire length. The discussion shows
in all cases. On the contrary, by assigning the timing critical that, TSVs on the boundary of a TSV block have higher
 3D Partitioning:
TSVs required for signal on each tier is determined

3D Floorplanning:
TSV Block are determined
1. Partitioning is required for large TSV blocks
2. The size of each TSV block is limited
Boundary of a Tier Corner of a Tier

(a) Spiral-Style (b) Snake-Style (c) Hybrid

Based on the position of each TSV block, determine
the structure of each TSV-chain

Fig. 9. Chaining Styles Placement

probabilities to be routed through for minimum wire length. 3D Routing:

These TSVs should be assigned as head parts of TSV-chains. Assignment of signals to TSVs
A spiral-style chaining policy is proposed for TSV-chain Considering the structure of each TSV-chain
when perform the assignment of signals to TSVs
design. In a TSV block, by picking a TSV in the central
position to be the starting point, spiral-style chaining results Fig. 10. Proposed Design Flow for TSV-Chain
in a routing path where all TSVs on the boundary are at one VI. C ONCLUSION
end. The starting TSV is assigned as redundant TSV while the
other end becomes the head of a TSV-chain. An example for a In this paper, a new redundant TSV architecture with
4 × 5 TSV block is shown in Figure 9(a) where TSVs in grey reasonable cost for ASICs has been proposed. Design issues
are head and good for timing critical signals. In routing stage, including recovery rate and timing problem have been inves-
routers can choose to assign timing-critical signals to TSVs tigated. Required modications on the design ow has been
that are on the boundary of a TSV block. This can reduce the explained. Based on probabilistic models, the new design can
probability for a timing critical signal to be shifted. successfully recover most of the failed chips and increase the
The spiral-style chaining policy is appropriate for a TSV yield of TSV bonding to 99.99%. This can effectively reduce
block that is not on the boundary or the corner of a tier. the cost of manufacturing 3D designs.
For a TSV block located on the boundary of a tier, most R EFERENCES
signals assigned to that TSV block are connected from the
[1] W. R. Davis, J. Wilson, S. Mick, davis demystifying 3D et al.,
opposite side of the tier boundary. In this case, a snake-style “Demistifying 3D ICs: The Pros and Cons of Going Vertical,” IEEE
chaining policy satises the requirement. The result is shown Design Test of Computer, vol. 22, no. 6, pp. 498-510, Nov./Dec., 2005.
in Figure 9(b). For a TSV block located on the corner, most [2] J. Burns, L. Mcllrath, C. Keast, et al., “Three-Dimensional Integrated
Circuit for Low Power, High-Bandwidth Systems on a Chip,” ISSCC
signals assigned to that TSV block are connected from the Dig. of Tech. Papers, pp. 268-269, Feb., 2001.
counter direction of the tier corner. In this case, a hybrid [3] S. Siesshoefer and et al., “Z-axis Interconnect Using Fine Pitch,
chaining policy as shown in Figure 9(c) becomes the best Nanoscale Through Silicon Vias: Process Development,” ECTC, 2004.
candidate. Based on the position of each TSV block, one of [4] P. Morrow, M. J. Kobrinsky, S. Ramanathan, et al., “Wafer-Level 3D
Interconnects via Cu Bonding,” Proceedings of the Advanced Metalliza-
these three chaining policies can be applied to determine the tion Conference, pp. 125-130, 2004.
structure of a TSV-chain. [5] Philip Garrou, Christopher Bower, and Peter Ramm, “Handbook of
3D Integration: Technology and Application of 3D Integrated Circuits
C. Physical Design Flow Considering TSV-Chain Volume 1 & 2,” poblished by WILEY-VCH Verlag GmbH & Co. KGaA,
Weinheim, 2008, ISBN: 978-3-527-32034-9.
In current design ow for 3D ICs , 3D partitioning rst [6] Uksong Kang, Hoe-Ju Chung, Seongmoo Heo, et al., “8Gb 3D DDR3
takes place to determine which tier each design blocks to be DRAM Using Through-Silicon-Via Technology,” ISSCC Dig. of Tech.
placed. The number of required TSVs for signals between two Papers, pp. 130-131, Feb., 2009.
[7] Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita and Luca
consecutive tiers is determined in this stage. Next, in oorplan Benini, “A Low-Overhead Faule Tolerance Scheme for TSV-Based 3D
stage, blocks with x area but unknown dimensions are placed Network on Chip Links,” ICCAD, 2008.
in each tier. To provide communication links between blocks [8] Hsien-Hsin S. Lee and Krishnendu Chakrabarty, “Test Challenges for
3D Integrated Circuits,” IEEE Design & Test of Computers, vol. 26, no.
in different tiers, TSV blocks are placed. The number of sig- 5, pp. 26-35, Sep./Oct., 2009.
nals to be assigned to each TSV block as well as the position [9] R. Patti, “Three-Dimensional Integrated Circuits and the Future of
of each TSV block are roughly determined in this stage. Based System-on-Chip Designs,” Proc. of the IEEE, vol. 84, no. 6, June 2006.
on the discussion in Section IV, the number of TSVs in each [10] A. W. Topol, J. D. C. La Tulipe, L. Shi, et al., “Three Dimensional
Integrated Circuits,” IBM Journal of Research and Development, vol.
TSV block should be limited. Partitioning may be required 50, no. 4/5, pp. 491-506, July/Sepetember 2006.
for large TSV blocks. Based on the position of each TSV [11] R. Patti, “Impact of Wafer-Level 3D Stacking on the Yield of ICs,”
block, the structure of each TSV-chain is determined. In place Future Lab Intl., issue 23, July 2007.
[12] N. Miyakawa, “A 3D Prototyping Chip based on a Wafer-Level Stacking
and route stage, routers should be aware of the TSV-chain Technology,” ASP-DAC, Jan. 2009.
structure in each TSV block. Based on design constraints and [13] B. Swinnen, W. Ruythooren, et al., “3D Integration by Cu-Cu Thermo-
requirements, router needs to decide whether to assign timing Compression Bonding of Extremely Thinned Bulk-Si Die Containing
critical signals to TSVs that are located at the head of TSV- 10 𝜇m Pitch Through-Si Vias,” IEDM, Dec. 2006.
[14] A. W. Topol, et al., “Enabling SOI-Based Assembly Technology for
chains. The overall design ow for TSV-chain is shown in Three-Dimensional Integrated Circuits,” IEDM, Dec. 2005.
Figure 10.