Digital Logic

and
System Design

7. Sequential Logic
COL215, I Semester 2024-2025
Venue: LHC 408
‘E’ Slot: Tue, Wed, Fri 10:00-11:00

Instructor: Preeti Ranjan Panda

[email protected]
www.cse.iitd.ac.in/~panda/
Dept. of Computer Science & Engg., IIT Delhi
Sharing Resources

a b c a b c
• Implement: y = a + b + c
• ...with only ONE adder
• REUSE the adder t=a+b

• Need to STORE
intermediate value y
y=t+c
• t=a+b 2 Adders
Store intermediate value t
• y=t+c Use later for 2nd addition
(C) P. R. Panda, IIT Delhi, 2024
 Complex Computation

a b c d
• Break up complex y=a+b+c–d+e
function/computation
• intermediate values s=a+b t=c-d
s=a+b
• similar to software t=c–d
• Efficient resource u=s+t e
y=u+e
utilization u=s+t
• same adder reused
for several additions
y=u+e
(C) P. R. Panda, IIT Delhi, 2024
New Hardware Components

a b c d
• Elementary operation:
• Store a value
• use it later s=a+b t=c-d
• Control and Sequencing
• Manage order of operations e
• Decide what action is performed by unit u=s+t
(ADD vs SUB)
• Provide alternative paths for operands
y=u+e
(C) P. R. Panda, IIT Delhi, 2024
 Combinational vs. Sequential Logic
inputs

• Combinational: Combinational
• Output is a function only of Logic
present inputs outputs
• Independent of earlier input values
inputs
• Sequential:
• Output is a function of present Sequential
input AND earlier inputs memory Logic

• memory is stored outputs

(C) P. R. Panda, IIT Delhi, 2024

Synchronous Design

• Computation and Storage are associated with CLOCKs

• Periodic signals
• Events triggered at Clock Edges
• positive edge: (0 to 1) transition
• negative edge: (1 to 0) transition

Clock Signal

Positive Negative
Edge Edge

(C) P. R. Panda, IIT Delhi, 2024

Alternative: Asynchronous Design

• No common clock
• Completion signalled by individual components
• Contrast: In Synchronous Design completion is checked only at
clock edges

(C) P. R. Panda, IIT Delhi, 2024

 Storage Element: SR Latch

R (reset)
Q

Q’ (complement of Q)
S (set)

1 1 0 0
R (reset) R 0 R (reset) R 1
Q Q Q Q

Q’ Q’ Q’ Q’
S (set) 0 S 0 1 S (set) 1 S 1 0

RS = 10: Outputs QQ’=01 (Q reset to 0) RS = 01: Outputs QQ’=10 (Q set to 1)

(C) P. R. Panda, IIT Delhi, 2024
 Storing the Q value

R (reset)
Q

Q’ (complement of Q)
S (set)

0 0 0 0
R (reset) 0 R 0 R (reset) 1 R 1
Q Q Q Q

Q’ Q’ Q’ Q’
S (set) 0 1 S 0 1 S (set) 0 0 S 0 0

RS = 00: Outputs QQ’=01 maintained (no change) RS = 00: Outputs QQ’=10 maintained (no change)
(C) P. R. Panda, IIT Delhi, 2024
 Unstable conditions in SR Latch
1 1 0 0
R (reset) R 0 R 0 R 1
Q Q Q Q

Q’ Q’ Q’ Q’
S (set) 1 S 1 0 S 0 0 S 0 1

RS = 11: Outputs QQ’=00 RS = 00: Outputs QQ’=11

0 0
R 0 R 1
Q Q

Q’ Unstable (Oscillating QQ’)

0
Q’
S 0 S 0 1
SR=11 is NOT ALLOWED!
Outputs QQ’=00 Outputs QQ’=11
(C) P. R. Panda, IIT Delhi, 2024
 We have a storage/memory device!

1 0 0 0
R 0 R 1 R 1 R 0
Q Q Q Q

Q’ Q’ Q’ Q’
S 0 1 S 1 0 S 0 0 S 0 1

RS = 10: Output Q=0 RS = 01: Output Q=1 RS = 00: Output Q unchanged

S R Q Q’
Working of the SR Latch 1 0 1 0
• Normally, SR=00 0 0 1 0
• If Q=0 needed, make SR=01. Return to SR=00.
0 1 0 1
• If Q=1 needed, make SR=10. Return to SR=00. Not Allowed
• Don’t set SR=11 0 0 0 1
• Don’t go directly from SR=01 to SR=10 1 1 0 0
(C) P. R. Panda, IIT Delhi, 2024
Function Table
 SR Latch with NAND gates

S (set) Q

R (reset) Q’ (complement of Q)

0 0 1 1
S (set) S 1 S (set) S 0
Q Q Q Q

R (reset) Q’ R 0 Q’ R (reset) Q’ R 1 Q’
1 1 0 0

SR = 01: Outputs QQ’=10 (Q set to 1) SR = 10: Outputs QQ’=01 (Q reset to 0)

(C) P. R. Panda, IIT Delhi, 2024
 Storing the Q value

S (set) Q

R (reset) Q’

1 1 0 1 1
S 0 S S 1 S 1
Q Q Q Q

R Q’ R Q’ R Q’ R Q’
1 1 1 1 1 0 1 0

SR = 11: Outputs QQ’=01 maintained (no change) SR = 11: Outputs QQ’=10 maintained (no change)

(C) P. R. Panda, IIT Delhi, 2024

 Unstable conditions in NAND Latch

0 0 1 1 0
S S 1 S 1 S
Q Q Q Q

R Q’ R Q’ R Q’ R 0
Q’
0 0 1 1 1 1
SR = 00: Outputs QQ’=11 SR = 11: Outputs QQ’=00

1 1 0
S 1 S
Q Q

Q’ Q’ Unstable (Oscillating QQ’)

R 1 R 0
1 1
SR=00 is NOT ALLOWED!
Outputs QQ’=00 Outputs QQ’=11
(C) P. R. Panda, IIT Delhi, 2024
 NAND latch is also a storage/memory device

0 1 1 0 1
1 0 S S 1
S Q S Q Q Q

R Q’ R Q’
R 0 Q’ R 1 Q’ 1 1 1 0
1 0
SR = 01: Output Q=1 SR = 10: Output Q=0 SR = 11: Output Q unchanged
S R Q Q’
Working of the NAND SR Latch 0 1 1 0
• Normally, SR=11 1 1 1 0
• If Q=0 needed, make SR=10. Return to SR=11.
1 0 0 1
• If Q=1 needed, make SR=01. Return to SR=11. Not Allowed
• Don’t set SR=00 1 1 0 1
• Don’t go directly from SR=01 to SR=10 0 0 1 1
(C) P. R. Panda, IIT Delhi, 2024
Function Table
NAND/NOR Latch needs enhancement

• Signal to enable writing

• When enabled, S and R are complements (01 or 10)

(C) P. R. Panda, IIT Delhi, 2024

Ensuring complement

S (set)
Q

Derive R from S?

R (reset) Q’

Unsafe. May transition through SR=00

(C) P. R. Panda, IIT Delhi, 2024

Enabling writing

En
• En (enable) signal
S (set)
x
• When En=0: x = y = 1 Q
• save state
• When En = 1:
• x = S’ Q’
R (reset) y
• y = R’

• What should go here?

(C) P. R. Panda, IIT Delhi, 2024

The D (data) Latch

• En (enable) signal
• When En=0: x = y = 1 D
• save state
x
• When En = 1: Q
• x = D’
• y=D En
• D input ignored when En = 0
Q’
• When En=1: Q = D y
• Q follows D when En enabled
• Last D value saved when En
disabled

(C) P. R. Panda, IIT Delhi, 2024

 The D Latch Functionality
Q follows D when En is ON
D
Q
En
En Q’

previous
Q value
D En D Q previous
0 0 q Q value
0 1 q En D Q
1 0 0 0 x q
Q
1 1 1 1 x D
Function Function
Table Table
(C) P. R. Panda, IIT Delhi, 2024
Concerns about Latches

• D input might be function of Combinational

output Q of same latch Logic
• loop in signal path
• OK in sequential designs D
• En might be ON for entire
duration Q
• ...causing oscillations En
• Safety: in Latch-based designs,
need to be careful of Q’
feedback/loop paths
• e.g., use different En signals in
different latch stages

(C) P. R. Panda, IIT Delhi, 2024

 Master-Slave Flip-Flop
R follows D when Clock=1 (Master Enabled)

Clock
Master Slave
D-Latch D-Latch
D R Q D
D Q D Q

En En R

Q
Clock

Clock=1: Master Enabled. Slave disabled. Q follows R when Clock=0 (Slave Enabled)
Clock=0: Slave Enabled. Master disabled.

(C) P. R. Panda, IIT Delhi, 2024

 Master-Slave Flip-Flop

Clock
Master Slave
D-Latch D-Latch
D R Q D
D Q D Q

En En R

Q
Clock

Clock=1: Master Enabled. Slave disabled.

Clock=0: Slave Enabled. Master disabled.
D→Q on Negative Edge of Clock

(C) P. R. Panda, IIT Delhi, 2024

D Flip-flop: Alternative Design

Clk = 0:

3 SR Latches
S
1 Q
Clk
Maintain Q,Q’
0
1 Q’
R

(C) P. R. Panda, IIT Delhi, 2024

 D Flip-flop: Alternative Design

Clk = 0→1, D = 0 Clk = 0→1, D = 1

D→Q on Clk edge

No changes later
S S
1 Q 1 Q
Clk Clk
0→1 0→1
1 Q’ 1 Q’
R R

D D
0 1

Clk=0→1 causes R=1→0, Q=0 Clk=0→1 causes S=1→0, Q=1

Further changes in D? Further changes in D?
(C) P. R. Panda, IIT Delhi, 2024
Positive Edge-triggered Flip-flop

• D is transferred to Q at rising Clk edge

• No changes on falling Clk edge
• No changes in rest of Clk period

(C) P. R. Panda, IIT Delhi, 2024

Flip-flop Timing Considerations

Hold Time
Setup Time
D needs to be constant for this
D needs to be constant for this
duration after clock edge
duration before clock edge
Minimum Pulse Width
Clock needs to be constant
for at least this duration

Clock

(C) P. R. Panda, IIT Delhi, 2024

Other flip-flop designs

• T flip-flop
• T=0: Q=q
• T=1: Q=NOT q
• JK flip-flop
• J=1,K=0: Q=1
• J=0,K=1: Q=0
• J=1,K=1: Q=NOT q
• J=0,K=0: Q=q
(C) P. R. Panda, IIT Delhi, 2024
T (Toggle) Flip-Flop

T Flip-flop Specification

On clock edge: • T=0: Q=q maintain state

• T=1: Q=NOT q invert

q
Q
? D Q
T
Clk
Clock

(C) P. R. Panda, IIT Delhi, 2024

T Flip-Flop implemented using D Flip-flop
T Flip-flop Specification
T q Q • T=0: Q=q
0 0 0 • T=1: Q=NOT q
0 1 1 Q=q
1 0 1 Q= NOT q
1 1 0
Function Table q
Q
D Q
T
Q=q⊕T Clk
Clock
On clock edge: Q takes the value of q ⊕ T
(q ⊕ T) is sent to D input

(C) P. R. Panda, IIT Delhi, 2024

JK Flip-Flop

Specification
• J=1,K=0: Q=1
On clock edge: • J=0,K=1: Q=0
• J=1,K=1: Q=NOT q
• J=0,K=0: Q=q

q
Q
J ? D Q
K
Clk
Clock

(C) P. R. Panda, IIT Delhi, 2024

 JK Flip-Flop implemented using D Flip-flop
Specification
Function Table • J=1,K=0: Q=1
On clock edge: • J=0,K=1: Q=0
J K q Q
• J=1,K=1: Q=NOT q
0 0 0 0 K-map for Q • J=0,K=0: Q=q
Q=q
0 0 1 1 JK Jq’
q 00 01 11 10
0 1 0 0 Q= 0 0 0 0 1 1
0 1 1 0
1 0 0 1 1 1 0 0 1 q’
Q=1 Q
1 0 1 1
K’q J D Q
1 1 0 1
1 1 1 0
Q=NOT q K Clk
Q’
Q = Jq’ + K’q
q Clock
On clock edge: Q takes the value of Jq’ + K’q
This is sent to D input
(C) P. R. Panda, IIT Delhi, 2024
Latches vs. Flip-flops

• Latches are Level-triggered

• Q follows D when En=1 (level = 1)
• Flip-flops are Edge-triggered
• D value captured on clock edge
• Feedback/loop is eliminated

(C) P. R. Panda, IIT Delhi, 2024

 D Flip-flop: Asynchronous Inputs

New Input RESET:

RESET=0 causes Q=0

S S
Q Q
Clk Clk

Q’ R
Q’
R

D RESET acts
D independently
RESET of Clk, D
RESET Asynchronous Reset
??
(C) P. R. Panda, IIT Delhi, 2024
Characteristic Tables: Flip-flop Properties

D Q (t+1) J K Q (t+1)
0 0 Reset 0 0 Q(t) No change
1 1 Set 0 1 0 Reset
1 0 1 Set
D Flip-flop 1 1 Q’(t) Complement
Characteristic Table
JK Flip-flop
T Q (t+1) Characteristic Table
0 Q(t) No change
1 Q’(t) Complement

T Flip-flop
Characteristic Table

(C) P. R. Panda, IIT Delhi, 2024

Characteristic Equations

D Q (t+1) J K Q (t+1)
0 0 Reset 0 0 Q(t) No change
1 1 Set 0 1 0 Reset
1 0 1 Set
D Flip-flop 1 1 Q’(t) Complement
Q (t+1) = D
JK Flip-flop
T Q (t+1) Q (t+1) = Q’J + QK’
0 Q(t) No change
1 Q’(t) Complement
Q (= Q(t)): Value of Q just before clock edge
T Flip-flop
Clock is implicit (not written in equation)
Q (t+1) = Q ⊕ T

(C) P. R. Panda, IIT Delhi, 2024

 Analysing Clocked Sequential Circuits

x A
• All clocked sequential D Q
circuits have: Clk
A’
• Inputs
• Outputs
• Combinational logic B
D Q
• functions of inputs and Qs
B’
• A set of flip-flops (any type) Clock Clk
• A clock (common to all flip-
flops) y

(C) P. R. Panda, IIT Delhi, 2024

 Deriving State Equations

x A Equations for new values of A, B, y:

D Q
A(t+1) = A(t) x (t) + B (t) x (t)
A’ B(t+1) = A’ (t) x (t)
Clk
y = x’ (t)(A (t) +B (t))

Simplify: Drop the (t)

A(t+1) = Ax + Bx
B B(t+1) = A’x
D Q
y = x’(A+B)
Clock B’
Clk
Generates A, B, y values in next clock cycle
in terms of values in current clock cycle
y

(C) P. R. Panda, IIT Delhi, 2024

 Sequential Designs

State
next
Register present
state f
F D Q state
Clk
G g
D Q
Clk
a Combinational preset next
inputs b Logic i/p state state o/p
c a b c f g h F G H x y
H D Q h 0 0 0 0 0 0 0 1 0 1 0
• on clock edge: F,G,H →f,g,h Clk 0 0 0 0 0 1 0 1 0 1 0
x
• clock implicit y
• Given circuit, we can derive state table outputs state table
• Given state table, can derive circuit (C) P. R. Panda, IIT Delhi, 2024
 Deriving State Table

State Table
x A a
D Q a b x A B y
0 0 0 0 0 0
Clk 0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
b 1 0 0 0 0 1
B
D Q 1 0 1 1 0 0
1 1 0 0 0 1
Clock Clk 1 1 1 1 0 0

(C) P. R. Panda, IIT Delhi, 2024

 State Diagram (Finite State Machine - FSM)
Q values of Flip-flops together constitute the State of the system
Our design has 4 states: 00, 01, 10, 11 (ab/AB values)

State Table State Diagram State Transition

present next x=0/y=0 Condition/Action
state state
1/0
a b x A B y Present
0 0 0 0 0 0 00 01 Next
0/1 State State
0 0 1 0 1 0
0 1 0 0 0 1 0/1 1/0
0/1 Each Row in State Table becomes:
0 1 1 1 1 0
one Edge/State Transition in FSM
1 0 0 0 0 1 10 11
1 0 1 1 0 0
Same x=1/y=0
1 1 0 0 0 1
Information
1 1 1 1 0 0 x=1/y=0
(C) P. R. Panda, IIT Delhi, 2024
 Sequential Analysis

State Table State Diagram

Sequential Design present next x=0/y=0
state state 1/0
x a b x A B y
D Q A 00 01
0 0 0 0 0 0 0/1
Clk A’
0 0 1 0 1 0
0 1 0 0 0 1 0/1 1/0
D Q B 0/1
Clock Clk B’ 0 1 1 1 1 0
1 0 0 0 0 1 10 11
y
1 0 1 1 0 0 x=1/y=0
1 1 0 0 0 1
1 1 1 1 0 0 x=1/y=0
Synthesis

(C) P. R. Panda, IIT Delhi, 2024

Example Finite State Machine

Specification: Counter Strategy

Output P = 1 every 3rd clock cycle • Let us count: 0, 1, 2, 0, 1, 2, 0, 1, 2....
Output P = 0 in other cycles • Every time we hit 0, set P=1
If input R = 0, reset count to zero
If input R = 1, resume counting
FSM (States + Transitions)
R=1/P=0
States
00 1st cycle 00 01

2nd cycle main loop

01
10 3rd cycle R=1/P=1 R=1/P=0

10

(C) P. R. Panda, IIT Delhi, 2024

Example Finite State Machine

Specification: Counter Strategy

Output P = 1 every 3rd clock cycle • Let us count: 0, 1, 2, 0, 1, 2, 0, 1, 2....
Output P = 0 in other cycles • Every time we hit 0, set P=1
If input R = 0, reset count to zero
If input R = 1, resume counting
FSM (States + Transitions)
R=1/P=0
States
R=0/P=0 00 01
00 1st cycle R=0/P=0
2nd cycle main loop
01
R=0/P=0
10 3rd cycle R=1/P=1 R=1/P=0

10
Assume: P=0 upon reset
(C) P. R. Panda, IIT Delhi, 2024
Deriving State Table from FSM

present next
state state
FSM (States + Transitions)
R=1/P=0 a b R A B P
0 0 0 0 0 0
R=0/P=0 00 01
R=0/P=0 0 0 1 0 1 0
main loop 0 1 0 0 0 0
R=0/P=0 0 1 1 1 0 0
R=1/P=1 R=1/P=0
1 0 0 0 0 0
1 0 1 0 0 1
10
1 1 0 - - -
1 1 1 - - -

(C) P. R. Panda, IIT Delhi, 2024

Deriving Sequential Design from State Table

present next
state state
next State
a b R A B P present a state Register
0 0 0 0 0 0 state A
D Q
0 0 1 0 1 0
b Combi- Clk
0 1 0 0 0 0
0 1 1 1 0 0 national
B
1 0 0 0 0 0 Logic D Q
1 0 1 0 0 1 R Clk
1 1 0 - - - P
1 1 1 - - -

(C) P. R. Panda, IIT Delhi, 2024

Boolean Expressions for Next State, Output

K-map for A K-map for B

present next ab ab
state state 00 01 11 10 00 01 11 10
R R
0 0 0 x 0 0 0 0 x 0
a b R A B P
0 0 0 0 0 0 1 0 1 x 0 1 1 0 x 0
0 0 1 0 1 0 A = bR B = a’b’R
0 1 0 0 0 0
0 1 1 1 0 0 K-map for P
1 0 0 0 0 0 ab
00 01 11 10
1 0 1 0 0 1 R
0 0 0 x 0
1 1 0 - - -
1 1 1 - - - 1 0 0 x 1
P = aR
(C) P. R. Panda, IIT Delhi, 2024
 Gate-level Design

K-map for A K-map for B present

ab ab state
00 01 11 10 00 01 11 10
R R next State
0 0 0 x 0 0 0 0 x 0 a
state Register
1 0 1 x 0 1 1 0 x 0 A Q
D
A = bR B = a’b’R Clk
b
K-map for P
ab
00 01 11 10 B
R D Q
0 0 0 x 0
Clk
1 0 0 x 1 P
R
P = aR

(C) P. R. Panda, IIT Delhi, 2024

 What if we used a different sequence?

FSM (States + Transitions) Replace FSM (States + Transitions)

R=1/P=0 00 by 11 R=1/P=0
R=0/P=0 00 01 R=0/P=0 00 01
R=0/P=0 R=0/P=0
main loop main loop
R=0/P=0 R=0/P=0
R=1/P=1 R=1/P=0 R=1/P=1 R=1/P=0

10 11

Specification
What changes? Sequence of states: 0,1,3,0,1,3,...
Output P = 1 every 3rd clock cycle
What remains unchanged? Output P = 0 in other cycles Output P sequence unchanged!
Is the functionality still delivered? If input R = 0, reset count to zero Specification still met.
If input R = 1, resume counting Values 00, 01, etc., don’t matter
(C) P. R. Panda, IIT Delhi, 2024
 FSM States can be Symbolic

FSM (States + Transitions) FSM (States + Transitions)

R=1/P=0 Replace by: R=1/P=0
R=0/P=0 00 01 R=0/P=0 X Y
R=0/P=0 R=0/P=0
main loop main loop
R=0/P=0 R=0/P=0
R=1/P=1 R=1/P=0 R=1/P=1 R=1/P=0

10 Z

Specification still met.

Values 00, 01, etc., don’t matter
States can be Symbolic (labelled X, Y, Z)

(C) P. R. Panda, IIT Delhi, 2024

 Start with Symbolic FSM
Specification
Output P = 1 every 3rd clock cycle
Output P = 0 in other cycles
If input R = 0, reset count to zero
If input R = 1, resume counting

State Encoded FSM

FSM (Symbolic States + Transitions)
Encoding/
R=1/P=0 R=1/P=0
State
R=0/P=0 X Assignment R=0/P=0 00 01
Y
R=0/P=0 R=0/P=0
main loop main loop
R=0/P=0 R=0/P=0
R=1/P=1 R=1/P=0 X=00 R=1/P=1 R=1/P=0
Y=01
Z Z=10 10
Other encodings also valid
(C) P. R. Panda, IIT Delhi, 2024
 Symbolic State Table
Encoded State Table
Symbolic State Table (Truth Table)

FSM (Symbolic States + Transitions) PS R NS P present next

R=1/P=0 X 0 X 0 state state
X 1 Y 0 a b R A B P
R=0/P=0 X Y
R=0/P=0 Y 0 X 0 0 0 0 0 0 0
main loop Y 1 Y 0 0 0 1 0 1 0
R=0/P=0 Z 0 X 0 0 1 0 0 0 0
R=1/P=1 R=1/P=0
Z 1 X 1 0 1 1 1 0 0
Z 1 0 0 0 0 0
PS: present state
1 0 1 0 0 1
NS: next state
No need for
don’t care rows
(C) P. R. Panda, IIT Delhi, 2024
Finally, Sequential Circuit

present
Encoded State Table state
(Truth Table)
a next State
present next state Register
state state A Q
D
a b R A B P Clk
0 0 0 0 0 0 b
0 0 1 0 1 0
0 1 0 0 0 0 B
D Q
0 1 1 1 0 0
1 0 0 0 0 0 Clk
P
1 0 1 0 0 1
R

(C) P. R. Panda, IIT Delhi, 2024

Another FSM Example

• Design a Sequence Detector

• Detect a sequence of 3 or more 1’s on an input line
Input: 0 1 1 0 1 1 1 0 1 0 1 1 1 1 0 1...
One bit per clock
Output: 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0...

• Design FSM
• Inputs? Outputs? States? Transitions?
(C) P. R. Panda, IIT Delhi, 2024
FSM Design

Input: 0 1 1 0 1 1 1 0 1 0 1 1 1 1 0 1
Output: 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0
0/0 1/0
Style: Mealy Machine
S0 S1 Output is a function of both state and input.
0/0 Output is associated with transition.

0/0 1/0 Alternative Style: Moore Machine

0/0 Output is a function of state only
(Ref: Textbook. Figure 5.27)
S2 S3
The 2 styles are equivalent
1/1 1/1
(C) P. R. Panda, IIT Delhi, 2024
 Organising complex designs

• Controller + Datapath
Control
• Controller: FSM (sends control signals)
Signals
• What activity to enable in each clock cycle?
• MUX select inputs FSM
Datapath
• Load enable signals to flip-flops/registers (Controller)

• Datapath: Computation
Status
• Adders, Multipliers, MUXes Signals
• May send status signals back to FSM
• results of comparisons
• overflow/exceptions

(C) P. R. Panda, IIT Delhi, 2024

 Specifying FSMs in HDL

VHDL Model
VHDL
Present State Signal entity...
port...
end entity
architecture...
VHDL signal...
VHDL Comb Output process...
State
Input Logic Port -- state register
Register
Port end process
Inputs: Next process...
State Outputs:
Status -- comb. logic
VHDL VHDL Control
Signals end process
Process Process Signals
end architecture

(C) P. R. Panda, IIT Delhi, 2024

 State Register in VHDL

State Register states State Register with Reset

type state_type is (ADD, SUB); initial state process (clk, reset)

signal cur_state : state_type := ADD; begin
signal next_state : state_type := ADD; initial/reset
if (reset = '1') then
state
cur_state <= ADD;
process (clk) rising edge
elsif (clk'EVENT AND clk = '1') normal
begin then function
if (clk'EVENT AND clk = '1') then cur_state <= next_state;
cur_state <= next_state; end if;
end if; end process;
Q <= D
end process;

• Synthesised into set of D flip-flops

Source: COL215 Hardware Assignment
• #flip-flops (#bits) not specified here (automatically inferred) Author: Naman Jain
(C) P. R. Panda, IIT Delhi, 2024
 Next State and Output Logic in VHDL

process (cur_state, M, Done)

begin M cntrl_add_sub
Done
next_state <= cur_state;

case cur_state is 11/1

when ADD =>
if Done = '1' and M = '1' then
ADD SUB
next_state <= SUB; 0-/0
cntrl_add_sub <= '1’;
elsif Done = '0' then
next_state <= ADD;
cntrl_add_sub <= '0’;
end if;
when SUB => ... Source: COL215 Hardware Assignment
end case; Author: Naman Jain
end process; (C) P. R. Panda, IIT Delhi, 2024
 Next State and Output Logic in VHDL

process (cur_state, M, Done) ...

begin when SUB =>
next_state <= cur_state; if Done = '1' and M = '0' then 11/1
next_state <= ADD;
case cur_state is cntrl_add_sub <= '0’; ADD SUB
when ADD => 0-/0 0-/1
elsif Done = '0' then
if Done = '1' and M = '1' then next_state <= SUB;
next_state <= SUB; cntrl_add_sub <= '1’; 10/0
cntrl_add_sub <= '1’; end if;
elsif Done = '0' then end case;
next_state <= ADD; end process;
cntrl_add_sub <= '0’;
end if;
... Source: COL215 Hardware Assignment
Author: Naman Jain
(C) P. R. Panda, IIT Delhi, 2024
 Step 0 Step 1 Step 2
S2 S2 S2
State Reduction: S1 S1
S1
Equivalent States S0 S0 S0
S3 S2 S1 S3 S2 S1 S3 S2 S1
0/0 1/0 S0: 0/0 1/0 S0: 0/0 1/0
S3: 0/0 1/1 S2: 0/0 1/1
S0 S1
0/0 O/P Conflict O/P Conflict

0/0 1/0 Step 3 Step 4 Step 5

0/0
S2 S2 S2
S2 S3
S1 S1 S1
1/1 1/1 S0 ? S0 ? S0 ?
2 States are equivalent if: S3 S2 S1 S3 S2 S1 S3 S2 S1
For every input: S0: 0/0 1/0 S3: 0/0 1/1 S2: 0/0 1/1
• Same output values S1: 0/0 1/0 S1: 0/0 1/0 S1: 0/0 1/0
• Same/Equivalent next states O/P Compatible O/P Conflict O/P Conflict
(C) P. R. Panda, IIT Delhi, 2024
 Step 5 Step 6

State Reduction :
S2 S2 ?
S1 S1
Equivalent States S0 ? S0 ?
S3 S2 S1 S3S2 S1
0/0 1/0 S2: 0/0 1/1 S2: 0/0 1/1
S1: 0/0 1/0 S3: 0/0 1/1
S0 S1
0/0 O/P Conflict O/P Compatible
0/0 1/0 Step 7 Step 8
0/0
S2 ? S2 ✓
S2 S3
S1 S1
1/1 1/1
S0 S0
S3 S2 S1 S3 S2 S1
S0: 0/[0,S0] 1/[0,S1] S2: 0/[0,S0] 1/[1,S2]
S1: 0/[0,S0] 1/[0,S3] S3: 0/[0,S0] 1/[1/S2]
Next State Conflict Next State Compatible
(C) P. R. Panda, IIT Delhi, 2024
 Reducing the FSM

0/0 1/0 1/0

0/0 0/0 1/0
S0 S1 S0 S1
0/0 S0 S1
0/0 0/0
0/0 1/0 1/0
0/0 0/0 1/0
0/0 0/0
S2 S3 S2 S3 S3
1/1 1/1 1/1 1/1
1/1
Reduced FSM

(C) P. R. Panda, IIT Delhi, 2024