PA RT 2 PROBLEM SOLUTIONS

NOTES ON SOLUTIONS:
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as more challenging than the typical problems.
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1
 Problem Solutions – Chapter 1

LOGIC AND COMPUTER DESIGN FUNDMENTALS – INSTRUCTOR’S MANUAL 2

CHAPTER 7

7-1.
Clock
Reset
Load
C
D 0000 1010 0101 0000
Q 0000 1010 0101

0 ps 40 ns 80 ns

7-2.
Clock
Reset
Load
C
D 0000 1010 0101 0000
Q 0000 1010 0101

0 ps 40 ns 80 ns

7-3.
(a) R1 + 2’s complement of R2 = 2n + R1 - R2. If R1 ≥ R2, the result is ≥ 2n. The 2n gives C = 1.
R1 + 2’s complement of R2 = 2n + R1 - R2, if R1 < R2, the result is < 2n giving C = 0.
(b) If C = 1 then R1 ≥ R2 and there is no borrow.
If C = 0 then R1 < R2 and there is a borrow. Thus, the borrow is the complement of the C status bit.

7-4.*
1001 1001
1100 0011
1000 0001 AND
1101 1011 OR
0101 1010 XOR

7-5.
(a) AND, 1010 1010 1010 1010 (b) OR, 1111 0000 0000 0000
(c) XOR, 0000 1111 1111 0000

7-6.*
sl 1010 0110 sr 0010 1001

3
 Problem Solutions – Chapter 7

7-7.*
Connections to MUX data input 0 and data input 3 remain the same. Qi-1 is connected to MUX data input 2 instead of MUX
Data input 1. Finally, 0 is connected to MUX data input 1.

7-8.*
a) 1000, 0100, 0010, 0001, 1000
b) # States = n

7-9.
a) 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000
b) # States = 2n

7-10.
a) 5 b) 8

7-11.+
Examine an n-bit ripple counter and an n-bit synchronous counter. If either
of these counters cycles through all of its states, there are 2(2n) = 2n+1
transitions for the clock, and there are 2n+1– 2 total transitions for all flip-
flop outputs. For the ripple counter, the clock transitions occur on the
input of only one stage, the 0th stage. For the synchronous counter, the
clock transistions occur on the inputs to all of the n stages. Combining the
transition counts above, the ration of the input + output transitions for the
synchronous counter compared to the ripple counter is:
[n 2n+1 + 2n+1 – 2]/[2n+1 + 2n+1 – 2] ≈ (n + 1) 2n+1/2 (2n+1) = (n+1)/2
Thus, the power dissipated by the synchronous counter is at least as large
as that dissipated by the ripple counter in all cases and grows more rapidly
with the number of stages.

7-12.
CLK
CTR 4 CTR 4 CTR 4 CTR 4
Count EN Q0 EN Q0 EN Q0 EN Q0
Q1 Q1 Q1 Q1
4 x (CO delay) + (C1-C3 delay) Q0-Q3 Q4-Q7 Q8-Q11 Q12-Q15
Q2 Q2 Q2 Q2
= 4 + 1 = 5 AND gates Q3 Q3 Q3 Q3
CO CO CO CO

4
 Problem Solutions – Chapter 7

7-13.+
Enable

EN CTR 8 EN CTR 8
Clock CO CO
Q0-Q7 Q8-Q15

EN CTR 8 EN CTR 8
CO CO
Q16-Q23 Q24-Q31

EN CTR 8 EN CTR 8
Q32-Q39 CO Q40-Q47 CO

Assume delay of XOR = delay of AND.

Delay serial = 2 + 1 + 7(1) + 1 + 1 = 12
EN CTR 8 EN CTR 8 Delay this circuit = 2 + 1+ 2(1) + 1 + 1 = 7
Q48-Q55 CO Q56-Q63 CO Frequency ratio = 12/7

7-14.
CTR 4 CTR 4
CLK CLK
Load Load
1 Count 1 Count
D0 Q 0 D0 Q 0
D1 Q1 D1 Q1
D2 Q2 D2 Q2
D3 Q3 D3 Q3
CO CO

7-15.
Clk

Init CTR 4 CTR 4

Load Load
1 Count Count
D0 Q0 D4 Q4
D1 Q 1 D 5 Q5
D2 Q 2 D 6 Q6
D3 Q 3 D 7 Q7
CO CO

5
 Problem Solutions – Chapter 7

7-16.*
The equations given on page 337 can be manipulated into SOP form as follows: D1 =
Q1, D2 = Q2 ⊕ Q1Q8 = Q1Q2Q8 + Q1Q2 + Q2Q8, D4 = Q4 ⊕ Q1Q2 = Q1Q2Q4 + Q1Q4
+ Q2Q4, D8 = Q8 ⊕ (Q1Q8 + Q1Q2Q4) = Q8(Q1Q8+Q1Q2Q4) + Q8(Q1 + Q8)(Q1 + Q2
+ Q4) = Q1Q2Q4Q8 + Q1 Q8. These equations are mapped onto the K-maps for Table
7-9 below and meet the specifications given by the maps and the table.

D1 Q2 D2 Q2
1 0 0 1 0 1 0 1
1 0 0 1 0 1 0 1
Q4 Q4
Q8 X X X X Q8 X X X X
1 0 X X 0 0 X X
Q1 Q1 To add the enable,
Q2 D8 Q2 change D1 to:
D4
0 0 1 0 0 D1 = Q1 ⊕ EN.
0 0 0
0 1 For the other three func-
1 1 0 0 1 0
Q4 Q4 tions, AND EN with the
X X X X
Q8 Q8 X X X X expression XORed with
0 0 X X 1 0 X X the state variable. The
Q1 Q1 circuit below results.

Q1 Y
D

Q2
D
EN
C

Q4
D

Q8
D

Clock

7-17.*
Present state Next state a) DB = C b) DA = BC + AC
A B C A B C DC = B C DB = A BC + BC
0 0 0 1
0 1 1 0 DC = C
1 0 0 0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 0 0 0

6
 Problem Solutions – Chapter 7

7-18.
Present state Next state DA = ABC + AB
A B C A B C DB = C + AB
0 0 0 0 0 1 DC = A B
0 0 1 0 1 1
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 1 0
1 1 0 0 0 0

7-19.

Present Next DA = B
state state FF Inputs
DB = C
D D D D D
DC = D
A B C D E A B C D E A B C D E
DD = E
0 0 0 0 1 0 0 0 1 0 0 0 0 1 0
0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 DE = A
0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 Use ABCD as counter
0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 0 0 1 0 0 0 0 1

7-20.
The basic cell of the register is as follows:

S1
S0

S1
S0 D Out

S1 C
S0
In
Clock

7-21.*
R1 R2
Load Load
C3
Clock

7-22.
R0 0 MUX R4
1
2 CLK
R1 3S S
1 0
LOAD
R2

R3 C0
C1
C2
C3

7
 Problem Solutions – Chapter 7

7-23.*
R1
C2C1C0 LOAD
C
D0 Q0
D1 Q1
D2 Q2
D3 Q3

R2
LOAD
C
D0 Q0
D1 Q1
D2 Q2
D3 Q3

Clock

7-24.

C0

D A
C1
C

D B

Clock

7-25.

S0

S1 D R0

D R1

Clock

7-26.
D A
CI= S0 for lowest order bit.
C
CI = CO for other bits.
CI
CI
A S D B
S1
B CO CO
C

Clock

8
 Problem Solutions – Chapter 7

7-27.
2x1-Mux
0
1
R0
S0

CB
CC
2x1-Mux
0
1
R1
S0

CA

R2

Clock

7-28.*
a) CLK CTR 4
R2 ADD 4
C1
Load
REG 4 0 CI C1
C2 Count R1
D(0-3) Q(0-3) A(0-3) C(0-3) D(0-3) Q(0-3)
B(0-3) CO CO

R1
b)
C1 REG 4
C2 D(0-3) L Q(0-3)

ADD 4
CI R2
A(0-3) C(0-3) REG 4
B(0-3) CO D(0-3) Q(0-3)
L

Clock

7-29.
The register transfer logic is as follows:

Operation Select Load

S1 S0 L0 L1 L2
CA: R1 <- R0 0 0 0 1 0
CB: R0 <- R1, R2 <- R0 0 1 1 0 1
CC: R1 <- R2, R0 <- R2 1 0 1 1 0

CC S1
CB S0
CB L0
CC
CA L1
CC
CB L2

9
 Problem Solutions – Chapter 7

R0
0 S1 S0
1 LO
2
3-to-1 Mux

R1

L1

R2

L2
Clock

7-30.
Replace multiplexer with:
K1
R1
4 4
R0
4
R2

7-31.*
a) Destination <- Source Registers b) Source Registers -> Destination
R0 <- R1, R2 R0 -> R4
R1 <- R4 R1 -> R0, R3
R2 <- R3, R4 R2 -> R0, R4
R3 <- R1 R3 -> R2
R4 <- R0, R2 R4 -> R1, R2

c) The minimum number of buses needed for operation of the transfers

is three since transfer Cb requires three different sources.

d)

R0 R1 R2 R3 R4

MUX MUX

MUX

7-32.
a) Using two clock cycles, the minimum # of buses is 2 .

b)

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11

MUX MUX

10
 Problem Solutions – Chapter 7

7-33.
Two clock cycles minimum

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9

MUX
MUX

7-34.*
1000, 0100, 1010, 1101 0110, 0011, 0001, 1000

7-35.*
Shifts: 0 1 2 3 4
A 0111 0011 0001 1000 1100
B 0101 0010 0001 0000 0000
C 0 1 1 1 0

7-36.*
library IEEE;
use IEEE.std_logic_1164.all;

entity reg_4_bit is
port (
CLEAR, CLK: in STD_LOGIC;
D: in STD_LOGIC_VECTOR (3 downto 0);
Q: out STD_LOGIC_VECTOR (3 downto 0)
);
end reg_4_bit;

architecture reg_4_bit_arch of reg_4_bit is

begin

process (CLK, CLEAR)

begin
if CLEAR ='0' then --asynchronous RESET active Low
Q <= "0000";
elsif (CLK'event and CLK='1') then --CLK rising edge
Q <= D;
end if;
end process;

end reg_4_bit_arch;

clk
clear
d 0000 1010 0101 1111
q 0000 1010 0101 0000

0 40

11
 Problem Solutions – Chapter 7

7-37.
library IEEE; architecture reg_4_bit_load_arch of reg_4_bit is
use IEEE.std_logic_1164.all; begin
entity reg_4_bit is process (CLK)
port ( begin
LOAD, CLK: in STD_LOGIC; if (CLK'event and CLK='1') then --CLK rising edge
D: in STD_LOGIC_VECTOR (3 downto 0); if LOAD = '1' then
Q: out STD_LOGIC_VECTOR (3 downto 0) Q <= D;
); end if;
end reg_4_bit; end if;
end process;
-- (continued in next column)
endreg_4_bit_load_arch;

clk
load
d 0000 1010 0101 1111
q UUUU 1010 1111

0 40 80

7-38.
library ieee; architecture counter_4_bit_arch of counter_4_bit is
use ieee.std_logic_1164.all; component dff
entity dff is port(CLK, RESET, D: in std_logic;
port(CLK, RESET, D: in std_logic; Q: out std_logic
Q : out std_logic); );
end dff; end component ;
signal D_in, C, Q_out: std_logic_vector(3 downto 0);
architecture pet_pr of dff is
-- Implements positive edge-triggered bit state storage begin
-- with asynchronous reset. C(0) <= EN;
signal state: std_logic; C(1) <= C(0) and Q_out(0);
begin C(2) <= C(1) and Q_out(1);
Q <= state; C(3) <= C(2) and Q_out(2);
process (CLK, RESET) CO <= C(3) and Q_out(3);
begin
if (RESET = '1') then D_in(0) <= C(0) xor Q_out(0);
state <= '0'; D_in(1) <= C(1) xor Q_out(1);
else D_in(2) <= C(2) xor Q_out(2);
if (CLK'event and ClK = '1') then D_in(3) <= C(3) xor Q_out(3);
state <= D;
end if; bit0: dff
end if; port map (Clock, Reset, D_in(0), Q_out(0));
end process; bit1: dff
end; port map (Clock, Reset, D_in(1), Q_out(1));
bit2: dff
library IEEE; port map (Clock, Reset, D_in(2), Q_out(2));
use IEEE.std_logic_1164.all; bit3: dff
entity counter_4_bit is port map (Clock, Reset, D_in(3), Q_out(3));
port (
Clock, Reset, EN: in STD_LOGIC; Q <= Q_out;
Q: out STD_LOGIC_VECTOR (3 downto 0);
CO: out STD_LOGIC end counter_4_bit_arch;
);
end counter_4_bit;

clock
reset
en
q 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000
co

0 100 200 300 400

12
 Problem Solutions – Chapter 7

7-39.*
module register_4_bit (D, CLK, CLR, Q) ;

input [3:0] D ;
input CLK, CLR ;
output [3:0] Q ;
reg [3:0] Q ;

always @(posedge CLK or negedge CLR)

begin
if (~CLR) //asynchronous RESET active low
Q = 4'b0000;
else //use CLK rising edge
Q = D;
end
endmodule

CLK
CLR

D 0000 1010 0101 1111

Q 0000 1010 0101 0000

0 20 40 60

7-40.
module register_4_bit_load (D, CLK, LOAD, Q) ;

input [3:0] D ;
input CLK, LOAD ;
output [3:0] Q ;
reg [3:0] Q ;

always @(posedge CLK)

begin
if (LOAD)
Q = D;
end
endmodule

CLK
LOAD
D 0000 1010 0101 1111
Q 1010 1111

0 20 40 60 80

13
 Problem Solutions – Chapter 7

7-41.
// 4-bit Binary Counter C[0] = EN,
C[1] = C[0] & Q[0],
// Positive Edge-Triggered D Flip-Flop with Reset: C[2] = C[1] & Q[1],
C[3] = C[2] & Q[2],
module dff_v(CLK, RESET, D, Q); CO = C[3] & Q[3];
input CLK, RESET, D;
output Q; assign
reg state; D_in[0] = C[0] ^ Q[0],
D_in[1] = C[1] ^ Q[1],
assign Q = state; D_in[2] = C[2] ^ Q[2],
D_in[3] = C[3] ^ Q[3];
always @(posedge CLK or posedge RESET)
begin
if (RESET) dff_v
state <= 0; g1(Clock, Reset, D_in[0], Q[0]),
else g2(Clock, Reset, D_in[1], Q[1]),
state <= D; g3(Clock, Reset, D_in[2], Q[2]),
end g4(Clock, Reset, D_in[3], Q[3]);
endmodule
endmodule
module Counter_4bit (Clock, Reset, EN, Q, CO) ;

input Clock, Reset, EN ;

output [3:0] Q ;
output CO ;
wire[3:0] Q ;

wire [3:0] C, D_in;

// (continued in next column)

Clock
Reset
EN
Q 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000

CO

0 100 200 300

14
Problem Solutions – Chapter 7

15
CHAPTER 8

8-1.*
S0
Z1 = 0 Inputs: X1X2
Z2 = 0 Outputs: Z1Z2

0 1
X1
S1
Z1 = 0
Z2 = 1

00 01
X1X2
10 11

S2
Z1 = 1
Z2 = 0

00 01
X1X2
11 10

8-2.*
A: 0 1 1 0 1 1 0 1
B: 1 1 0 1 0 1 0 1
C: 0 1 0 1 0 1 0 1
State: ST1 ST1 ST2 ST3 ST1 ST2 ST3 ST1 ST2
Z: 0 0 0 1 0 1 1 0

8-3.
0XX

PS IN NS Z PS IN NS Z PS IN NS Z
ST1/0
A B C A B C A B C
1XX
ST1 0 0 0 ST1 0 ST2 0 0 0 ST3 0 ST3 0 0 0 ST1 1
ST1 0 0 1 ST1 0 ST2 0 0 1 ST3 0 ST3 0 0 1 ST1 1
XXX X10/1 ST1 0 1 0 ST1 0 ST2 0 1 0 ST1 1 ST3 0 1 0 ST1 1
ST1 0 1 1 ST1 0 ST2 0 1 1 ST3 1 ST3 0 1 1 ST1 1
ST1 1 0 0 ST2 0 ST2 1 0 0 ST3 0 ST3 1 0 0 ST1 1
ST3/1 ST2 ST1 1 0 1 ST2 0 ST2 1 0 1 ST3 0 ST3 1 0 1 ST1 1
X0X/0 ST1 1 1 0 ST2 0 ST2 1 1 0 ST1 1 ST3 1 1 0 ST1 1
X11/1 ST1 1 1 1 ST2 0 ST2 1 1 1 ST3 1 ST3 1 1 1 ST1 1

16
 Problem Solutions – Chapter 8

8-4.
A

0 1
X
B
Z

0 1
Y

8-5.*
STA
Reset

0 1
X

STB STD

0 1
X X
1 0
STC STE
Z Z

0 1 0 1
X X

17
 Problem Solutions – Chapter 8

8-6.+
a) Regions marked A, B, and C are defined in part b. b) Insert the following in the ASM chart in the A and C regions, respectively:

IDLE RINSE1 1
A 1IDLE
COLD

A 1 0
0 0 Pause Start
Start Full
0 1
WASH1 1 1
1
Stop Goto Label ‘B’
Load
HOT 0
RINSE2
A DEC
0 TURN
Full
1 A
0
Load Zero
C
WASH2 SPIN3 1
DEC 1
B Go to State “IDLE” Stop
TURN DRAIN
0
A A
0 0
Zero Empty

SPIN1 1 1
C
Load
DRAIN
SPIN4
A DEC
0 TURN
Empty DRAIN
1 A
0 1
Load Zero

SPIN2
DEC
TURN
DRAIN
A
0 1
Zero

8-7.

S0 S1 S2 S3

GN YN RN RN
RE RE GE YE

0 1 1 0 0 1 1 0
T T T T

8-8.*
ST1(t + 1) = ST1⋅A + ST2⋅B⋅C + ST3, ST2(t + 1) = ST1⋅A, ST3(t + 1)= ST2⋅(B + C), Z = ST2⋅B + ST3
For the D flip-flops, DSTi = STi(t + 1) and STi = QSTi. Reset initializes the flip-flops: ST1 = 1, ST2 = ST3 = 0.

18
 Problem Solutions – Chapter 8

8-9.*
Y0 DECODER ST1 A
State Assignment DY0 D
0 DY0
Y1 Y0 C 0 ST2
2 1
R ST3
ST1 0 0 21 2 B
DY1
ST2 0 1 C
Y1
ST3 1 0 DY1 D
C
R Z
Reset

8-10.+

CLK
RESET
IDLE
Start S
D

HOT COLD
WASH1 RINSE1
Full D Full D

CR C R

WASH2
RINSE2
Zero D Zero D

CR C R

SPIN1
SPIN3
Empty D Empty D

CR C R

SPIN2
SPIN4
Zero D Zero D

C R CR

DEC = TURN DRAIN LOAD

19
 Problem Solutions – Chapter 8

8-11.*
100110 (38) 100110
× 110101 (× 53) 110101
100110 000000 Init PP
000000 100110 Add
100110 100110 After Add
000000 0100110 After Shift
100110 00100110 After Shift
100110 100110 Add
11111011110 (2014) 10111110 After Add
010111110 After Shift
0010111110 After Shift
100110 Add
1100011110 After Add
01100011110 After Shift
100110 Add
11111011110 After Add
011111011110 After Shift

8-12.
STATE P B C A Q
IDLE X 1010 X X 1011
MUL0 011 1010 0 1010 1011
MUL1 011 1010 0 0101 0101
MUL0 010 1010 0 1111 0101
MUL1 010 1010 0 0111 1010
MUL0 001 1010 0 0111 1010
MUL1 001 1010 0 0011 1101
MUL0 000 1010 0 1101 1101
MUL1 000 1010 0 0110 1110
IDLE 111 1010 0 0110 1110

8-13.
Time = 2(n+1)f

8-14.
Max Value 2n bits = 22n – 1
Max Multiplicand = Max Multiplier = 2n – 1
(2n – 1) × (2n – 1) = 22n – 2(n + 1) + 1 ≤ 22n – 1? Yes, since 2(n + 1) ≥ 2 for n > 0

8-15.
(a) The maximum product size is 32 bits. The product is available in registers A and Q.
(b) The counter P is 4 bits wide. The initial value loaded is (1111)2.
(c) Z is generated by a 4-bit NOR gate driven by the P counter.

20
 Problem Solutions – Chapter 8

8-16.*
IN
A(14:0)||0 B(14:0)||0
CLK CLK
S 1 MUX 0
LA L AR LB L BR
CLK
Bit 15 B(15:0) LC L
A(15:0) CR
R
Zero
R is a synchronous reset that overides any
simultaneous synchronous transfer.

A
Reset

0 1
G LA
B
LB
C
LC

G
D D D LC
C C C
R R R
LA LB

Reset

8-17.+
n –1 IN
n
Multiplicand

Counter P Register B

log 2 n n

Zero detect SUB

Parallel
G (Go) Adder-Subtractor
Cout

Z n
n
Control Q0 Multiplier
Unit 0
Q-1 C Shift Register A Shift Register Q FF Q-1

5 n
Product














Control signals OUT

21
 Problem Solutions – Chapter 8

IDLE

0 1
G

C ← 0, A ← 0
P←n–1

MUL0

0 1
Q
0

1 Q 0 1 0
–1 Q–1

A ← A + B, A ← A – B,
C ← C out C ← C out

MUL1
C ← 0, C || A || Q ← sr C || A || Q,
P←P–1

0 1
Z

8-18.+
Start = 0 Z=1 Z=0 A: Initial State
B: BR <- Input A, AR <- Input B, PR <- 0
A B C C: PR <- BR + PR, AR <- AR – 1
Start = 1
BR LD n
n LD
AR
n DEC
ADD
2n 2n Zero Z
CLR
PR
LD

Start LD_BR = LD_AR = CLR_PR LD_PR = DEC_AR

Z
A B
D D C
D
C C
S R
C
CLK R

RESET

22
 Problem Solutions – Chapter 8

8-19.*
library IEEE;
use IEEE.std_logic_1164.all;
entity asm_819 is
port (
A, B, C, CLK, RESET: in STD_LOGIC;
Z: out STD_LOGIC
);
end asm_819;
architecture asm_819_arch of asm_819 is
type state_type is (ST1, ST2, ST3);
signal state, next_state : state_type;
begin
state_register: process (CLK, RESET)
begin
if RESET='1' then--asynchronous RESET active High
state <= ST1;
elsif (CLK'event and CLK='1') then --CLK rising edge
state <= next_state;
end if;
end process;
next_state_func: process (A, B, C, state)
begin
case (state) is
when ST1 =>
if A = '0' then
next_state <= ST1;
else
next_state <= ST2;
end if;
when ST2 =>
if ((B = '1') and (C = '0')) then
next_state <= ST1;
else
next_state <= ST3;
end if;
when ST3 =>
next_state <= ST1;
end case;
end process;
output_func: process (B, state)
begin
case (state) is
when ST1 =>
Z <= '0';
when ST2 =>
if (B = '1') then
Z <= '1';
else
Z <= '0';
end if;
when ST3 =>
Z <= '1';
end case;
end process;
end asm_819_arch;

clk
reset
a
b
c
state st1 st2 st3 st1 st2 st1 st2 st3 st1
z

0 50 100 150

23
 Problem Solutions – Chapter 8

8-20.*
module asm_820 (CLK, RESET, A, B, C, Z) ;
input CLK, RESET, A, B, C ;
output Z ;
reg [1:0] state, next_state;
parameter ST1=2'b00, ST2=2'b01, ST3=2'b10;
reg Z;
//State register
always @(posedge CLK or posedge RESET)
begin
if (RESET) //asynchronous RESET active High
state <= ST1;
else //use CLK rising edge
state <= next_state;
end
//Next state function
always @(A or B or C or state)
begin
case (state)
ST1: next_state <= A ? ST2: ST1;
ST2: next_state <= (B && ! C) ? ST1: ST3;
ST3: next_state <= ST1;
default: next_state <= ST1;
endcase
end
//Output function
always @(B or state)
begin
case (state)
ST1: Z <= 1'b0;
ST2: Z <= B ? 1'b1: 1'b0;
ST3: Z <= 1'b1;
default: Z <= 0'b0;
endcase
end
endmodule

CLK
RESET
A
B
C
Z
state 00 01 10 00 01 00 01 10 00

0 50 100 150

8-21.
module asm_821 (X, CLK, RESET, Z) ; //Next state function
input X ; always@(X or state)
input CLK ; begin
input RESET ; case (state)
output Z ; S0: if (X) next_state <= S3;
else next_state <= S1;
reg [2:0] state, next_state; S1: if (X) next_state <= S2;
parameter S0= 3'b000, S1 = 3'b001, S2 = 3'b010, else next_state <= S1;
S3 = 3'b011, S4 = 3'b100; S2: if (X) next_state <= S3;
reg Z; else next_state <= S4;
//State register S3: if (X) next_state <= S3;
always@(posedge CLK or posedge RESET) else next_state <= S4;
begin S4: if (X) next_state <= S2;
if (RESET == 1) else next_state <= S1;
state <= S0; default: next_state <= S0;
else endcase
state <= next_state; end
end

24
 Problem Solutions – Chapter 8

//Output function S4: Z <= 1'b1;

always@(state) default: Z <= 1'b0;
begin endcase
case (state) end
S2: Z <= 1'b1; endmodule

CLK
RESET
X
state 000 001 010 011 100 001 010 100 010
Z

0 ps 50 ns 100 ns 150 ns 200 ns

8-22.+
library IEEE; next_state <= S1;
use IEEE.std_logic_1164.all; else
next_state <= S2;
entity asm_822 is
port (T: in STD_LOGIC; end if;
CLK: in STD_LOGIC; when S2 =>
RESET: in STD_LOGIC; if T = '1' then
GN: out STD_LOGIC; next_state <= S3;
RN: out STD_LOGIC; else
YN: out STD_LOGIC; next_state <= S2;
GE: out STD_LOGIC; end if;
RE: out STD_LOGIC; when S3 =>
YE: out STD_LOGIC); if T = '1' then
end asm_822; next_state <= S3;
else
architecture asm_822_arch of asm_822 is next_state <= S0;
type state_type is (S0, S1, S2, S3); end if;
signal state, next_state: state_type; when others => null;
begin end case;
state_register: process (CLK, RESET) end process;
begin
if (RESET = '1') then output_func: process (state)
state <= S0; begin
elsif (CLK'event and CLK = '1') then GN <= '0'; RN <= '0'; YN <= '0';
state <= next_state; GE <= '0'; RE <= '0'; YE <= '0';
end if; case state is
end process; when S0 =>
GN <= '1'; RE <= '1';
next_state_func: process (T, state) when S1 =>
begin YN <= '1'; RE <= '1';
case state is when S2 =>
when S0 => RN <= '1'; GE <= '1';
if T = '1' then when S3 =>
next_state <= S1; RN <= '1'; YE <= '1';
else when others => null;
next_state <= S0; end case;
end if; end process;
when S1 =>
if T = '1' then end asm_822_arch;

25
 Problem Solutions – Chapter 8

t
clk
reset
state s0 s1 s2 s3 s0 s1
gn
rn
yn
ge
re
ye

0 10 sec 20 sec 30 sec

8-23.+
module asm_823 (CLK, T, RESET, GN, YN, RN, GE, YE, RE) ; S3: if (T)
next_state <= S3;
input CLK, T, RESET; else
output GN,YN, RN, GE, YE, RE; next_state <= S0;
default: next_state <= S0;
reg [1:0] state, next_state; endcase
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; end
reg GN, YN, RN, GE, YE, RE;
//Output function
//State register always@(state)
always@(posedge CLK or posedge RESET) begin
begin GN <= 1'b0; RN <= 1'b0; YN <= 1'b0;
if (RESET == 1'b1) GE <= 1'b0; RE <= 1'b0; YE <= 1'b0;
state <= S0; case (state)
else S0: begin
state <= next_state; GN <= 1'b1; RE <= 1'b1;
end end
S1: begin
//Next state function YN <= 1'b1; RE <= 1'b1;
always@(T or state) end
begin S2: begin
case (state) RN <= 1'b1; GE <= 1'b1;
S0: if (T) end
next_state <= S1; S3: begin
else RN <= 1'b1; YE <= 1'b1;
next_state <= S0; end
S1: if (T) default begin
next_state <= S1; GN <= 1'b0; RN <= 1'b1; YN <= 1'b0;
else GE <= 1'b0; RE <= 1'b0; YE <= 1'b1;
next_state <= S2; end
S2: if (T) endcase
next_state <= S3; end
else endmodule
next_state <= S2;

CLK
RESET
T
state 00 01 10 11 00 01
GN
YN
RN
GE
YE
RE

0 us 10 sec 20 sec 30 sec

26