Institute of Technology Department of Electrical

of Cambodia and Energy Engineering

Lab Experiment 1
Concurrent Circuit Basics

LECTURED BY:
TEP SOVICHEA (COURSE)
LIM PHING (TP)

EXPERIMENT AND RESEARCH BY:

KOY DANIEL (e20200834)

ENGINEERING’S DEGREE
DEPARTMENT OF ELECTRICAL AND ENERGY ENGINEERING
INSTITUTE
OF TECHNOLOGY OF CAMBODIA
PHNOM PENH

Academy Year
2023-2024
Contents

CONTENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i

1 CONCURRENT CIRCUIT BASICS 1

1 OBJECTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 EQUIPMENT AND REQUIREMENT . . . . . . . . . . . . . . . . . . . . . . . 1
3 THEORETICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3.1 Introduction to Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . 1
3.2 Introduction to Address Decoder . . . . . . . . . . . . . . . . . . . . . . 15
4 CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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Chapter 1

CONCURRENT CIRCUIT BASICS

1. OBJECTIVE

• Get familiar with VHDL code structure and syntax

• Get familiar with RTL view and simulation flow in Quartus Prime

• Build basic concurrent circuit using VHDL

• Test the circuit using Cyclone V development board

2. EQUIPMENT AND REQUIREMENT

3. THEORETICAL

3.1. Introduction to Multiplexer

The Multiplexer (MUX) is a combinational circuit that selects binary information from one of
many input lines and directs it to output line or it is simply called a ”DATA SELECTOR”.

Figure 1: Schematic of a n multiplexer. It can be equated to a controlled switch.

The relation between the selector variable and input

n = 2m
m = log2 n
where: n : the number of the input line; m : the number of the select line

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■ TYPE
There are five multiplexer such as:

a) 2 : 1 MUX with 1 selector b) 4 : 1 MUX with 2 selector

c) 8 : 1 MUX with 3 selector d) 16 : 1 MUX with 4 selector
e) 32 : 1 MUX with 5 selector

■ Example: 2-to-1 multiplexer

The code below show two methods to build a 2-to-1 multiplexer with 4-bit data width.
Listing 1 uses, with-select statement, which makes the code easier to read. However, as
you can see, it is not flexible when you want to make the multiplexer with different size.
This is because you have to modify the code to add or remove the number of inputs.
Listing 2, on the other hand, utilize generic vector assignment; thus allowing a variable
size multiplexer upon changing the number of inputs and data width.

– Listing 1. 2-to-1 multiplexer using with-select statement

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux_2 is
port(
x0 : in std_logic_vector(3 downto 0);
x1 : in std_logic_vector(3 downto 0);
sel : in std_logic;
y : out std_logic_vector(3 downto 0)
);
end entity;

architecture comb of mux_2 is

begin
with sel select
y <= x0 when "0";
x1 when others;
end architecture;

– Listing 2. 2-to-1 multiplexer using generic vector assignment

library IEEE;
use IEEE.STD_LOGIC_1164.all;

2
 entity mux_2 is
port(
x : in std_logic_vector(7 downto 0);
sel : in std_logic;
y : out std_logic_vector(3 downto 0)
);
end entity;

architecture comb of mux_2 is

signal sel_int : natural range 0 to 1;
begin
sel_int <= to_interger(unsigned(sel));
y <= x((sel_int + 1) * 4 - 1 downto sel_int *4);
end architecture;

■ Exercise A

Figure 2: Multiplexer with 4 inputs Figure 3: Multiplexer with n inputs

a). Following the example, write a VHDL code to build the multiplexer in shown Fig-
ure 1.
b). Define the multiplexer with a 4 inputs and the data width of 8 bits. Provide the
RTL view of your code, as well as the the simulation output for all 4 cases.
c). Test your circuit with the development board.

Solution A:
a). Following the example, write a VHDL code to build the multiplexer in shown Figure 1.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

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• Before we start to write the VHDL code we must include the library Library IEEE;
it contains one of the most basic package,useIEEE.STD LOGIC 1164.all.
• The package useIEEE.STD LOGIC 1164.all It contains the types STD LOGIC (similar
to bit) and definition of data types which are used for modeling wires at the time of
synthesis..

entity exerciseA is
port(
x0 : in std_logic_vector(7 downto 0);
x1 : in std_logic_vector(7 downto 0);
x2 : in std_logic_vector(7 downto 0);
x3 : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(1 downto 0);
Y: out std_logic_vector(7 downto 0)
);
end entity;

• The syntax above shows the main parts of an entity declaration (or entity, for short),
which is the port clauses (together, they form the entity header ).
• Remember that the entity name should be also the project name (exerciseA), so
that is another reason for choosing that name carefully.
• Now in this region in the syntax above is the port list, which is just a list with
specifications of all circuit inputs and outputs. From the code above x0, x1, x2,
x3: in std logic; and sel : in std logic vector(1 downto 0); are inputs
entity declaration. The Y: out std logic; is an output entity declaration.

architecture mux_4_1 of exerciseA is

begin
process(x0, x1, x2, x3, sel)
begin
case sel is
when "00" => Y <= x0;
when "01" => Y <= x1;
when "10" => Y <= x2;
when "11" => Y <= x3;
end case;
end process;
end architecture;

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• The last section is the architecture body (or architecture, for short) contains the
VHDL code proper, which describes the circuit behavior or structure, from which
a compliant hardware can then be inferred by the compiler. It can also contain
instances of previous designs. It is composed of two parts, the first being a declarative
region and the second a statement region above.
• Architecture Declaration:

architecture mux_4_1 of exerciseA is

This line declares the architecture named mux 4 1 for the entity exerciseA
• Signal Assignment:

begin

This begins the architecture declaration section.

• Process Statement:

process(x0, x1, x2, x3, sel)

This declares a process with sensitivity to changes in signals x0, x1, x2, x3, sel.
The process will execute whenever any of these signals change.
• Case Statement:

begin
case sel is
when "00" => Y <= x0;
when "01" => Y <= x1;
when "10" => Y <= x2;
when "11" => Y <= x3;
end case;

Within the process, there’s a case statement that evaluates the value of signal sel.
Depending on its value, the output Y is assigned one of the four input signals (x0,
x1, x2, x3).
• End Process:

end process;

This ends the process declaration.

• End Architecture:

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 end architecture;

This ends the architecture declaration.

• For example, if sel is "00", Y will be assigned the value of x0. If sel is "01", Y will
be assigned the value of x1, and so on.

b). Define the multiplexer with a 4 inputs and the data width of 8 bits. Provide the RTL
view of your code, as well as the the simulation output for all 4 cases.

• Library and Use Clauses:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

These lines include the necessary libraries and packages required for working with
standard logic types and operations in VHDL.
• Entity Declaration:

entity exerciseA is
port(
x0 : in std_logic_vector(7 downto 0);
x1 : in std_logic_vector(7 downto 0);
x2 : in std_logic_vector(7 downto 0);
x3 : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(1 downto 0);
Y: out std_logic_vector(7 downto 0)
);
end entity;

This declares the entity exerciseA with five ports:

– x0, x1, x2, x3: 8-bit input vectors representing the four data inputs.
– sel: 2-bit input vector representing the selection input.
– Y: 8-bit output vector representing the output of the multiplexer.
• Architecture Declaration:

architecture mux_4_1 of exerciseA is

This line declares the architecture mux 4 1 for the entity exerciseA.
• Signal Assignment:

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 begin

This begins the architecture declaration section.

• Process Statement:

process(x0, x1, x2, x3, sel)

This declares a process with sensitivity to changes in signals x0, x1, x2, x3, and
sel. The process will execute whenever any of these signals change.
• Case Statement:

begin
case sel is
when "00" => Y <= x0;
when "01" => Y <= x1;
when "10" => Y <= x2;
when "11" => Y <= x3;
end case;

Inside the process, a case statement is used to select the appropriate input signal
(x0, x1, x2, or x3) based on the value of sel.
• End Process:

end process;

This ends the process declaration.

• End Architecture:

end architecture;

This ends the architecture declaration.

• For example, if sel is "00", Y will be assigned the value of x0. If sel is "01", Y will
be assigned the value of x1, and so on.

■ Provide the RTL view of your code

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 Figure 4: RTL of the code exercise A

• The simulation output for all 4 cases.

Figure 5: Waveform of multiplexer 4 to 1

From the waveform above we can discuss that the 4 to 1 multiplexer where there are 4
inputs with 2 selectors and 1 output Y. From the multiplexer truth table we can see that
when selectors sel 0 and sel 1 equal 00 the Y choose x0 that’s why the result show that the
output Y is 00000000, when the sel 0 and sel 1 equal 01 the Y choose x1 and the result
we received from the output is 00000001 and the process repeated over again and again
until the selector reach 11

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c). Test your circuit with the development board.
Before we get started with simulation circuit with the FPGA board we must have the
ALTERA CYCLONE IV EP4CE22F17C6N board and jumper (male to female).

Before we upload the code we must assign the pin to know which we need to assign we
carefully read the user manual. Once we finished assign the pins of the board save the
project than run the hardware.

To run the hardware we connect the board to the computer. Go to −→ Program Device
(Open Programmer) than −→ Hardware Setup to select the board once we finished
select Start.

■ The result from the simulation

(a) When sel = 00 so x0 = 11000000

From the Figure 6 we see that when we click the the button to 00 we see that the
output led are high 2 led and the rest are low.

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 Figure 6: When sel = 00 and x0 = 11000000

(b) When sel = 01 so x1 = 00010000

From the Figure 7 we see that when we click the the button to 01 we see that the
output led is high 1 led and the rest are low.

Figure 7: When sel = 01 and x1 = 00010000

(c) When sel = 10 so x1 = 00111110

From the Figure 8 we see that when we click the the button to 10 we see that the
output led are high 5 led and the rest are low.

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 Figure 8: When sel = 10 and x1 = 00111110

(d) When sel = 10 so x1 = 11111111

From the Figure 9 we see that when we click the the button to 10 we see that the
output led are high 5 led and the rest are low.

Figure 9: When sel = 11 and x1 = 11111111

■ Exercise B
In this exercise, you will create a generic multiplexer by providing variables NUM INPUTS
and NUM BITS as generic constants, where NUM BITS is the data width for each input and
output. Test your circuit by using NUM INPUTS = 7 and NUM BITS = 8.

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Solution B:
Create a generic multiplexer by providing variables NUM INPUTS and NUM BITS
Given: NUM INPUTS = 7 and NUM BITS = 8

• Library and Use Clauses:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;

These lines import standard libraries required for logic operations (STD LOGIC 1164),
numeric operations (NUMERIC STD), and real number math operations (MATH REAL). The
commented lines are alternative libraries that are not used in this code.

• Entity Declaration:

entity exerciseB is
generic(
NUM_INPUTS: integer := 7; -- number of inputs
NUM_BITS: integer := 8 -- Data width for each input and output
);
port(Architecture:
inputs: in std_logic_vector(NUM_BITS-1 downto 0); -- A is input
output: out std_logic_vector(NUM_BITS-1 downto 0); -- B is output
sel: in std_logic_vector(integer(ceil(log2(real(NUM_INPUTS))))-1
downto 0)
-- Note: "ceil()" rounds up the result to the nearest integer.
-- "log2()" returns the base-2 logarithm of a real number.
);
end entity exerciseB;

This entity declaration defines a component with two generics (NUM INPUTS and NUM BITS)
and three ports (inputs, output, and sel). inputs and output are arrays of std logic vector,
and sel is an array of std logic vector with a width determined by the number of bits
needed to represent NUM INPUTS.

• Architecture:

architecture exB of exerciseB is

This line declares the architecture exB for the entity exerciseB

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• Process Statement:

process(inputs,sel)
begin
-- Process body

This process statement specifies that the process sensitivity list includes the signals
inputs and sel. This means that the process will be executed whenever there is a
change in the values of inputs or sel.

• Case Statement:

begin
process(inputs, sel)
begin
if (to_integer(unsigned(sel)) >= 0 and to_integer(unsigned(sel))
<= NUM_INPUTS - 1) then
output <= inputs((to_integer(unsigned(sel)) * NUM_BITS)
+ NUM_BITS - 1 downto (to_integer(unsigned(sel)) * NUM_BITS));
else
output <= (others => '0');
end if;
end process;

• The architecture exB defines a process sensitive to changes in inputs and sel.

• Inside the process, there’s an if statement to select the appropriate slice of inputs based
on sel.

• If sel is within the valid range (0 to NUM INPUTS - 1), it selects the corresponding slice
from inputs.

• If sel is outside the valid range, it assigns all ′ 0′ s to the output.

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 • Provide the RTL view of your code

Figure 10: RTL of the code exercise B

• The simulation output for all 4 cases.

Figure 11: Waveform of multiplexer 7 to 3 with generic cases

From the waveform above we see that in the row that said ”/exerciseb/inputs” has the
inputs bit of 56 this because we multiply the NUM INPUTS with NUM BITS. In the inputs we set

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”11100000” as a first 8-bit with the selector of ”000” we see the output given that it is the same
as first 8-bit inputs. and it is happen the same with other cases except when the selector is
”111” the output given is ”0000000” this because the selector actually is 2 inputs but we assume
it is 3 because from the calculation on the selector it is float (2.8). From the code above in the
architecture section we set else when output <= (others => ’0’); this mean when the the
selestor is not match the output will select ”0” that is why the output given ”00000000”.

3.2. Introduction to Address Decoder

Address decoder is on of the most common decoders which has ability to employed in memory
chips to activate the word line corresponding to the received address vector. The inputs are
the address vectors (a) plus an enable signal (ena) The circuit described produces an output
signal (denoted as b) that activates one of the memory lines at a time. This signal ensures that
only one bit in the output differs from all the others, representing a binary-to-one-hot code
converter. This can be understood clearly from the truth table provided. The only instance
where there’s an exception is when the enable signal (ena) is 0, indicating that none of the
memory words should be selected. If the input signal a has N bits, then the output signal b
will have 2N bits.

■ Exercise C

Figure 12: Address Decoder

ena a(2 : 0) b(7 : 0) a(2 : 0) b(7 : 0)

0 xxx 00000000
1 000 00000001 100 00010000
1 001 00000010 101 00100000
1 010 00000100 110 01000000
1 011 00001000 111 10000000

Address decoders were reviewed in section 1.4.2 of text book.

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 1. Why are they said to be combinational?
2. Write a VHDL code that implements the circuit of figure 6. Enter the number of
bits at the point (call it NUM BITS) as a generic parameter. (Hint: Section 7.10.3.)
3. Show simulation results, for NUM BITS = 3.

Solution C:

1. Why are they said to be combinational?

An address decoder is often described as a combinational circuit because its output de-
pends solely on the current input address lines and not on any past history or internal
state. Here’s why an address decoder is considered to be combinational:

• Input-Output Relationship: The output of an address decoder is determined

solely by the input address lines. Each combination of input address lines corre-
sponds to a unique output line. There is no internal memory or feedback involved
in generating the output.
• No Sequential Logic: Unlike sequential circuits, which have memory elements like
flip-flops or latches, an address decoder does not store any past information about
the inputs. The output is computed directly from the current state of the input
address lines.
• Truth Table Representation: An address decoder’s behavior can be described
using a truth table, where each row represents a unique combination of input address
lines and the corresponding output line(s). This aligns with the definition of a
combinational circuit, where the output is solely determined by the current input
values.
• Instantaneous Output: The output of an address decoder is available immediately
after the input address lines stabilize. There are no clock signals or sequencing
involved in producing the output.

2. Write a VHDL code that implements the circuit of figure 6. Enter the number of bits at
the point (call it NUM BITS) as a generic parameter. (Hint: Section 7.10.3.)

• Library and Use Clauses:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

These lines import necessary libraries for standard logic operations.

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• Entity Declaration:
– The entity exerciseC is declared with one generic parameter NUM BITS, which
specifies the number of input bits.
– It has two ports: address as input, which is a vector of NUM BITS bits, and
enable as output, which is a vector of size 2**NUM BITS - 1.

entity exerciseC is
generic (
NUM_BITS : integer := 3
);
Port (
address : in std_logic_vector(NUM_BITS - 1 downto 0);
enable : out std_logic_vector(2**NUM_BITS - 1 downto 0)
);
end exerciseC;

• Architecture Declaration:

architecture exC of exerciseC is

This declares the architecture named exC for the entity exerciseC.
• Process Statement:

begin
process(address)
begin
-- Process body goes here
end process;
end exC;

– A process statement is used to define the behavior of the circuit.

– The sensitivity list contains only address, meaning the process will execute
whenever the address input changes.
• Conditional Statements:
– These conditional statements decode the input address and set the enable
signal accordingly.
– f the address matches any of the specified patterns, the corresponding enable
signal is set to ’1’.
– If none of the patterns match (the else case), all enable signals are set to ’0’.

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 if address = "000" then
enable <= "00000001";
elsif address = "001" then
enable <= "00000010";
elsif address = "010" then
enable <= "00000100";
elsif address = "011" then
enable <= "00001000";
elsif address = "100" then
enable <= "00010000";
elsif address = "101" then
enable <= "00100000";
elsif address = "110" then
enable <= "01000000";
elsif address = "111" then
enable <= "10000000";
else
enable <= (others => '0');
end if;

• End:

end process;

This ends the process statement and architecture declaration.

• Provide the RTL view of your code

Figure 13: RTL of the code exercise C

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 3. Show simulation results, for NUM BITS = 3.

Figure 14: Waveform of address decoder with generic cases

From the waveform (Figure 14) at the address row there are three input bits and the
enable row there are eight output bits. In this condition we set the address input bit
based on the given truth table above (Figure 12). As the result, we see that when we
set the address inputs equal ”000” we got the output that equal to ”10000000” and so
no. If we compare the result from the output waveform to the truth table we see that the
result are the same to the truth table.

4. CONCLUSION

In summary, multiplexers are like versatile switches that help connect many input signals to
one output. They’re handy when you need to choose which signal goes through based on
certain conditions. For example, in a TV remote, you have many buttons, but only one button
press gets sent to the TV. On the other hand, address decoders are like translators that help
a computer know which memory or device to talk to. Imagine a big library with many books.
The address decoder helps the computer find the right shelf where a particular book is kept.
It’s like having a map that guides you to the correct section of the library.

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