Institute of Technology Department of Electrical

of Cambodia And Energy Engineering

Lab Experiment 1
Concurrent Circuit Basics
LECTURED BY :

TEP SOVICHEA (COURSE)

LIM PHING (TP)

EXPERIMENT AND RESEARCH BY :

KEANG SAKDA (e20200856)

ENGINEERING’S DEGREE
DEPARTMENT OF ELECTRICAL AND ENERGY ENGINEERING
INSTITUS
OF TECHNOLOGY OF CAMBODIA

Academy Year
2023-2024

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Contents

CONTENTS……………………………………………..i
1. CONCURRENT CIRCUIT BASICS
1. OBJECTIVES……………………………………………………………….1
2. EQUIPMENT AND REQUIREMENTS………………………………..2
3. THEORETICAL…………………………………………………………….3

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CONCURRENT CIRCUIT BASICS

1. OBJECTIVE
• Get familiar with VHDL code structure and syntax
• Get familiar with RTL view and simulation flow in Quartus Prime
• Build basic concurrent circuit using VHDL
• Test the circuit using Cyclone 5 development board
2. EQUIPMENT AND REQUIREMENTS
3. THEORETICAL
3.1. Introduction to multiplexer

A multiplexer operates by using control signals to determine which input

signal to pass through to the output. It essentially combines multiple inputs
into one output, allowing for efficient data transmission and signal routing in
digital systems.

Figure 1 : Schematic of a multiplexer 2 input

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Exercise A

Figure 2 : Multiplexer with 4 inputs Figure 3 : Multiplexer with n inputs

Solution A :
a. Write VHDL code to build the multiplexer

• To write VHDL code, we need a library like the one above In addition, we also need a
package like use IEEE.STD_LOGIC_1164.all;

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 • entity mux4 is: This declares the entity named “mux4”. An entity in VHDL is like a
blueprint or interface for a digital component. It defines the inputs, outputs, and behavior
of the component.

• port (...): This section declares the ports of the entity. Ports define the interface of the
entity. In this case, the entity has six ports:

• (x0, x1, x2, x3): These are input ports of type “std_logic_vector” with a range of 7 downto
0. Each port represents an 8-bit vector.
• “Y”: This is an output port of type “std_logic_vector” with a range of 7 downto 0. It
represents the output of the multiplexer.
• “sel”: This is an input port of type “std_logic_vector” with a range of 1 downto 0. It
represents the selection input used to choose which input (x0, x1, x2, or x3) is routed to
the output “Y”.

• The entity “mux4” thus represents a 4-to-1 multiplexer with four 8-bit input vectors (x0,
x1, x2, x3), one 8-bit output vector (Y), and a 2-bit selection input (sel). Depending on the
value of “sel”, one of the input vectors is selected and routed to the output “Y”.

• “sel” is the selection signal, which is a 2-bit input.

• There are four data inputs: x0, x1, x2, and x3.
• The output y selects one of the four inputs based on the value of sel.
➢ The syntax with sel select is a VHDL construct that allows you to select different outputs
based on the value of sel. In this case:

• When “sel” is "00", the output y is assigned the value of x0.

• When “sel” is "01", the output y is assigned the value of x1.
• When “sel” is "10", the output y is assigned the value of x2.
• When “sel” is any other value (including "11"), the output y is assigned the value of x3.
➢ So, essentially, the multiplexer selects one of the four input signals (x0, x1, x2, or x3)
based on the value of the selection signal sel.
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C). Test your circuit with the development board.

• Before we get started with simulation circuit with the FPGA board we must have the ALTERA
CYCLONE IV EP4CE22F17C6N board and jumper (male to female)

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Exercise B

In this exercise, you will create a generic multiplexer by providing variables NUM_INPUTS
and NUM_BITS as generic constants, where NUM_BITS is the data width for each input and
output. Test your circuit by using NUM_INPUTS = 7 and NUM_BITS = 8

Sloution B

• Library

❖ In this VHDL code snippet, several IEEE libraries are being imported:

• IEEE.STD_LOGIC_1164: This library defines the std_logic type and provides functions
and operators for working with it.
• ieee.numeric_std: This library provides numeric types like unsigned and signed, as well
as arithmetic and comparison functions for these types.
• ieee.math_real: This library provides mathematical functions for real numbers, such as
sine, cosine, square root, etc.
➢ These libraries are commonly used in VHDL design to work with standard logic signals,
perform arithmetic operations on numeric types, and apply mathematical functions to
real numbers.

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 • Entity

❖ This VHDL entity genMux represents a generic multiplexer (MUX) module with configurable
parameters. Here's a brief explanation of its components:

• generic: This section defines generic parameters that can be configured when instantiating the
entity. In this case, there are two generic parameters:

• NUM_INPUTS: Specifies the number of input ports for the multiplexer. It has a default value of 7.
• NUM_BITS: Specifies the number of bits for each input port. It has a default value of 3.
• port: This section defines the input and output ports of the entity:

• input: An input port representing the data inputs to the multiplexer. It is a std_logic_vector with a
width calculated based on the product of NUM_INPUTS and NUM_BITS.
• sel: An input port representing the selection lines for choosing among the inputs. It is a
std_logic_vector whose width is determined by the number of selection lines required to address all
inputs, calculated as the ceiling of the logarithm base 2 of NUM_INPUTS.
• output: An output port representing the output of the multiplexer. It is a std_logic_vector with a
width equal to NUM_BITS.
➢ Overall, this entity defines a configurable multiplexer capable of handling a variable number of
inputs and selecting among them using a set of selection lines.

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 • Architecture

❖ This VHDL architecture RTL implements the functionality of the genMux entity. Here's a brief
explanation of the architecture:
• signal int_sel: This line declares an intermediate signal named int_sel. It converts the sel input
(which is a std_logic_vector) to an integer using the unsigned conversion function. This integer
represents the selected input index.
• begin: This marks the beginning of the architecture body.
• output <= input(((int_sel+1)*NUM_BITS)-1 downto int_sel*NUM_BITS): This line assigns a portion
of the input signal to the output signal based on the selected input index (int_sel). It calculates the
range of bits to be assigned based on the selected input index and the width of each input
(NUM_BITS). It essentially performs the multiplexing operation by selecting the appropriate bits from
the input signal and assigning them to the output signal.
➢ Overall, this architecture implements the multiplexing functionality of the genMux entity, selecting
the input based on the provided selection lines (sel) and outputting the corresponding bits.

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 • Introduction to Address Decoder

An address decoder is a digital circuit that translates memory addresses or

device identifiers into physical locations within a computer system. It
facilitates efficient data transfer by directing signals from the CPU to the
appropriate memory bank or device, ensuring seamless communication
between different components of the system.

• Ex3

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a).An address decoder is termed "combinational" because its output relies
solely on the present input address lines, devoid of any past history or internal
state. It operates through the following key points:

• Input-Output Relationship : Output is determined directly by the input

address lines, with each combination of inputs mapping to a unique
output without any internal memory or feedback.

• Absence of Sequential Logic : Unlike sequential circuits, address

decoders lack memory elements like flip-flops or latches and compute
output directly from the current input state.

• Truth Table Representation : Behavior is defined using a truth table,

aligning with combinational circuits where output depends solely on
current inputs.

• Instantaneous Output : Output is available immediately once input

address lines stabilize, without requiring clock signals or sequencing.

b) code VHDL

❖ Library and Use Clauses :

• These lines import necessary libraries for standard logic operations.

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 ❖ Entity Declaration:

• The entity exerciseC is declared with one generic parameter NUM BITS, which specifies
the number of input bits.
• It has two ports: address as input, which is a vector of NUM BITS bits, and
enable as output, which is a vector of size 2**NUM BITS - 1.

❖ Architecture and process:

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This is a piece of VHDL code that describes a simple register transfer level (RTL) architecture for a
circuit. Let's break down what it does:
1. Signal Declaration:
• int_a is declared as an integer signal and initialized with the value of a converted to
an unsigned integer.
2. Process Statement:
• A process is defined with sensitivity to changes in signals en and a.
• Whenever either en or a changes, the process is triggered to execute.
3. Process Body:
• Inside the process, there's an if-else statement.
• If en is '1' (indicating enable is active), then:
• b is cleared (all bits set to '0').
• The bit at position int_a in b is set to '1'.
• If en is not '1' (indicating enable is not active), then:
• b is cleared (all bits set to '0').
4. End of Process:
• End of the process statement.
5. End of Architecture:
• End of the architecture description.

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CONCLUSION

Multiplexers and address decoders serve distinct functions in electronic systems.

Multiplexers act as versatile switches, enabling the connection of multiple input
signals to a single output, useful for selecting signals based on specific conditions.
In contrast, address decoders function as translators, assisting computers in
identifying the memory or device to communicate with, analogous to a map guiding
one to the correct section of a library containing a particular book.

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