DATA MOVEMENT Lecture 6

INSTRUCTIONS
LECTURE OUTLINE
4-3 LOAD-EFFECTIVE ADDRESS
 4–4 STRING DATA TRANSFERS
 4–5 MISCELLANEOUS DATA TRANSFER INSTRUCTIONS
 4–3 LOAD-EFFECTIVE ADDRESS
LEA
loads a 16- or 32-bit register with the offset address of the data
specified by the operand.
 By comparing LEA with MOV, we observe that LEA BX,[DI] loads the
offset address specified by [DI] (contents of DI) into the BX register; MOV
BX,[DI] loads the data stored at the memory location addressed by [DI] into
register BX.
 Earlier examples presented by using the OFFSET directive.
 OFFSET directive performs the same function as an LEA instruction if the
operand is a displacement.
 For example, the MOV BX,OFFSET LIST performs the same function as LEA
BX,LIST. Both instructions load the offset address of memory location LIST
into the BX register.
 But why is the LEA instruction available if the OFFSET
directive accomplishes the same task?
- First, OFFSET only functions with simple operands such as
LIST. It may not be used for an operand such as [DI], LIST [SI],
and so on.
The OFFSET directive is more efficient than the LEA
instruction for simple operands. It takes the microprocessor
longer to execute the LEA BX,LIST instruction than the MOV
BX,OFFSET LIST.
Microprocessor requires two clocks to execute the LEA
BX,LIST instruction and only one clock to execute MOV
BX,OFFSET LIST. The reason that the MOV BX,OFFSET
LIST instruction executes faster.
- the assembler calculates the offset address of LIST, whereas the
microprocessor calculate the address for the LEA instruction.
LDS, LES, LFS, LGS, AND LSS
 load any 16-bit or 32-bit register with an offset address, and the DS, ES,
FS, GS, or SS segment register with a segment address.
 These instructions use any of the memory-addressing modes to access a
32-bit or 48-bit section of memory that contains both the segment and
offset address.

- The 32-bit section of memory contains a 16- bit offset and segment
address, while the 48-bit section contains a 32-bit offset and a
segment
address.
 Figure 4–17 illustrates an example LDS BX,[DI] instruction. This instruction
transfers the 32-bit number, addressed by DI in the data segment, into the
BX and DS registers.
FIGURE 4–17 THE LDS BX,[DI] INSTRUCTION LOADS REGISTER BX FROM ADDRESSES
11000H AND 11001H AND REGISTER DS FROM LOCATIONS 11002H AND 11003H. THIS
INSTRUCTION IS SHOWN AT THE POINT JUST BEFORE DS CHANGES TO 3000H AND BX
CHANGES TO 127AH.
 This instruction transfers the 32-bit number, addressed by DI in the data
segment, into the BX and DS registers.
 The LDS, LES, LFS, LGS, and LSS instructions obtain a new far address
from memory.
- offset address appears first, followed by the segment address.
TABLE 4–10 LOAD-EFFECTIVE ADDRESS INSTRUCTIONS.
 4–4 STRING DATA TRANSFERS

 Five string data transfer instructions: LODS, STOS, MOVS, INS,

and OUTS.
 Each string instruction allows data transfers that are either a
single byte, word, doubleword, or quadword.
 Before the string instructions are presented, the operation of
the D flag-bit (direction), DI, and SI must be understood as they
apply to the string instructions.
THE DIRECTION FLAG
 The direction flag (D, located in the flag register) selects the auto-
increment (D=0) or the auto-decrement (D=1) operation for the DI and SI
registers during string operations.

- used only with the string

instructions.
The CLD instruction clears the D flag (D=0) and the STD instruction sets it
(D=1).

- CLD instruction selects the auto-increment mode and STD selects the
auto-decrement mode
DI AND SI
 During execution of a string instruction, memory accesses occur
through either or both of the DI and SI registers.

- DI offset address accesses data in the extra segment for all

string instructions that use it.
- SI offset address accesses data, by default, in the data
segment.
 Operating in the 32-bit mode in the 80386 microprocessor or above,
the EDI and ESI registers are used in place of DI and SI.
- This allows string using any memory location in the entire 4G-byte
protected mode address space of the microprocessor.
LODS
 loads AL, AX, EAX, or RAX with data stored at the data segment
offset address indexed by the SI register.
 1 is added to or subtracted from SI for a byte-sized LODS
 2 is added or subtracted for a word-sized LODS
 4 is added or subtracted for a doubleword-sized LODS.
 8 is added or subtracted for a quadword-sized LODS.
 Figure 4–18 shows the effect of executing the LODSW instruction.
FIGURE 4–18 THE OPERATION OF THE LODSW INSTRUCTION IF DS = 1000H, D = 0,
11000H = 32 AND 11001H = A0. THIS INSTRUCTION IS SHOW N AFTER AX IS LOADED
FROM MEMORY, BUT BEFORE SI INCREMENTS BY 2.
TABLE 4–11 FORMS OF THE LODS INSTRUCTION.
STOS
 Stores AL, AX, EAX, or RAX at the extra segment memory location
addressed by the DI register.
 STOSB (stores a byte) instruction stores the byte in AL at the extra
segment memory location addressed by DI.
 STOSW (stores a word) instruction stores AX in the extra segment
memory location addressed by DI.
 STOSD (stores a doubleword) instruction.
 STOSQ (stores a quadword) instruction.
 After the byte (AL), word (AX), doubleword (EAX), or quadword
(RAX) is stored, the contents of DI increment or decrement.
TABLE 4–12 FORMS OF THE STOS INSTRUCTION.
STOS WITH A REP
 The repeat prefix (REP) is added to any string data transfer
instruction, except the LODS instruction.
- REP prefix causes CX to decrement by 1 each time the
string instruction executes; after CX decrements, the string
instruction repeats.
 If CX reaches a value of 0, the instruction terminates and the
program continues with the next sequential instruction.
MOVS
 Transfers a byte, word, doubleword, or quadword from the data
segment location addressed by SI to the extra segment location
addressed by DI.
- pointers then are incremented or decremented, as dictated
by the direction flag.
TABLE 4–14 FORMS OF THE MOVS INSTRUCTION.
TABLE 4–13 COMMON OPERAND MODIFIERS.
INS
 Transfers a byte, word, or doubleword of data from an I/O device
into the extra segment memory location addressed by the DI register.
- I/O address is contained in the DX register
 Useful for inputting a block of data from an external I/O device
directly into the memory.
 One application transfers data from a disk drive to memory.
- Disk drives are often considered and interfaced
as I/O devices in a computer system.
TABLE 4–15 FORMS OF THE INS INSTRUCTION.
OUTS
 Transfers a byte, word, or doubleword of data from the data
segment memory location address by SI to an I/O device.
- I/O device is addressed by the DX register as it is with the
INS instruction.
 In the 64-bit mode for the Pentium 4 and Core2, there is no 64-bit
output
TABLE 4–16 FORMS OF THE OUTS INSTRUCTION.
4–5 MISCELLANEOUS DATA TRANSFER
INSTRUCTIONS

 Used in programs, data transfer instructions detailed in this

section are XCHG, XLAT, IN, OUT, BSWAP, MOVSX, MOVZX, and
CMOV.
 XCHG
 Exchanges the contents of a register with the contents of any other
register or memory location.

- cannot exchange segment registers or memory-to-memory

data.
 Exchanges are byte-, word-, or doubleword-sized and use any
addressing mode except immediate addressing.
 XCHG using the 16-bit AX register with another 16-bit register, is the
most efficient exchange.
 The XCHG AL,[DI] instruction is identical to the XCHG [DI],AL
Instruction.
TABLE 4–17 FORMS OF THE XCHG INSTRUCTION.
 XLAT
 XLAT (translate) instruction converts the contents of the AL register
into a number stored in a memory table.

 An XLAT instruction first adds the contents of AL to BX to form a

memory address within the data segment.
- copies the contents of this address into AL
- only instruction that adds an 8-bit number to a l6-bit number.
FIGURE 4–19 THE OPERATION OF THE XLAT INSTRUCTION AT THE POINT
JUST BEFORE 6DH IS LOADED INTO AL.

- After the translation, AL= 6DH

EXAMPLE 4–11

 Figure 4–19 shows the operation of this example program if TABLE

= 1000H, DS = 1000H, and the initial value of AL = 05H After the
translation, AL = 6DH
IN AND OUT
 IN and OUT instructions, which perform I/O operations.
 Contents of AL, AX, or EAX are transferred only between the I/O
device and the microprocessor.
- An IN instruction transfers data from an external I/O
device into AL, AX, or EAX;
- an OUT transfers data from AL, AX, or EAX to an external
I/O device.
only the 80386 and above contain EAX.
 Two forms of I/O device (port) addressing exist for IN and OUT:
fixed port and variable port.
 Fixed-port addressing allows data transfer between AL, AX, or
EAX using an 8-bit I/O port address.
- port number follows the instruction’s opcode, just as it did with
immediate addressing.
- IN AL,6AH 8 bits data from I/O address 6AH are input to AL.

 Variable-port addressing allows data transfers between AL, AX,

or EAX and a 16-bit port address.
- I/O port number is stored in register DX, which can be changed
(varied) during the execution of a program.
TABLE 4–18 IN AND OUT INSTRUCTIONS.
FIGURE 4–20 THE SIGNALS FOUND IN THE MICROPROCESSOR-BASED
SYSTEM FOR AN OUT 19H,AX INSTRUCTION.