Material On Embedded System 3
Material On Embedded System 3
-- debouncing FSM
-- state register
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FSMD
-- next-state/ out put logic
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1
FSMD
We used an FSM and a timer (which is a regular sequential circuit), it is not
based on the RT methodology because the two units are running independently
and the FSM has no control over the timer. The waiting period in this design is
between 20 and 30 ms but is not an exact interval. This deficiency can be
overcome by applying the RT methodology.
• The circuit include two output signals: db-level, which is the debounced output, and db-tick,
which is a one-clock-cycle enable pulse asserted at the zero-to-one transition.
• The zero and one states mean that the sw input has been stabilized for '0' and 'l' , respectively.
• The wait_l and wait_0 states are used to filter out short glitches.
• The data path contains one register, q, which is 21 bits wide.
• When the sw input signal becomes '1', the FSMD moves to the wait_1 state and initializes q to
"1 . . . ". In the wait_l state, the q decrements in each clock cycle. If sw remains as '1', the
FSMD returns to this state repeatedly until q reaches "0 . . . 0 " and then moves to the one
state.
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FSMD
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FSMD
• Code with explicit data path components
The key data path component custom 21-bit decrement counter that can:
• Be initialized with a specific value
• Count downward or pause
• Assert a status signal when the counter reaches 0
• The complete data path is composed of the q register and the next-state logic of the custom
decrement counter. A comparison circuit is included to generate the q-zero status signal.
• The control path consists of an FSM, which takes the sw input and the q-zero status and
asserts the control signals, q-load and q-dec, according to the desired action in the ASMD
chart.
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3
-- FSMD control path next-state logic
process(state_reg, sw, q_zero)
begin
q_load <= '0'; when one =>
q_dec <= '0'; db_level <= '1';
db_tick <= '0'; if (sw='0') then
state_next <= state_reg; state_next <= wait0;
case state_reg is q_load <= '1';
when zero => end if;
db_level <= '0'; when wait0=>
if (sw='1') then db_level <= '1';
state_next <= wait1; if (sw='0') then
q_load <= '1'; q_dec <= '1';
end if; if (q_zero='1') then
when wait1=> state_next <= zero;
db_level <= '0'; end if;
if (sw='1') then else -- sw='1'
q_dec <= '1'; state_next <= one;
if (q_zero='1') then end if;
state_next <= one; end case;
db_tick <= '1'; end process;
end if; end exp_fsmd_arch;
else -- sw='0'
state_next <= zero; 43
end if;
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Simple Processor
• R0, R1, R2, R3: n-bit registers
• Extern: control signal to enable n-bit external data input
• AddSub: 0 Sum A+B
1 difference A-B [2’s compliment of B]
• G: store output of add/sub with Gin, Gout control signals
• Operations performed in processor
• Load and Move operations require only one step (clock-cycle, one
transfer across the bus)
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• Add and Sub operations require three steps
Simple Processor
• Function: control signal input to
perform specific operation
initiated by setting w=1
• Done: output, when operation is
completed
• Control circuit is based on a two
bit counter since longest
operation needs three steps
• Each of the decoder outputs
represents a step in an operation.
• T0, T1, T2, T3: no-operation,
step_1 to step_3
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Simple Processor
• Function input: to
specify the operation
with six bits
• f1f0: opcode
• 00-Load,
• 01-Move,
• 10-Add,
• 11-Sub
• Rx1Rx0:operand Rx
• Ry1Ry0:operand Ry
• Function Register:
store function inputs
when FRin is asserted
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Simple Processor
6
Simple Processor
• Rest outputs from control circuit depend on the specific step
being performed in each operation
Simple Processor
Logic expressions for outputs of control circuit
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Simple Processor: VHDL Code
• Components:
• upcount
• regn
• trin
• dec2to4
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Simple Processor: Components
N-bit register
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Simple Processor: Components
COMPONENT : a piece of conventional code (LIBRARY declarations +ENTITY+ ARCHITECTURE).
By declaring such code as being a COMPONENT, it can then be used within another circuit.
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Simple Processor: Package
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Simple Processor: VHDL Code
• Reset: to initiate the counter to 00
• Func: six-bit signal (F & Rx & Ry), input to Function
register
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Simple Processor: VHDL Code
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Instantiation of
Function Register
with data inputs
Func and the
outputs FuncReg
Logic expressions
for the output of
control circuit
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Simple Processor: VHDL Code
Instantiation
of tri-state
buffers and
registers
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Description of
adder/subtraction module
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Simple Processor: VHDL Code: example results
• Start of an operation
at each ↑ and w=1
• At 250ns:
Load R0, data
• Next
Load R1, data
• Next
Load R2, data
• At 850ns
Add R1,R0
• At next ↑
R1(55) appear on bus
• At 950 ns
55 is loaded into A
and R0 (2A) on bus
Adder generate sum
7F,
• At 1050ns
Loaded into G
After this ↑, G (7F) is
placed on bus
• At 1150 ns
7F is loaded into R1
• Move R3,R1 65
• Sub R3,R2
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Computer System: Software
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Computer System:
Simple CPU Design: Single-Cycle Implementation
CPU Specification:
CPU External Busses- 16-bit external data bus and a 13- bit address bus.
General Purpose Registers- a 16-bit register: accumulator (acc).
Memory Organization- Capable of addressing 8192 words of memory; each
word has a 16 bit width.
Instruction Format-Each instruction is a 16-bit word and occupies a memory
word. Operands: An Explicit operand (the memory location whose address is
specified in the instruction)‚ and an implicit operand (acc).
The CPU has a total of 8 instructions‚ divided into three classes:
• Arithmetic-logical instructions (ADD‚ SUB‚ AND‚ and NOT)
• Data-transfer instructions (LDA‚ STA)
• Control-flow instructions (JMP‚ JZ) 69
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CPU Design:
Single-Cycle Implementation: datapath design
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Simple CPU Design
Step 2: Arithmetic-Logical Instruction
Data-Path.
•First operand is acc . Second operand
read from the data memory
•adr field of the instruction points to the
memory location that contains the
second operand (bits 12 to 0)
•Result of the operation is stored in acc
•arithmetic-logical unit (alu) performs the
operation of arithmetic and logical
instructions
•alu operation is controlled by a 2-bit
input‚ alu_op
•alu is designed as combinational circuit 73
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Simple CPU Design
Step 4: Data-Transfer Instruction
Datapath: LDA and STA
• LDA uses adr field of the instruction to
read a 16-bit data from data memory and
store it in acc register
• STA instruction writes the content of acc
into a data memory location pointed by the
adr field
• data memory have two control signals‚
mem_read and mem_write for control of
reading from it or writing into it.
• In order to control accumulator writing‚
the acc_write (write-control‚ or clock
enable) signal is needed 75
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Simple CPU Design
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Simple CPU Design
Instruction Execution : Example instruction- ADD 100
• On the rising edge of the clock, a new value is written into pc, and pc points
the instruction memory to read the instruction ADD 100.
• Memory read operation is complete and the controller starts to decode the
instruction.
• Controller issue the appropriate control signals to control the flow of data
in the datapath.
• On the next rising edge of the clock, the alu output is written into acc to
complete the execution of the current instruction and the pc+1 is written
into pc. This new value of pc points to the next instruction.
• Since the execution of the instruction is completed in one clock cycle‚ the
implementation is called single-cycle implementation.
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Simple CPU Design
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Data-Transfer Class:
LDA Instruction:
• mem_read=1 to read an operand from the data memory
• acc_write=1‚ to store the data memory output in acc
• alu_op is XX‚ because alu has no role in the execution of LDA
• acc_src=1‚ to direct data memory output to the acc input
• jmp_cond‚ and jmp_uncond are 0 to direct pc+1 to the pc input 82
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Simple CPU Design
STA Instruction:
• mem_write=1 to write acc into the data memory
• acc_write=0‚ so that the value of acc remains unchanged
• alu_op is XX because alu has no role in the execution of STA
• acc_src=X‚ because acc writing is disabled and its source is not important
• jmp_cond‚ and jmp_uncond are 0 to direct pc+1 to the pc input.
Control-Flow Class:
JMP Instruction:
• mem_read & mem_write are 0‚ because JMP does not read from or write into data
memory
• acc_write=0‚ because acc does not change during JMP
• alu_op is XX because alu has no role in execution of JMP
• acc_src=X‚ because acc writing is disabled and its source is not important
• jmp_cond=0‚ jmp_uncond=1‚ puts 1 on pc_src and directs jump address(12- 0) to pc83
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Simple CPU Design
CPU Design:
Multi-Cycle Implementation
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CPU Design:
Multi-Cycle Implementation: datapath design
• Use a single memory unit which stores both instructions and data‚
• Use a single alu which plays the role of both alu and the adder.
Sharing hardware adds one or more registers and multiplexers
• one multiplexer: To choose between the address of the memory unit from the pc
output (to address instructions) and bits 12 to 0 of the instruction (to address data)
• two multiplexers: at the alu inputs;
• first alu input‚ chooses between pc and acc
• second alu input, chooses between memory output and a constant value 1
alu inputs are 16 bits wide‚ so append 3 zeros on the left of pc to make 16-bits
• instruction register (ir): To store the instruction read from the memory
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Multi-Cycle Implementation:
Steps for execution of the instructions:
Instruction Fetch (IF): Read the instruction from memory and increment pc.
memory-read operation - pc addresses the memory for memory-read operation and
write the instruction into ir.
pc increment - apply pc to the first alu input‚ and the constant value 1 to the second
alu input‚ perform an addition‚ and store the alu output in pc
Instruction Decode (ID): Controller decodes the instruction (stored in ir) to issue the
appropriate control signals.
Execution (EX): Datapath operation in this step is determined by the instruction class:
Arithmetic-Logical Class: Apply bits 12 to 0 of ir to the memory‚ and perform a
memory read operation. Apply acc to the first alu input‚ and the memory output
to the second alu input‚ perform an alu operation (addition‚ subtraction‚ logical
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and‚ and negation)‚ and finally store the alu result into acc.
Multi-Cycle Implementation
Controller Design:
• Controller specify the appropriate control signals for each step
• Controller of a multi-cycle datapath is designed as a sequential circuit
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Datapath & Controller inter-connection
Multi-Cycle Implementation:
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Multi-Cycle Implementation: Controller design
State 0: IF step :
• pc is applied to memory address input (i_or_d=0)‚
• instruction is read from memory (mem_read=1),
• instruction is written into ir (ir_write=1)‚
• pc is incremented by 1 (src_a=0‚ src_b=1‚ alu_op=00‚ pc_src=1‚ pc_write_uncond=1).
Next State:
Arithmetic-logical instruction / LDA instruction /STA instruction /JMP instruction
/JZ instruction:
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