Advanced Microprocessor Systems
Advanced Microprocessor Systems
Power ROM/FLASH
Clock
Hypertransport/PCI express
3D sound,
Network Comm.
10/100bT/Gb/802.11
I/O Control A/V Joystick,
USB
Wireless, Ethernet, Optical IEEE488
Bluetooth
SCSI
IDE/ATA/SATA
FDDI
Peripherals
Mass Storage
Keyboard, Mouse, scanner, USB
SATA, RAID, DVD,
Blueray
CPU
Advancement
Mechanisms:
1)
Advances
in
processor
architecture:
RISC
Pipelining
Superscalar
Out-‐of-‐order
execu9on
RISC
-‐
a
system
that
uses
a
small,
highly-‐opBmized
set
of
instrucBons
that
typicaly
execute
in
one
clock
cycle,
rather
than
a
more
specialized
set
of
instrucBons
that
may
require
several
clock
cycles.
There
are
many
traits
associated
with
RISC.
For
example,
most
machines
are
implemented
with
mulBple
internal
buses
similar
to
a
Harvard
architecture.
Another
common
trait
is
that
RISC
systems
use
the
load/store
architecture,
where
memory
is
normally
accessed
only
through
specific
instrucBons,
rather
than
accessed
as
part
of
other
instrucBons
like
an
add.
Pipelining
-‐
a
technique
used
in
the
design
of
computers
to
increase
their
instrucBon
throughput.
Rather
than
processing
each
instrucBon
sequenBally,
each
instrucBon
is
split
up
into
a
sequence
of
steps
which
are
executed
within
a
small
offset
from
one
another.
Thus,
different
steps
can
be
executed
concurrently
(by
different
circuitry),
and
almost
in
parallel.
Superscalar
-‐
a
form
of
parallelism
called
instrucBon-‐level
parallelism
within
a
single
processor.
A
CPU
executes
more
than
one
instrucBon
during
a
clock
cycle
by
simultaneously
dispatching
mulBple
instrucBons
to
redundant
funcBonal
units
on
the
processor.
Out-‐of-‐order
execu9on
–
A
CPU
technique
involving:
• fetching
instrucBons
in
a
compiler-‐generated
order
Mechanical
1900
AD
1960 AD
1970
AD
OpBcal
Semiconductor
Quantum
1994
AD
Timeline
of
computaBonal
implementaBons
Molecular
Color
key:
Red
=
processor
Black
=
I/O
Lt.
gray
=
single
chip
19
=
contained
on
chip
Dark
gray
Package size
12 x 12 mm
Memory interface
Two types of LPDDR - SDRAM memories are supported in POP package: S4 and S2 with size up to 2GB
and 32-bit data width.
The POP device includes feedthroughs. The feedthroughs are defined from the bottom ball-grid array
(BGA) to the stacked memory. The purpose of some of the feedthroughs is to provide power supply to the
stacked memories.