Digital Logic Level

Gates and Boolean Algebra

• Gates
• Boolean Algebra
• Implementation of Boolean
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
o Multiplexers
o Demultiplexers
o Decoders
CHAPTER 3
o Comparator
• Arithmetic Circuits
o Shifters
o Half Adder
DIGITAL LOGIC LEVEL
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops
• Registers Faculty of Computer Systems and Technologies
• Memory Organization
• Memory Chips
o 4 Mbit University of Computer Studies, Yangon
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

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 GATES
Digital Logic Level
Gates and Boolean Algebra
• Gates • Binary information is represented in digital computers by
• Boolean Algebra
• Implementation of Boolean
Functions
physical quantities called signals.
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
• Electrical signals such as voltages exist throughout the
o Multiplexers
o Demultiplexers computer in either one of the two recognizable states:
o Decoders
o Comparator
• Arithmetic Circuits
o Shifters ❑ 1 (high voltage) or 0 (low voltage)
o Half Adder
o Full Adder
o ALU
• Clocks
Memory
• E.g., A signal between 0 and 0.5 volt represents binary 0.
• Latches
• Flip-Flops
• Registers
A signal between 1 and 1.5 volts represents binary 1.
• Memory Organization
• Memory Chips
o 4 Mbit
(Other voltages are not permitted)
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
Gates, tiny electronic devices can compute various
• Bus Clocking
o Synchronous Bus functions of these two-valued signals. These gates form the
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
hardware basis on which all digital computers are built.
• Bus Operations

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 FIVE BASIC GATES
Digital Logic Level
Gates and Boolean Algebra
• Gates
• Boolean Algebra
• Implementation of Boolean
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
o Multiplexers
o Demultiplexers
o Decoders
o Comparator
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations FIGURE 3.2
The Symbols and functional behavior for the five basic gates
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 BIPOLAR TRANSISTOR
Digital Logic Level
Gates and Boolean Algebra
• Gates • A Bipolar Junction Transistor, or BJT, is a
• Boolean Algebra
• Implementation of Boolean
Functions
solid-state device in which the current flow
• Circuit Equivalence
Basic Digital Logic Circuits
between two terminals (the collector and
• Integrated Circuits
• Combinational Circuits the emitter) is controlled by the amount of
o Multiplexers
o Demultiplexers current that flows through a third terminal
o Decoders
o Comparator (the base).
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops Vin is low → Vout is high
• Registers
• Memory Organization Vin is high → Vout is low
• Memory Chips
o 4 Mbit
o 512 Mbit
• This circuit is an inverter, converting a
CPU Chips and Buses
• CPU Chips logical 0 to a logical 1, and logical 1 to a
• Computer Buses
• Bus Width logical 0.
• Bus Clocking
o Synchronous Bus • The resistor is needed to limit the amount
o Asynchronous Bus
• Centralized Bus Arbitration of current drawn by the transistor so it does
• Decentralized Bus Arbitration Transistor Inverter
• Bus Operations
not burn out.

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 BIPOLAR TRANSISTOR
Digital Logic Level
Gates and Boolean Algebra
• Gates
• Two transistors are cascaded in series.
• Boolean Algebra
• Implementation of Boolean • If both V1 and V2 are high, both transistors
Functions
• Circuit Equivalence will conduct and Vout will be pulled low.
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
• If either input is low, the corresponding
o Multiplexers
o Demultiplexers
transistor will turn off, and the output will be
o Decoders high.
o Comparator
• Arithmetic Circuits
o Shifters • In other words, Vout will be low if and only if
o Half Adder
both V1 and V2 are high. NAND gate
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
• Two transistors are wired in parallel.
o 4 Mbit
o 512 Mbit
CPU Chips and Buses • If input is high, the corresponding
• CPU Chips
• Computer Buses transistor will turn on and pull the output
• Bus Width
• Bus Clocking down to ground.
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• If both inputs are low, the output will
• Bus Operations
NOR gate remain high.
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 BOOLEAN ALGEBRA
Digital Logic Level
Gates and Boolean Algebra
• Gates • In 1845, George Boole introduced a systematic treatment of logic now
• Boolean Algebra
• Implementation of Boolean called Boolean algebra.
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
• Logical statements are built up from:
o Multiplexers
o Demultiplexers • Variables: a, x, etc. Variables can be used to represent
o Decoders
o Comparator propositions (statements that are either true or false) or signals in
• Arithmetic Circuits
o Shifters
o Half Adder
digital circuits (voltages that are either high or low, representing 0
o Full Adder
o ALU
or 1).
• Clocks
Memory • Operators: The two operators (+, ●) are used to combine
• Latches
• Flip-Flops variables to produce more complex statements or logic functions.
• Registers
• Memory Organization These operators must satisfy certain properties.
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• The most well-known form of Boolean algebra is a two-valued
• Computer Buses
• Bus Width system, in which all variables take values on the set {0, 1} and the
• Bus Clocking
o Synchronous Bus operators (+, ●) correspond to (OR, AND) respectively.
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

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 BOOLEAN ALGEBRA

Implementation
• Write down the truth table for
the function.
• Provide inverters to generate
the complement of each input.
• Draw an AND gate for each
term with a 1 in the result
column.
• Wire the AND gates to the
appropriate inputs.
FIGURE 3.3
(a) Truth table of three • Feed the output of all the AND
variables (b) Circuit for (a) gates into an OR gate.

• The truth table for a Boolean function of three variables:

M = f(A, B, C)
ഥBC + AB
M= A ഥC + ABCത + ABC

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 CIRCUIT EQUIVALENCE
Digital Logic Level
Gates and Boolean Algebra • Circuit designers often try to reduce the number of gates in their
• Gates
• Boolean Algebra products to reduce the chip area needed to implement them, minimize
• Implementation of Boolean
Functions power consumption, and increase speed.
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits • To reduce the complexity of a circuit, the designer must find another
• Combinational Circuits
o Multiplexers circuit that computes the same function as the original but does so
o Demultiplexers
o Decoders
with fewer gates.
o Comparator
• Arithmetic Circuits
o Shifters E.g., two-input gates instead of four input gates
o Half Adder
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations FIGURE 3.4 Construction of (a) NOT, (b) AND, and (c) OR gates using only NAND
gates or only NOR gates.
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 CIRCUIT EQUIVALENCE
Digital Logic Level
Gates and Boolean Algebra
• Gates
• Boolean Algebra
• Implementation of Boolean
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
o Multiplexers
o Demultiplexers
o Decoders
o Comparator
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations FIGURE 3.5 (a) AB + AC. (b) A(B + C).

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 SOME IDENTITIES OF BOOLEAN ALGEBRA
Digital Logic Level
Gates and Boolean Algebra
• Gates
• Boolean Algebra
• Implementation of Boolean
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
o Multiplexers
o Demultiplexers
o Decoders
o Comparator
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

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 ALTERNATIVE SYMBOLS FOR SOME GATES
Digital Logic Level
Gates and Boolean Algebra
• Gates
• Boolean Algebra
• Implementation of Boolean
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits NAND gate NOR gate
o Multiplexers
o Demultiplexers
o Decoders • AND form is shown with negation • The dual form of De Morgan’s law, it
o Comparator
• Arithmetic Circuits
indicated by inversion bubbles, both should be clear that a NOR gate can
o Shifters for input and output. be drawn as an AND gate with
o Half Adder
o Full Adder • An OR gate with inverted inputs is inverted inputs.
o ALU
• Clocks
equivalent to a NAND gate.
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width AND gate OR gate
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Figures show equivalent representations of the AND and OR gates.
• Centralized Bus Arbitration • Analogous symbols exist for the multiple-variable forms of De Morgan’s law
• Decentralized Bus Arbitration
• Bus Operations (e.g., an 𝑛 input NAND gate becomes an OR gate with 𝑛 inverted inputs).
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 EXCLUSIVE OR
Digital Logic Level
Gates and Boolean Algebra
• Gates
• Boolean Algebra
• Implementation of Boolean
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
o Multiplexers (a)
o Demultiplexers
o Decoders
o Comparator
• Arithmetic Circuits The truth table for the XOR function.
o Shifters
o Half Adder
o Full Adder
o ALU
• Clocks • The standard sum-of-products circuit is shown in
Memory
• Latches
Fig. (a).
• Flip-Flops (b)
• Registers • To convert to NAND form, the lines connecting
• Memory Organization
• Memory Chips
the output of the AND gates to the input of the OR
o 4 Mbit gate should be redrawn with two inversion
o 512 Mbit
CPU Chips and Buses bubbles, as shown in Fig. (b).
• CPU Chips
• Computer Buses • The variables A and B can be generated from A
• Bus Width
• Bus Clocking and B using NAND or NOR gates with their inputs
o Synchronous Bus tied together. Note that inversion bubbles can be
o Asynchronous Bus (c)
• Centralized Bus Arbitration moved along a line at will, for example, from the
• Decentralized Bus Arbitration
• Bus Operations outputs of the input gates in Fig. (c) to the inputs Three circuits for computing
of the output gate. truth table of the XOR function.
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 INTEGRATED CIRCUITS
Digital Logic Level
Gates and Boolean Algebra Gates are not manufactured or sold individually but rather in units
• Gates
• Boolean Algebra called Integrated Circuits, often called ICs or chips.
• Implementation of Boolean
Functions
• Circuit Equivalence
Basic Digital Logic Circuits • An IC is a rectangular piece of silicon of varied size depending on how
• Integrated Circuits
• Combinational Circuits
many gates are required to implement the chip’s components.
o Multiplexers
o Demultiplexers • Small dies will measure about 2 mm × 2 mm, while larger dies can be as
o Decoders
o Comparator
large as 18 mm × 18 mm.
• Arithmetic Circuits
o Shifters • ICs are mounted into plastic or ceramic packages that can be much larger
o Half Adder
o Full Adder than the dies they house, if many pins are required to connect the chip to
o ALU
• Clocks
the outside world.
Memory
• Latches • Each pin connects to the input or output of some gate on the chip or to
• Flip-Flops
• Registers
power or to ground.
• Memory Organization
• Memory Chips
o 4 Mbit Common types of integrated-circuit packages
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

Dual-inline Package Pin Grid Array Land Grid Array

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 COMBINATIONAL CIRCUITS
Digital Logic Level
Gates and Boolean Algebra
• Gates Combinational Circuits: Many applications of digital logic
• Boolean Algebra
• Implementation of Boolean
Functions
require a circuit with multiple inputs and outputs in which the
• Circuit Equivalence
Basic Digital Logic Circuits outputs are uniquely determined by the current input values.
• Integrated Circuits
• Combinational Circuits
o Multiplexers
o Demultiplexers
o Decoders
o Comparator
• Not all circuits have this property.
• Arithmetic Circuits
o Shifters
o Half Adder
• For example, a circuit containing memory elements may generate
o Full Adder
o ALU
• Clocks
outputs that depend on the stored values as well as the input
Memory
• Latches variables.
• Flip-Flops
• Registers
• Memory Organization • Some frequently used combinational circuits,
• Memory Chips
o 4 Mbit
o 512 Mbit o Multiplexers
CPU Chips and Buses
• CPU Chips
• Computer Buses o Decoders
• Bus Width
• Bus Clocking
o Synchronous Bus
o Comparators
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

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 MULTIPLEXERS

• At the digital logic level, a multiplexer is a circuit

with 2n data inputs, one data output, and n
control inputs that select one of the data inputs.
• The selected data input is ‘‘gated’’ (i.e., sent) to
the output.
• In Fig.,
o The three control lines, A, B, and C,
encode a 3-bit number that specifies
which of the eight input lines is gated to
the OR gate and thence to the output.
o No matter what value is on the control
lines, seven of the AND gates will always
output 0; the other one may output either
0 or 1, depending on the value of the
selected input line.
o Each AND gate is enabled by a different
combination of the control inputs. An eight-input multiplexer circuit.

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 MULTIPLEXERS
Digital Logic Level
Gates and Boolean Algebra
• Gates
• Boolean Algebra
• Implementation of Boolean
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
o Multiplexers
o Demultiplexers
o Decoders
o Comparator
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder
o ALU
• Clocks (a) An eight-input multiplexer. (b) The same multiplexer wired to (c) Truth table
Memory compute the majority function.
• Latches
• Flip-Flops
• Registers
• Memory Organization • In Fig. (b), for each combination of A, B, and C, one of the data input
• Memory Chips
o 4 Mbit lines is selected.
o 512 Mbit
CPU Chips and Buses
• CPU Chips • Each input is wired to either Vcc (logical 1) or ground (logical 0).
• Computer Buses
• Bus Width
• Bus Clocking • The algorithm for wiring the inputs is simple: input Di is the same as
o Synchronous Bus
o Asynchronous Bus
the value in row i of the truth table.
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations
• In Fig. (c), rows 0, 1, 2, and 4 are 0, so the corresponding inputs are
grounded; the remaining rows are 1, so they are wired to logical 1.
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 DEMULTIPLEXER (DEMUX)
Digital Logic Level
Gates and Boolean Algebra • The inverse of a multiplexer is a demultiplexer, which routes its single input
• Gates
• Boolean Algebra
signal to one of 2𝑛 outputs, depending on the values of the n control lines.
• Implementation of Boolean
Functions
• If the binary value on the control lines is 𝑘, output 𝑘 is selected.
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
o Multiplexers
o Demultiplexers
o Decoders
o Comparator
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations Image copyright © www.electrically4u.com

Block diagram and circuit of 1 : 4 demux

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 DECODERS

• A circuit takes an n-bit number as input

and uses it to select (i.e., set to 1) exactly
one of the 2𝑛 output lines, such a circuit,
illustrated for n = 3 in Fig. is called a
decoder.
• It is useful for memory addressing.
• 3 bits are the three inputs, A, B, and C.
• Depending on the inputs, exactly one of
the eight output lines, D0, . . . , D7, is 1;
the rest are 0.
• Each output line enables one of the eight
memory chips because only one output
line is set to 1, only one chip is enabled.
A three-to-eight decoder circuit.
• The operation of the circuit of Fig. is straightforward.
• Each AND gate has three inputs, of which the first is either A or A, the second is either B
or B, and the third is either C or C.
• Each gate is enabled by a different combination of inputs: D0 by A B C, D1 by A B C, and
so on.
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 COMPARATORS
Digital Logic Level
Gates and Boolean Algebra
• Gates
• Boolean Algebra
• Implementation of Boolean
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
o Multiplexers
o Demultiplexers
o Decoders
o Comparator
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder
o ALU
• Clocks
Memory
• Latches A simple 4-bit comparator.
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit • A comparator is a circuit which compares two input words and
CPU Chips and Buses
• CPU Chips produces 1 if they are equal and 0 otherwise.
• Computer Buses
• Bus Width
• Bus Clocking • Based on the Exclusive-OR gate, which returns 0 if its inputs are equal
o Synchronous Bus
o Asynchronous Bus and 1 if, they are unequal.
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations • A NOR gate decided whether to return 1 for equality or 0 for inequality.

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 SHIFTERS
Digital Logic Level
Gates and Boolean Algebra
• Gates • For an eight-input, eight-output shifter, eight bits of input are
• Boolean Algebra
• Implementation of Boolean presented on lines D0, ..., D7.
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• The output, which is just the input shifted 1 bit, is available on lines
• Integrated Circuits
• Combinational Circuits
S0, ..., S7.
o Multiplexers
o Demultiplexers • The control line, C, determines the direction of the shift, 0 for left and
o Decoders
o Comparator 1 for right.
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

A 1-bit left/right shifter.

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 ADDERS - HALF ADDER
Digital Logic Level
Gates and Boolean Algebra
• Gates • A computer that cannot add integers is almost unthinkable.
• Boolean Algebra
• Implementation of Boolean • Consequently, a hardware circuit for performing addition is an
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
essential part of every CPU.
• Integrated Circuits
• Combinational Circuits
• For addition on 1-bit integers, two outputs are present: the sum of the
o Multiplexers
o Demultiplexers inputs, A and B, and the carry to the next (leftward) position.
o Decoders
o Comparator • A circuit can compute both the sum bit and the carry bit.
• Arithmetic Circuits
o Shifters
o Half Adder
• This simple circuit is generally known as a half adder.
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

(a) Truth table for 1-bit addition. (b) A circuit for a half adder.
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 ADDERS - FULL ADDER
Digital Logic Level
Gates and Boolean Algebra
• Gates
• A full adder is built up from two half adders.
• Boolean Algebra
• Implementation of Boolean • The Sum output line is 1 if an odd number of A, B, and the Carry in
Functions
• Circuit Equivalence are 1.
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
• The Carry out is 1 if either A and B are both 1 (left input to the OR
o Multiplexers
o Demultiplexers
gate) or exactly one of them is 1 and the Carry in bit is also 1.
o Decoders
o Comparator • Together the two half adders generate both the sum and the carry
• Arithmetic Circuits
o Shifters bits.
o Half Adder
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

(a) Truth table for full adder. (b) Circuit for a full adder.
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 ADDERS - FULL ADDER
Digital Logic Level
Gates and Boolean Algebra
• Gates Ripple Carry Adder
• Boolean Algebra
• Implementation of Boolean
Functions • The carry out of a bit is used as the carry into its left neighbor.
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• The carry into the rightmost bit is wired to 0.
• Combinational Circuits
o Multiplexers • This type of adder is called a ripple carry adder.
o Demultiplexers
o Decoders
o Comparator
• Arithmetic Circuits
o Shifters Carry Select Adder
o Half Adder
o Full Adder
o ALU • For a faster adder, consider breaking up a 32-bit adder into a 16-bit
• Clocks
Memory lower half and 16-bit upper half.
• Latches
• Flip-Flops
• Registers
• Instead of having a single upper half, give the adder two upper halves
• Memory Organization in parallel by duplicating the upper half.
• Memory Chips
o 4 Mbit
o 512 Mbit • The circuit consists of three 16-bit adders: a lower half and two upper
CPU Chips and Buses
• CPU Chips
halves, U0 and U1 that run in parallel.
• Computer Buses
• Bus Width • After a 16-bit addition times, it will be known what the carry into the
• Bus Clocking
o Synchronous Bus upper half is, so the correct upper half can be selected from the two
o Asynchronous Bus
• Centralized Bus Arbitration variable answers.
• Decentralized Bus Arbitration
• Bus Operations • This adder reduces the addition time by a factor of two.

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 ARITHMETIC LOGIC UNITS

• Arithmetic Logic Unit or ALU can

compute any one of four functions—
namely, A AND B, A OR B, B, or A + B,
depending on whether the function-select
input lines F0 and F1 contain 00, 01, 10,
or 11 (binary).
• A + B means the arithmetic sum of A and
B, not the Boolean OR.

• The INC signal is useful only

A 1-bit ALU.
for addition operations.
• When present, it increments
(i.e., adds 1 to) the result,
making it possible to
compute sums like A + 1 and
Eight 1-bit ALU slices connected to make an 8-bit ALU. The A + B + 1.
enables and invert signals are not shown for simplicity.
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 CLOCKS

A clock in this context is a circuit that emits a series of pulses with a precise pulse
width and precise interval between consecutive pulses.

• Clock Cycle Time: The time interval between the corresponding edges of two consecutive pulses
is known as the clock cycle time.
• Pulse frequencies are commonly between 100 MHz and 4 GHz, corresponding to clock cycles of
10 nsec to 250 psec.
• To achieve high accuracy, the clock frequency is usually controlled by a crystal oscillator.

➢ The timing diagram of Fig. (b) provides four time

references for discrete events:
1. Rising edge of C1.
2. Falling edge of C1.
3. Rising edge of C2.
(a) A clock. (b) The timing diagram for the clock. 4. Falling edge of C2.

➢ To generate an asymmetric pulse train, the basic

clock is shifted using a delay circuit and ANDed
with the original signal, as shown in Fig. (c) as C.
(c) Generation of an asymmetric clock.
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 SR LATCH
Digital Logic Level
Gates and Boolean Algebra
• Gates
• An essential component of every computer is its memory.
• Boolean Algebra
• Implementation of Boolean • Without memory there could be no computers as we now know them.
Functions
• Circuit Equivalence • Memory is used for storing both instructions to be executed and data.
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
o Multiplexers
o Demultiplexers SR Latch
o Decoders
o Comparator • Two inputs, S, for Setting the latch, and R, for Resetting (i.e., clearing) it.
• Arithmetic Circuits
o Shifters • Two outputs, 𝑄 and 𝑄,ത which are complementary.
o Half Adder
o Full Adder
o ALU
• Unlike a combinational circuit, the outputs of the latch are not uniquely
• Clocks
Memory
determined by the current inputs.
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations
(a) NOR latch in state 0. (b) NOR latch in state 1. (c) Truth table for NOR.
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 SR LATCH
Digital Logic Level
Gates and Boolean Algebra NOR latch in state 0
• Gates
• Boolean Algebra • Assume that both S and R are 0, which they are most of the time.
• Implementation of Boolean
Functions • Also assume that Q = 0.
• Circuit Equivalence
Basic Digital Logic Circuits • Because Q is fed back into the upper NOR gate, both of its inputs are 0, so its
• Integrated Circuits ത is 1.
output, 𝑄,
• Combinational Circuits
o Multiplexers • The 1 is fed back into the lower gate, which then has inputs 1 and 0, yielding
o Demultiplexers
o Decoders Q = 0.
o Comparator
• Arithmetic Circuits
• This state is consistent.
o Shifters
o Half Adder
o Full Adder NOR latch in state 1
o ALU
• Clocks • Assume that Q is 1, with R and S still 0.
Memory ത of 0, which is fed back
• The upper gate has inputs of 0 and 1, and an output, 𝑄,
• Latches
• Flip-Flops to the lower gate.
• Registers
• Memory Organization • This state is also consistent.
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
✓ A state with both outputs equal to 0 is inconsistent, because it forces both
• CPU Chips gates to have two 0s as input, which, if true, would produce 1, not 0, as
• Computer Buses
• Bus Width output.
• Bus Clocking
o Synchronous Bus ✓ Similarly, it is impossible to have both outputs equal to 1, because that would
o Asynchronous Bus
• Centralized Bus Arbitration force the inputs to 0 and 1, which yields 0, not 1.
• Decentralized Bus Arbitration
• Bus Operations ✓ Our conclusion is simple: for R = S = 0, the latch has two stable states, which
we will refer to as 0 and 1, depending on Q.
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 CLOCKED SR LATCHES
Digital Logic Level
Gates and Boolean Algebra
• Gates
• This circuit has an additional input, the clock, which is normally 0.
• Boolean Algebra
• Implementation of Boolean
Functions
• With the clock 0, both AND gates output 0, independent of S and R,
• Circuit Equivalence
Basic Digital Logic Circuits
and the latch does not change state.
• Integrated Circuits
• Combinational Circuits
o Multiplexers
• When the clock is 1, the effect of the AND gates vanishes and the
o Demultiplexers latch becomes sensitive to S and R.
o Decoders
o Comparator
• Arithmetic Circuits • Despite its name, the clock signal need not be driven by a clock.
o Shifters
o Half Adder
o Full Adder • The terms enable and strobe are also widely used to mean that the
o ALU
• Clocks clock input is 1; that is, the circuit is sensitive to the state of S and R.
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

A clocked SR latch.
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 CLOCKED D LATCHES
Digital Logic Level
Gates and Boolean Algebra
• Gates
• A latch circuit with only one input, D, where the input to the lower AND
• Boolean Algebra
• Implementation of Boolean
gate is always the complement of the input to the upper one, the
Functions
• Circuit Equivalence
problem of both inputs being 1 never arises.
Basic Digital Logic Circuits
• Integrated Circuits • When D = 1 and the clock is 1, the latch is driven into state Q = 1.
• Combinational Circuits
o Multiplexers • When D = 0 and the clock is 1, it is driven into state Q = 0.
o Demultiplexers
o Decoders
o Comparator
• In other words, when the clock is 1, the current value of D is sampled
• Arithmetic Circuits
o Shifters
and stored in the latch.
o Half Adder
o Full Adder • This circuit, called a clocked D latch, is a true 1-bit memory.
o ALU
• Clocks • The value stored is always available at Q. To load the current value of
Memory
• Latches D into the memory, a positive pulse is put on the clock line.
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

A clocked D latch.
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 FLIP-FLOPS
• In many circuits it is necessary to sample the value on a certain line at a particular instant
in time and store it.
• In this variant, called a flip-flop, the state transition occurs not when the clock is 1 but
during the clock transition from 0 to 1 (rising edge) or from 1 to 0 (falling edge) instead.
• The difference between a flip-flop and a latch
o A flip-flop is edge triggered
o A latch is level triggered

(a) A pulse generator. A D flip-flop.

(b) Timing at four points in the circuit.

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 FLIP-FLOPS
Digital Logic Level
Gates and Boolean Algebra • Fig. (a) is a latch whose state is loaded when the clock, CK, is 1.
• Gates
• Boolean Algebra
• Implementation of Boolean
• Fig. 3-26(b) is a latch whose clock is normally 1 but which drops to 0
Functions
• Circuit Equivalence
momentarily to load the state from D.
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
o Multiplexers • Fig. (c) and (d) are flip-flops rather than latches, which is indicated by the
o Demultiplexers
o Decoders pointy symbol on the clock inputs.
o Comparator
• Arithmetic Circuits • Fig. (c) changes state on the rising edge of the clock pulse (0-to-1
o Shifters
o Half Adder transition),
o Full Adder
o ALU • Fig. (d) changes state on the falling edge (1-to-0 transition).
• Clocks
Memory
• Latches
• Many, but not all, latches and flip-flops also have Q as an output, and
• Flip-Flops some have two additional inputs Set or Preset (force state to Q = 1) and
• Registers
• Memory Organization Reset or Clear (force state to Q = 0).
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

D latches and flip-flops.

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 REGISTERS
Digital Logic Level
Gates and Boolean Algebra • Flip-flops can be combined in groups to create registers, which hold
• Gates
• Boolean Algebra
• Implementation of Boolean
data types larger than 1 bit in length.
Functions
• Circuit Equivalence • The register in Fig. shows how eight flip-flops can be ganged together
Basic Digital Logic Circuits
• Integrated Circuits to form an 8-bit storage register.
• Combinational Circuits
o Multiplexers
o Demultiplexers
• The register accepts an 8-bit input value (I0 to I7) when the clock CK
o Decoders
o Comparator
transitions.
• Arithmetic Circuits
o Shifters • To implement a register, all the clock lines are connected to the same
o Half Adder
o Full Adder input signal CK, such that when the clock transitions, each register
o ALU
• Clocks will accept the new 8-bit data value on the input bus.
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

An 8-bit register constructed from single-bit flip-flops.

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 MEMORY ORGANIZATION
Digital Logic Level
Gates and Boolean Algebra
• Gates
• The 8 input lines and 3 output lines.
• Boolean Algebra
• Implementation of Boolean ✓ Three inputs are for data :I0, I1, I2
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
✓ Two inputs are for address : A0, A1
• Integrated Circuits
• Combinational Circuits ✓ Three inputs are for control : CS (Chip Select), RD
o Multiplexers
o Demultiplexers (ReaD or write), OE (Output Enable)
o Decoders
o Comparator
• Arithmetic Circuits
✓ Three outputs are for data : D0, D1, D2
o Shifters
o Half Adder
o Full Adder
o ALU • To select this memory chip, external logic must set CS high and also
• Clocks
Memory
set RD high (logical 1) for read and low (logical 0) for write.
• Latches
• Flip-Flops • The two address lines must be set to indicate which of the four 3-bit
• Registers
• Memory Organization words is placed on the data output lines.
• Memory Chips
o 4 Mbit
o 512 Mbit
• For a read operation, the word selected is placed on the data output
CPU Chips and Buses
• CPU Chips
lines.
• Computer Buses
• Bus Width • For a write operation, the bits present on the data input lines are
• Bus Clocking
o Synchronous Bus
loaded into the memory word.
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

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 Logic Diagram For A 4 × 3 Memory
Digital Logic Level
Gates and Boolean Algebra
• Gates
• Boolean Algebra
• Implementation of Boolean
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
o Multiplexers
o Demultiplexers
o Decoders
o Comparator
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width Logic diagram for a 4 × 3
• Bus Clocking
o Synchronous Bus
memory. Each row is one
o Asynchronous Bus of the four 3-bit words. A
• Centralized Bus Arbitration read or write operation
• Decentralized Bus Arbitration
• Bus Operations always reads or writes a
complete word.
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 TRI-STATE DEVICES
Digital Logic Level
Gates and Boolean Algebra
• Gates
• Boolean Algebra
• Implementation of Boolean
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
o Multiplexers
o Demultiplexers
o Decoders
o Comparator
• Arithmetic Circuits
o Shifters
(a) A noninverting buffer. (b) Effect of (a) when control is high.
o Half Adder (c) Effect of (a) when control is low. (d) An inverting buffer.
o Full Adder
o ALU
• Clocks
Memory
• Noninverting buffer has a data input, a data output, and a control
• Latches input, Fig. (a).
• Flip-Flops
• Registers
• Memory Organization
• When the control input is high, the buffer acts like a wire, Fig. (b).
• Memory Chips
o 4 Mbit • When the control input is low, the buffer acts like an open circuit, Fig.
o 512 Mbit
CPU Chips and Buses (c).
• CPU Chips
• Computer Buses • Inverting buffer acts like a normal inverter when control is high and
• Bus Width
• Bus Clocking disconnects the output from the circuit when control is low, Fig. (d).
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
Both kinds of buffers are tri-state devices, because they can
output 0, 1, or none of the above (open circuit).
• Bus Operations

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 THE REASON FOR USING TRI-STATE DEVICES
Digital Logic Level
Gates and Boolean Algebra
• Gates • Although the three OR gates were fed into the three output data
• Boolean Algebra
• Implementation of Boolean
Functions lines, doing so sometimes causes problems.
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
o Multiplexers
• Because in actual memories, the same lines for input and output are
o Demultiplexers
o Decoders
o Comparator
used.
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder • If we had tied the OR gates to the data output lines, the chip would
o ALU
• Clocks
Memory
try to output data, even on writes, thus interfering with the input
• Latches
• Flip-Flops
• Registers
data.
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit • For this reason, it is desirable to have a way to connect the OR
CPU Chips and Buses
• CPU Chips
• Computer Buses
gates to the data output lines on reads but disconnect them
• Bus Width
• Bus Clocking
o Synchronous Bus
completely on writes, by using a noninverting buffer.
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

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 TWO WAYS OF ORGANIZING A 4-MBIT MEMORY CHIP
Digital Logic Level
Gates and Boolean Algebra
• Gates • 19 address lines are needed to address
• Boolean Algebra
• Implementation of Boolean one of the 219 bytes.
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• Eight data lines are needed for loading or
• Integrated Circuits
• Combinational Circuits
storing the byte selected.
o Multiplexers
o Demultiplexers • 𝐶𝑆 (Chip Select) signal
o Decoders
o Comparator ✓ to enable the chip
• Arithmetic Circuits
o Shifters
o Half Adder
• 𝑊𝐸 (Write Enable) signal
o Full Adder
o ALU ✓ to indicate that data are being
• Clocks
Memory written rather than being read
• Latches
• Flip-Flops
• Registers
• 𝑂𝐸 (Output Enable) signal
• Memory Organization
• Memory Chips ✓ asserted to drive the output signals.
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• When it is not asserted, the chip output is
• CPU Chips
• Computer Buses
disconnected from the circuit.
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus 512K × 8 Memory Chip Design
• Centralized Bus Arbitration
• Decentralized Bus Arbitration 4Mbit = 512K × 8 = 29 × 210 × 8 = 219 × 8
• Bus Operations
address pins = 19, data pins = 8
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 TWO WAYS OF ORGANIZING A 4-MBIT MEMORY CHIP
Digital Logic Level
Gates and Boolean Algebra
• Gates
• 2048 × 2048 matrix of 1-bit cells, which
• Boolean Algebra
• Implementation of Boolean
gives 4 Mbits.
Functions
• Circuit Equivalence • n × n matrices that are addressed by row
Basic Digital Logic Circuits
• Integrated Circuits and column.
• Combinational Circuits
o Multiplexers • 𝐶𝑆 (Chip Select) signal
o Demultiplexers
o Decoders ✓ to enable the chip
o Comparator
• Arithmetic Circuits
o Shifters
• 𝑊𝐸 (Write Enable) signal
o Half Adder
o Full Adder
✓ to indicate that data are being written
o ALU
• Clocks
rather than being read
Memory
• Latches
• 𝑂𝐸 (Output Enable) signal
• Flip-Flops
• Registers ✓ asserted to drive the output signals.
• Memory Organization
• Memory Chips • When it is not asserted, the chip output is
o 4 Mbit
o 512 Mbit disconnected from the circuit.
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
4096K × 1 Memory Chip Design
o Synchronous Bus
o Asynchronous Bus 4Mbit = 4096K × 1 = 212 × 210 × 1
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations
= 222 × 1 = 211 × 211 × 1
RAS signal = 11 lines, CAS signal = 11 lines
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 TWO WAYS OF ORGANIZING A 512-MBIT MEMORY CHIP
Digital Logic Level
Gates and Boolean Algebra
• Gates
• Boolean Algebra
• Implementation of Boolean
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
o Multiplexers
o Demultiplexers
o Decoders
o Comparator
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
25 signals allow each of the 225 27 signals allow each of the 227
CPU Chips and Buses
• CPU Chips
internal 16-bit cells to be internal 4-bit cells to be
• Computer Buses
• Bus Width
addressed. addressed.
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
RAS signal = 13 lines RAS signal = 13 lines
• Centralized Bus Arbitration CAS signal = 10 lines CAS signal = 12 lines
• Decentralized Bus Arbitration
• Bus Operations bank select = 2 lines bank select = 2 lines

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 CPU CHIPS
Digital Logic Level
Gates and Boolean Algebra
• Gates
• All modern CPUs are contained on a single chip.
• Boolean Algebra
• Implementation of Boolean • Each CPU chip has a set of pins, through which all its communication
Functions
• Circuit Equivalence with the outside world must take place.
Basic Digital Logic Circuits
• Integrated Circuits • Some pins output signals from the CPU to the outside world; others
• Combinational Circuits
o Multiplexers accept signals from the outside world; some can do both.
o Demultiplexers
o Decoders
o Comparator
• Arithmetic Circuits
• The pins on a CPU chip can be divided into three types: address, data,
o Shifters and control.
o Half Adder
o Full Adder
o ALU
• These pins are connected to similar pins on the memory and I/O chips via
• Clocks
Memory
a collection of parallel wires called a bus.
• Latches
• Flip-Flops
• To fetch an instruction, the CPU first puts the memory address of that
• Registers
• Memory Organization
instruction on its address pins.

• Two of the key parameters that determine the performance of a CPU are
the number of address pins and the number of data pins.
• A chip with m address pins can address up to 2𝑚 memory locations.
Common values of 𝑚 are 16, 32, and 64.
• Similarly, a chip with 𝑛 data pins can read or write an n-bit word in a
single operation. Common values of 𝑛 are 8, 32, and 64.

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 CPU CHIPS
Digital Logic Level
Gates and Boolean Algebra
• Gates • In addition to address and data pins, each CPU has some control
• Boolean Algebra
• Implementation of Boolean pins.
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• They regulate the flow and timing of data to and from the CPU and
• Integrated Circuits
• Combinational Circuits
have other miscellaneous uses.
o Multiplexers
o Demultiplexers • The control pins can be roughly grouped into the following major
o Decoders
o Comparator categories:
• Arithmetic Circuits
o Shifters
o Half Adder
1. Bus control.
o Full Adder
o ALU
2. Interrupts.
• Clocks
Memory 3. Bus arbitration.
• Latches
• Flip-Flops 4. Coprocessor signaling.
• Registers
• Memory Organization
• Memory Chips
5. Status.
o 4 Mbit
o 512 Mbit 6. Miscellaneous
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
The logical pinout of a generic CPU. The arrows indicate input signals and
• Bus Operations output signals. The short diagonal lines indicate that multiple pins are
used. For a specific CPU, a number will be given to tell how many.
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 COMPUTER BUSES
Digital Logic Level
• A bus is a common electrical pathway between multiple devices.
Gates and Boolean Algebra
• Gates
• Boolean Algebra
• Buses can be categorized by their function.
• Implementation of Boolean
Functions • They can be used internal to the CPU to transport data to and from the ALU, or
• Circuit Equivalence
Basic Digital Logic Circuits
external to the CPU to connect it to memory or to I/O devices.
• Integrated Circuits
• Combinational Circuits
• Each type of bus has its own requirements and properties.
o Multiplexers
o Demultiplexers • Early personal computers had a single external bus or system bus.
o Decoders
o Comparator • It consisted of 50 to 100 parallel copper wires etched onto the motherboard,
• Arithmetic Circuits
o Shifters
with connectors spaced at regular intervals for plugging in memory and I/O
o Half Adder boards.
o Full Adder
o ALU
• Clocks
• Modern personal computers generally have a special-purpose bus between the
Memory CPU and memory and (at least) one other bus for the I/O devices.
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

A computer system with multiple buses.

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 BUS PROTOCOL
Digital Logic Level
Gates and Boolean Algebra
• Gates • While the designers of the CPU are free to use any kind of bus they
• Boolean Algebra
• Implementation of Boolean want inside the chip, in order to make it possible for boards designed
Functions
• Circuit Equivalence by third parties to attach to the system bus, there must be well-
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
defined rules about how the external bus works, which all devices
o Multiplexers
o Demultiplexers attached to it must obey.
o Decoders
o Comparator • These rules are called the bus protocol.
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder
o ALU
• Governs format, content, timing of data, memory addresses, and
• Clocks
Memory
control messages sent across bus
• Latches
• Flip-Flops • We can’t let two devices put data on the bus at the same time. So, we
• Registers
• Memory Organization need access control.
• Memory Chips
o 4 Mbit
o 512 Mbit
• Approaches for access control
CPU Chips and Buses
• CPU Chips ✓ Master-Slave approach – traditional – CPU is bus master, and
• Computer Buses
• Bus Width all other devices are slaves.
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

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 MASTER BUS & SLAVE BUS
Digital Logic Level
Gates and Boolean Algebra
• Gates
• Some devices that attach to a bus are active and can initiate bus
• Boolean Algebra
• Implementation of Boolean
transfers, whereas others are passive and wait for requests.
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• The active ones are called masters; the passive ones are called
• Integrated Circuits slaves.
• Combinational Circuits
o Multiplexers
o Demultiplexers • When the CPU orders a disk controller to read or write a block, the
o Decoders
o Comparator CPU is acting as a master and the disk controller is acting as a slave.
• Arithmetic Circuits
o Shifters
o Half Adder
• Under no circumstances can memory ever be a master.
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus Examples of bus masters and slaves.
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

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 BUS DRIVER
Digital Logic Level
Gates and Boolean Algebra
• Gates
• The binary signals that computer devices output are frequently too weak
• Boolean Algebra to power a bus, especially if it is relatively long or has many devices on it.
• Implementation of Boolean
Functions
• Circuit Equivalence • For this reason, most bus masters are connected to the bus by circuitry
Basic Digital Logic Circuits
• Integrated Circuits called a bus driver, which is essentially a digital amplifier.
• Combinational Circuits
o Multiplexers
o Demultiplexers
o Decoders
o Comparator
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations Image copyright © robotics.org.za

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 BUS TRANSCEIVER
Digital Logic Level
Gates and Boolean Algebra
• Gates
• Boolean Algebra • Similarly, most slaves are connected to the bus by a bus receiver.
• Implementation of Boolean
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• For devices that can act as both master and slave, a combined circuit
• Integrated Circuits
• Combinational Circuits called a bus transceiver is used.
o Multiplexers
o Demultiplexers
o Decoders
o Comparator
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops Image copyright © xcluma.com
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration Image copyright © http://tok.hakynda.com
• Bus Operations

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 OPEN COLLECTOR, WIRED-OR
Digital Logic Level
Gates and Boolean Algebra
• Gates
• These bus interfaces are often tri-state devices, to allow them to float
• Boolean Algebra (disconnect) when they are not needed, or are hooked up in a somewhat
• Implementation of Boolean
Functions different way, called open collector, that achieves a similar effect.
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits
o Multiplexers
o Demultiplexers
o Decoders
o Comparator
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder
o ALU
• Clocks
Memory Image copyright © learn.adafruit.com
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips • When two or more devices on an open-collector line assert the line
o 4 Mbit
o 512 Mbit at the same time, the result is the Boolean OR of all the signals.
CPU Chips and Buses
• CPU Chips
• Computer Buses
• This arrangement is often called wired-OR.
• Bus Width
• Bus Clocking • Wired-OR is a technique to reduce the number of gates and to use
o Synchronous Bus
o Asynchronous Bus only one signal.
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations • On most buses, some of the lines are tri-state and others, which
need the wired-OR property, are open collector.
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 BUS WIDTH

• Bus width is the most obvious design parameter.

• The more address lines a bus has, the more memory the CPU can address directly.
• If a bus has n address lines, then a CPU can use it to address 2n different memory locations.
• To allow large memories, buses need many address lines.

• The original IBM PC • Intel flet it had to increase the • Unfortunately, more control
contained an 8088 CPU and address space to 16 MB, so lines had to be added to deal
a 20-bit address bus. four more bus lines were with the new address lines.
added.
• Having 20 bits allowed the • When the 80386 came out,
PC to address 1 MB of (without disturbing the original 20, another eight address lines
memory. for reasons of backward were added, along with still
compatibility) more control lines.

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 BUS WIDTH (BUS SKEW)
Digital Logic Level
Gates and Boolean Algebra
• Gates • The number of data lines needed also tends to increase over time.
• Boolean Algebra
• Implementation of Boolean • There are two ways to increase the bandwidth of a bus:
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
✓ decrease the bus cycle time (more transfers/sec)
• Integrated Circuits
• Combinational Circuits ✓ increase the data bus width (more bits/transfer)
o Multiplexers
o Demultiplexers • Speeding the bus up is possible because the signals on different lines
o Decoders
o Comparator travel at slightly different speeds, a problem known as bus skew.
• Arithmetic Circuits
o Shifters
o Half Adder
• The faster the bus, the more the skew.
o Full Adder
o ALU • This also makes the bus non-compatible with pre-existing devices.
• Clocks
Memory
• Latches
• Flip-Flops
• Registers
• Therefore, the usual approach to improving performance is to add
• Memory Organization
• Memory Chips
more data lines (data bus width).
o 4 Mbit
o 512 Mbit E.g. in the PC which went from 8 data lines to 16 and then to 32 on
CPU Chips and Buses
• CPU Chips essentially the same bus
• Computer Buses
• Bus Width
• Bus Clocking
• Another solution is to use a multiplexed bus.
o Synchronous Bus
o Asynchronous Bus
• The same lines are used for both data and addressing by breaking up
• Centralized Bus Arbitration
• Decentralized Bus Arbitration the bus operation into multiple steps. This slows down bus
• Bus Operations
performance.
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 SYNCHRONOUS BUSES
Digital Logic Level
Gates and Boolean Algebra
• Gates • A synchronous bus is driven by a master clock.
• Boolean Algebra
• Implementation of Boolean • All bus activities take an integral number of these cycles, called bus
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
cycles and synchronous bus is faster to use.
• Integrated Circuits
• Combinational Circuits
o Multiplexers
o Demultiplexers
o Decoders
o Comparator
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations
Read timing on a synchronous bus.
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 SYNCHRONOUS BUSES
Digital Logic Level
Gates and Boolean Algebra
• Gates
F = 100MHz = 100 *106 cycles per second
• Boolean Algebra
• Implementation of Boolean
Functions
T = 1/F = 1/(102 * 106) = 1/108 = 10-8 = 10 * 10-9 = 10 nsec
• Circuit Equivalence
Basic Digital Logic Circuits
• Integrated Circuits
• Combinational Circuits Memory read time after 𝑀𝑅𝐸𝑄
o Multiplexers
o Demultiplexers was asserted = Total – TM – TDS
o Decoders
o Comparator = (5 + 10 + 5) – 3 – 2
• Arithmetic Circuits
o Shifters
= 20 – 5 = 15 nsec
o Half Adder
o Full Adder
Memory read time after
o ALU
• Clocks
the address appears = Total – TAD – TDS
Memory = (10 + 10 + 5) – 4 -2
• Latches
• Flip-Flops = 25 – 6 = 19 nsec
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

Specification of some critical times.

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 ASYNCHRONOUS BUSES
Digital Logic Level
Gates and Boolean Algebra
• Gates
• An asynchronous bus does not have a master clock.
• Boolean Algebra
• Implementation of Boolean • Full handshaking is used to synchronize the slave to the master.
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
• Bus cycles can be of any length required and need not be the same
• Integrated Circuits
• Combinational Circuits
between all pairs of devices.
o Multiplexers
o Demultiplexers • Each event is caused by a pair event, not by a clock pulse.
o Decoders
o Comparator
• Arithmetic Circuits
o Shifters
o Half Adder
• Mixed technology can be handled by going to an asynchronous bus,
o Full Adder
o ALU
that is, one with no master clock, as shown in Fig..
• Clocks
Memory
• Latches
• Instead of tying everything to the clock, when the bus master has
• Flip-Flops asserted the address, MREQ, RD, and anything else it needs to, it
• Registers
• Memory Organization then asserts a special signal that we will call 𝑀𝑆𝑌𝑁 (Master
• Memory Chips
o 4 Mbit SYNchronization).
o 512 Mbit
CPU Chips and Buses
• CPU Chips • When the slave sees this, it performs the work as fast as it can.
• Computer Buses
• Bus Width
• Bus Clocking
• When it is done, it asserts 𝑆𝑆𝑌𝑁 (Slave SYNchronization).
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

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 ASYNCHRONOUS BUSES (FULL HANDSHAKE)
Digital Logic Level
Gates and Boolean Algebra
• Gates • A set of signals that interlocks this way is called a full handshake.
• Boolean Algebra
• Implementation of Boolean The essential part consists of four events:
Functions
• Circuit Equivalence
Basic Digital Logic Circuits
1. 𝑀𝑆𝑌𝑁 is asserted.
• Integrated Circuits
• Combinational Circuits
2. 𝑆𝑆𝑌𝑁 is asserted in response to 𝑀𝑆𝑌𝑁.
o Multiplexers
o Demultiplexers 3. 𝑀𝑆𝑌𝑁 is negated in response to 𝑆𝑆𝑌𝑁 .
o Decoders
o Comparator 4. 𝑆𝑆𝑌𝑁 is negated in response to the negation of 𝑀𝑆𝑌𝑁 .
• Arithmetic Circuits
o Shifters
o Half Adder
o Full Adder
o ALU
• Clocks
Memory
• Latches
• Flip-Flops
• Registers
• Memory Organization
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations

Operation of an asynchronous bus.

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 CENTRALIZED BUS ARBITRATION
Digital Logic Level
Gates and Boolean Algebra
Bus Arbitration : The mechanism that uses when two or more devices
• Gates all want to become bus master at the same time.
• Boolean Algebra
• Implementation of Boolean
Functions
• Circuit Equivalence
• In centralized bus arbitration scheme, a single bus arbiter determines who
Basic Digital Logic Circuits goes next.
• Integrated Circuits
• Combinational Circuits • When the arbiter sees a bus request, it issues a grant by asserting the bus
o Multiplexers
o Demultiplexers grant line.
o Decoders
o Comparator • This line is wired through all the I/O devices in series.
• Arithmetic Circuits
o Shifters • When the device physically closest to the arbiter sees the grant, it checks to
o Half Adder see if it has made a request.
o Full Adder
o ALU • If so, it takes over the bus but does not propagate the grant further down the
• Clocks
Memory line.
• Latches
• Flip-Flops • If it has not made a request, it propagates the grant to the next device in line,
• Registers
• Memory Organization
which behaves the same way, and so on until some device accepts the grant
• Memory Chips and takes the bus. This scheme is called daisy chaining.
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations
A centralized one-level bus arbiter using daisy chaining.
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 CENTRALIZED BUS ARBITRATION
Digital Logic Level
Gates and Boolean Algebra
• Gates
• To get around the implicit priorities based on distance from the arbiter,
• Boolean Algebra many buses have multiple priority levels.
• Implementation of Boolean
Functions
• Circuit Equivalence • For each priority level there is a bus request line and a bus grant line. The
Basic Digital Logic Circuits
• Integrated Circuits
one of Fig. has two levels, 1 and 2 (real buses often have 4, 8, or 16
• Combinational Circuits levels).
o Multiplexers
o Demultiplexers
o Decoders
• Each device attaches to one of the bus request levels, with more time-
o Comparator critical devices attaching to the higher-priority ones.
• Arithmetic Circuits
o Shifters
o Half Adder
• In Fig. devices, 1, 2, and 4 use priority 1 while devices 3 and 5 use
o Full Adder priority 2.
o ALU
• Clocks
Memory
• If multiple priority levels are requested at the same time, the arbiter issues
• Latches a grant only on the highest-priority one.
• Flip-Flops
• Registers
• Memory Organization
• Among devices of the same priority, daisy chaining is used.
• Memory Chips
o 4 Mbit
o 512 Mbit
CPU Chips and Buses
• CPU Chips
• Computer Buses
• Bus Width
• Bus Clocking
o Synchronous Bus
o Asynchronous Bus
• Centralized Bus Arbitration
• Decentralized Bus Arbitration
• Bus Operations
The same arbiter, but with two levels.
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 DECENTRALIZED BUS ARBITRATION

• Decentralized bus arbitration uses only three lines, no matter how many devices are present.
• The first bus line is a wired-OR line for requesting the bus.
• The second bus line is called BUSY and is asserted by the current bus master.
• The third line is used to arbitrate the bus.
• To acquire the bus, a device first checks to see if the bus is idle and the arbitration signal it is
receiving, IN, is asserted.
• If IN is negated, it may not become bus master, and it negates OUT.
• If IN is asserted, the device wants the bus, the device negates OUT, which causes its
downstream neighbor to see IN negated and to negate its OUT.
• When the dust settles, only one device will have IN asserted and OUT negated.
• This device becomes bus master, asserts BUSY and OUT, and begins its transfer.

Decentralized bus arbitration.

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 BUS OPERATIONS
• One word at a time is transferred.
• When caching is used, it is desirable to fetch an entire cache line at once.
• Often block transfers can be made more efficient than successive individual transfers.
• When a block read is started, the bus master tells the slave how many words are to be
transferred, for example, by putting the word count on the data lines during T1.
• Instead of just returning one word, the slave outputs one word during each cycle until the
count has been exhausted.
• Now with an extra signal BLOCK that is asserted to indicate that a block transfer is requested.

A block transfer.
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 BUS OPERATIONS (INTERRUPT VECTORS)
• Another important kind of bus cycle is for handling interrupts.
• When the CPU commands an I/O device to do something, it usually expects an interrupt
when the work is done. The interrupt signaling requires the bus.
• Since multiple devices may want to cause an interrupt simultaneously, the same kind of
arbitration problems are present here that we had with ordinary bus cycles.
• The usual solution is to assign priorities to devices and use a centralized arbiter to give
priority to the most time-critical devices.
• Standard interrupt interfaces exist and are widely used.

• The CPU hardware uses the number to index into a table of pointers, called interrupt
vectors, to find the address of the procedure to run to service the interrupt.

Use of the 8259A interrupt controller.

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 REFERENCE

STRUCTURED COMPUTER ORGANIZATION

6th edition, PEARSON
Andrew S. Tanenbaum, Todd Austin.

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