Instruction Set Architecture

Level
Instruction Formats
• Design Criteria for Instruction
Formats
• Expanding Opcodes
Addressing
• Addressing Modes
• Immediate Addressing
• Direct Addressing
• Register Addressing
CHAPTER 5
• Register Indirect Addressing
• Index Addressing
• Based-Indexed Addressing INSTRUCTION SET ARCHITECTURE LEVEL
• Stack Addressing
• Evaluation of Reverse Polish
Notation Formula

Faculty of Computer Systems and Technologies

University of Computer Studies, Yangon

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 INSTRUCTION FORMATS
Instruction Set Architecture
Level • An instruction consists of an opcode, usually along with some additional
Instruction Formats information such as where operands come from and where results go to.
• Design Criteria for Instruction
Formats • Addressing: The general subject of specifying where the operands are (i.e.,
• Expanding Opcodes
Addressing
their addresses).
• Addressing Modes • Four common instruction formats: (a) Zero-address instruction. (b) One-
• Immediate Addressing
• Direct Addressing address instruction (c) Two-address instruction. (d) Three-address
• Register Addressing instruction.
• Register Indirect Addressing
• Index Addressing
• Based-Indexed Addressing
• Stack Addressing
• Evaluation of Reverse Polish
Notation Formula

• On some machines, all instructions have the same length; on others there
may be many different lengths.
• Instructions may be shorter than, the same length as, or longer than the word
length.

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 DESIGN CRITERIA FOR INSTRUCTIO FORMATS
Instruction Set Architecture
Level • The efficiency of a particular ISA is highly dependent on the
Instruction Formats
• Design Criteria for Instruction
technology with which the computer is to be implemented.
Formats
• Expanding Opcodes
Addressing
❑ E.g. if memory accesses are fast, a stack based design (like
• Addressing Modes IJVM) is a good one, but if they are slow, then having many
• Immediate Addressing
• Direct Addressing
registers is the way to go.
• Register Addressing
• Register Indirect Addressing • Short instructions are better than long ones. A program consisting of n
• Index Addressing
• Based-Indexed Addressing
16-bit instructions takes up only half as much memory space as n
• Stack Addressing 32-bit instructions.
• Evaluation of Reverse Polish
Notation Formula
• A second design criterion is sufficient room in the instruction format
to express all the operations desired. A machine with 2n operations
with all instructions smaller than n bits is impossible.
• A third criterion concerns the number of bits in an address field. In
order to gain a finer memory resolution, one must pay the price of
longer addresses and thus longer instructions.

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 EXPANDING OPCODES
Instruction Set Architecture
Level • An (n + k) bit instruction with a k-bit opcode and a single n-bit address
Instruction Formats
• Design Criteria for Instruction ❑ This instruction allows 2k different operations and 2n addressable
Formats
• Expanding Opcodes memory cells.
Addressing
• Addressing Modes
• Immediate Addressing
• Direct Addressing • The same (n + k) bits could be broken up into a (k - 1) bit opcode, and
• Register Addressing
• Register Indirect Addressing an (n + 1) bit address.
• Index Addressing
• Based-Indexed Addressing ❑ Only half as many instructions but either twice as much memory
• Stack Addressing
• Evaluation of Reverse Polish addressable, or the same amount of memory but with twice the
Notation Formula
resolution

• A (k + 1) bit opcode and an (n - 1) bit address

❑ Gives more operations, but the price is either a smaller number
of cells addressable, or poorer resolution and the same amount
of memory addressable.

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 EXPANDING OPCODES
Instruction Set Architecture
Level
Instruction Formats
• Design Criteria for Instruction
Formats
• Expanding Opcodes
Addressing
• Addressing Modes
• Immediate Addressing
• Direct Addressing An instruction with a 4-bit opcode and three 4-bit address fields.
• Register Addressing
• Register Indirect Addressing
• Index Addressing
• Based-Indexed Addressing • A 16-bit instruction with a 4-bit opcode and three 4-bit address fields
• Stack Addressing
• Evaluation of Reverse Polish might be reasonable for a machine that has 16 registers (hence a 4-
Notation Formula
bit register address) on which all arithmetic operations take place.
• One design would be giving 16 three-address instructions.

If the designers need 15 three-address instructions, 14 two-address

instructions, 31 one-address instructions, and 16 instructions with
no address at all, the expanding opcode can be used.

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 EXPANDING OPCODES
Instruction Set Architecture
Level
Instruction Formats
• Design Criteria for Instruction
Formats
• Expanding Opcodes
Addressing
• Addressing Modes
• Immediate Addressing
• Direct Addressing
• Register Addressing
• Register Indirect Addressing
• Index Addressing
• Based-Indexed Addressing
• Stack Addressing
• Evaluation of Reverse Polish o An expanding opcode allowing
Notation Formula

❑ 15 three-address instructions,

❑ 14 two-address instructions,

❑ 31 one-address instructions,

❑ 16 zero-address instructions.

o The fields marked xxxx, yyyy, and

zzzz are 4-bit address fields.

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 ADDRESSING MODES
Instruction Set Architecture
Level Addressing is the way to specify where the operands of an
Instruction Formats
• Design Criteria for Instruction instruction are.
Formats
• Expanding Opcodes
Addressing
• Addressing Modes
• Generally, the programs are written in a high-level language, as it is a
• Immediate Addressing convenient way to define the variables and operations that the
• Direct Addressing
programmer needs to perform on the variables.
• Register Addressing
• Register Indirect Addressing • Later, this program is compiled to generate the machine code which has
• Index Addressing
• Based-Indexed Addressing low-level instructions.
• Stack Addressing
• Evaluation of Reverse Polish
• The low-level instruction has opcode and operands.
Notation Formula
• Addressing mode has nothing to do with the opcode part.
• It focuses on presenting the operand’s address in the instructions.

• How the bits of an address field are interpreted to find the operand.
1. Immediate addressing
2. Direct addressing
3. Register addressing
4. Register indirect addressing
5. Indexed addressing
6. Based-Indexed addressing
7. Stack addressing
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 IMMEDIATE ADDRESSING
Instruction Set Architecture
Level • The address part of the instruction actually contains the operand itself
Instruction Formats
• Design Criteria for Instruction
rather than an address or other information describing where the
Formats
• Expanding Opcodes
operand is.
Addressing
• Addressing Modes • Such an operand is called an immediate operand because it is
• Immediate Addressing
• Direct Addressing
automatically fetched from memory at the same time the instruction
• Register Addressing itself is fetched; hence it is immediately available for use.
• Register Indirect Addressing
• Index Addressing
• Based-Indexed Addressing
• Immediate addressing has the virtue of not requiring an extra memory
• Stack Addressing reference to fetch the operand.
• Evaluation of Reverse Polish
Notation Formula
• It has the disadvantage that only a constant can be supplied this way.

An immediate instruction for

loading 4 into register 1.

ADD R2, #100

STORE R2, 100H Image copyright © binaryterms.com

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 DIRECT ADDRESSING
Instruction Set Architecture
Level • A method for specifying an operand in memory is just to give its full
Instruction Formats
• Design Criteria for Instruction
address. This mode is called direct addressing.
Formats
• Expanding Opcodes • In direct addressing, the instruction will always access exactly the
Addressing
• Addressing Modes
same memory location.
• Immediate Addressing
• Direct Addressing
• So while the value can change, the location cannot.
• Register Addressing
• Register Indirect Addressing • Direct addressing can only be used to access global variables whose
• Index Addressing address is known at compile time.
• Based-Indexed Addressing
• Stack Addressing
• Evaluation of Reverse Polish
Notation Formula

ADD R2, A
STORE R2, B

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 REGISTER ADDRESSING
Instruction Set Architecture
Level • Register addressing is conceptually the same as direct addressing
Instruction Formats
• Design Criteria for Instruction
but specifies a register instead of a memory location.
Formats
• Expanding Opcodes
Addressing
• Because registers are so important (due to fast access and short
• Addressing Modes addresses) this addressing mode is the most common one on most
• Immediate Addressing
• Direct Addressing
computers.
• Register Addressing
• Register Indirect Addressing • The only time this addressing mode is not used is when an operand is
• Index Addressing
• Based-Indexed Addressing
moved from memory into a register (LDR instruction) or from a
• Stack Addressing register to memory (STR instruction).
• Evaluation of Reverse Polish
Notation Formula

ADD R4, R3
LOAD R3, R2
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 REGISTER INDIRECT ADDRESSING
Instruction Set Architecture
Level • The address is contained in a register. An address used in this manner is
Instruction Formats called a pointer.
• Design Criteria for Instruction
Formats
• Expanding Opcodes
• A big advantage of register indirect addressing is that it can reference memory
Addressing without paying the price of having a full memory address
• Addressing Modes in the instruction.
• Immediate Addressing
• Direct Addressing
• Register Addressing
• Register Indirect Addressing
• Index Addressing
• Based-Indexed Addressing
• Stack Addressing
• Evaluation of Reverse Polish
Notation Formula

A generic assembly program for computing the sum of the elements of an array.

Use several addressing modes

❖ The first three instructions use register mode for the first operand (the destination) and
immediate mode for the second operand (a constant indicated by the # sign).
❖ The second instruction puts the address of A in R2, not the contents.
❖ That is what the # sign tells the assembler.
❖ Similarly, the third instruction puts the address of the first word beyond the array in R3.
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 INDEXED ADDRESSING

• It is frequently useful to be able to reference memory words at a known offset from a

register.
E.g. In IJVM, local variables are referenced by giving their offset from LV.
• Addressing memory by giving a register (explicit or implicit) plus a constant offset is
called indexed addressing.

1. R1 — Holds the
accumulated OR of the
Boolean product terms.
2. R2 — The index, i, that is
used to step through the
arrays.
3. R3 — The constant 4096,
which is the lowest value of i
A generic assembly program for computing the OR of Ai AND Bi not to use.
for two 1024-element arrays. 4. R4 — A scratch register for
holding each product as it is
formed.

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 BASED-INDEXED ADDRESSING
Instruction Set Architecture
Level • Some machines have an addressing mode in which the memory
Instruction Formats
• Design Criteria for Instruction address is computed by adding up two registers plus an (optional)
Formats
• Expanding Opcodes offset.
Addressing
• Addressing Modes • Sometimes this mode is called based-indexed addressing.
• Immediate Addressing
• Direct Addressing • One of the registers is the base and the other is the index.
• Register Addressing
• Register Indirect Addressing
• Index Addressing
• Based-Indexed Addressing • Outside the loop we could have put the address of A in R5 and the
• Stack Addressing
• Evaluation of Reverse Polish address of B in R6.
Notation Formula
• Then we could have replaced the instruction at LOOP and its
successor with;

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 STACK ADDRESSING
Instruction Set Architecture
Level • Zero-address instructions, such as IADD, are possible in conjunction
Instruction Formats
• Design Criteria for Instruction
with a stack.
Formats
• Expanding Opcodes • Infix notation → x + y
Addressing
• Addressing Modes • Postfix (or) Reverse Polish notation → x y +
• Immediate Addressing
• Direct Addressing • Reverse Polish notation has a number of advantages over infix for
• Register Addressing
• Register Indirect Addressing expressing algebraic formulas.
• Index Addressing
• Based-Indexed Addressing
❑ Any formula can be expressed without parentheses.
• Stack Addressing
• Evaluation of Reverse Polish
❑ It is convenient for evaluating formulas on computers with stacks.
Notation Formula
❑ Infix operators have precedence, which is arbitrary and undesirable.

Some examples of infix expressions and their reverse Polish notation equivalents.

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 EVALUATION OF REVERSE POLISH NOTATION FORMULAS

Instruction Set Architecture

Level • Reverse Polish notation is the ideal notation for evaluating formulas
Instruction Formats
• Design Criteria for Instruction
on a computer with a stack.
Formats
• Expanding Opcodes • The evaluation of (8 + 2 × 5 ) / ( 1 + 3 × 2 - 4) in IJVM
Addressing
• Addressing Modes
• The corresponding reverse Polish notation formula is
• Immediate Addressing
• Direct Addressing
825×+132×+4-/
• Register Addressing
• Register Indirect Addressing
• Index Addressing
• Based-Indexed Addressing
• Stack Addressing
• Evaluation of Reverse Polish
Notation Formula

Use of a stack to evaluate a reverse Polish notation formula.

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 REFERENCE

STRUCTURED COMPUTER ORGANIZATION

6th edition, PEARSON
Andrew S. Tanenbaum, Todd Austin.

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