th eC ear € DICA-LAB-MA. DEPARTMENT OF ECE Experiment No . tne: To wre a VHDL program for 3 wo $ Decoder and simulate by using XILINX9.2 Soft SOFFWaRe, 1 WINX 93) 2.ISE Simulator iar IEEE se IEEE STD _LOGIC_L164ALL: se EEE STD_LOGIC_ARITHALL: use IEEE STD_LOGIC_UNSIGNED ALL centy del is Por (ea ia STD_LOGIC, xin STD_LOGIC_VECTOR (2 dovemo 0; ¥ out STD_LOGIC. VECTOR (7 downto 0) end dl: architecture Behavioral of dois be procewen) beria it en=1 then y. le ‘when °000"=>y-="00000001 when "001"=>y<="000000 0 when "010"=>y<="00N001 07 when “O11"=>3-="00001000 o> y.="0001 004" y=" 00100000 y=="01000000"; <=" 10000000" when others nul endif end process end Behavioral DIED LAB MANUAL DEPARTMENT OF ECE wise BLOCK DIAGRAM: %at BCC e Dic LABNARUAL DEPARTMENT OF ECE wise BLOCK DIAGRAM: RTL SCHEMATIC DIAGRAM: Dich LAB NANUAL DEPARTMENT OF ECE WBE3:10 PM 0.0KB/s Zi ( < DICA-LAB-MA.. Q & DEPARTMENT OF ECE ws ‘TRUTILTADLES eee w ve ops tststefeto}tetetoepote oe ae Tp peepee er pee rp po Pe pe Pe par pa fo fe TP Tee 7 tft eteftete obe 3. Creates VHDL. wae ie then, DEPARTMENT OF FCE wae (Tae now ep creaing heaC yea Died CAB NANUAL DEPARTMENT OF £cE wise 7URC aod € DICA-LAB-MA. DEPARTMENT OF ECE wise 8 to 3 Encoder (with and without priority) ABSTRACT: To study ani sinulate design of 8 to 3 Encoder (with and without pros) THEORY: 8 to 3 enceser has 8 inputs and only one opt base on he sect inputs 2) stress out one output 2, Pioty encoders are available im standard 1C form and the TT. TALSLAS ix an 40-3 bit pity encoder which has eight active LOW (logic "0" inputs and Provides «3-bit code of the highest ranked input tts utp PROCEDURE: {2 The to: encode Design is entered through VHDL {2 The dexign i simulated by applying tet vector- ENABLE. L, D_IN and o nput D-OUT. 12 After simulation obai the RTL, technology schematics and syahesis epee, 1 Implement the design by passing the deign by various stages by mapping. time analysis and bit stream, For locking the pine write UCP file before implementation nl guide the same though option set control fils, Output can be directly ‘ogrammed int targst device FPGA. ‘VHDL PROGRAM FOR 810 3 ENCODER (with out priority LIBRARY IEEE: IEEE STD_LOGIC_1164.ALL USE IFEE STD_LOGIC_ARITHLALL USE IEEE STD_LOGIC_UNSIGNED ALL ENTITY ENCODERS 3 1S, INSTD_LoaKc LIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0} [END ENCODERK 3; ARCHITECTURE ENCODER_ARCH OF ENCODERS. 3 1S BEGIN PROCESSCENABLE.L,D_IN) BEGIN Died LAB MANUAL DEPARTMENT OF ECE we 1 (ENABLE. L =") THEN Dour = "000" ELSE CASED INIS| WHEN *Do900001" > D_OUT <= "00" WHEN "10000010" > D_OUT <= "vorURC aod € DICA-LAB-MA. Dic TAB MANUAL DEPARTMENT OF ECE we 1 (ENABLE. L =") THEN Dour = "00" ELSE CASED INIS| \WHTEN *n0900001" => D_OUT <= "00" WHEN "10000010" => D_OUT <= "vor WHEN “vO.00100" => D_OUT <= "010" WHEN "0000 1000" =-D_OUT <= "01" WHEN “vo010000° => D_OUT <= "100" WHEN "v0100000" => D_OUT <= "10r WHEN "01000000" => D_OUT <= "10" WIEN "10000000" => D_OUT-<="111" WHEN OTHERS => NULL END CASE END, END PROCESS, END ENCODER_ARCH: LOGIC DIAGRAM: Dic LAB WANUAL D_DEPARTMENTOF ECE wise INTERNAL INGRAM,ERD LCBO) € DICA-LAB-MA. DEPARTMENT OF ECE wise INTERNAL DIAGRAM: ‘VHDL PROGRAM FOR 8 TO SENCODER (without prior nity V744148 is Port ( BILL: tn st [LL n selogic_vecto 7 downto 0} ALL: out std logic_sectr(? dowat £0.08 1: out sl opi) nd V7 148; Architecture beh ot VARS id Signal Et Signal I: sido ICD TAB NANDA DEPARTMENT OF ECE w Signal A: std_logic_vector2 downto 0) proces(ELLILLELEOGS.LA) ible feet rnp 7 downto 0at BCC e € DICA DEPARTMENT OF ECE wise le not ELL Kee not LL Foe! (0 then BOO 0 0p Heyl ten DEPARTMENT OF EE wise TRUTH TABL= ‘OUTPUTStC aod € DICA-LAB-MA. DEPARTMENT OF EcE wise TRUTH TABLE: ‘OUrPOTS NOL] GSE] EOL TP XR PRR Te xpx pa pat 7 yt TTX Tx Xpope eyo pelt XTX 5 TTT RRIF TTR TRAIT TTITTt TREE TTA TT TTT CO oe a TPT a aaa a End End loo End 0 _Le= not EO: GS Lens: AL net A End process End behaviors RESULT: DEPARTMENT OF ECE wise 8x1 Multiploxer-74151 and 1 x 4 De-multiplexer-74155 AIM: To waite a VHDL program for 8X1 Multiplexer and simulate it by using XILINX9 2 Som SOFTWARE: 1. WINX92i