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Module 2 - Quest Bank - BCS302

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33 views2 pages

Module 2 - Quest Bank - BCS302

Vvgjj

Uploaded by

varshinid418
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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MODULE 2

1.Differentiate Latches and Flip-Flops.

2. Explain the working of Four-bit adders using 4-full Adders

3. Implement Y (A, B, C, D) = ∑m (0, 1, 6, 7, 8, 9, 10, 11, 12, 14) using 16- to-1 multiplexer
and 8-to-1 multiplexer.

4. Explain different modelling styles used to write the code in VERILOG with an example.

5. Design a BCD-to-excess-3 code converter.

6. Define decoder. Describe the working principle of a 3:8 decoder. Draw the logic diagram
of the 3:8 decoder with enabled input. Realize the following Boolean expressions using a 3:8
decoder and multi-input OR gates: F1(A, B, C) = ∑ m(1, 3, 7) F2(A, B, C) = ∑m(2, 3, 5).

7.Explain data flow modelling in Verilog with Dataflow diagram.

8.Design a Ful Adder and Subtractor Circuit.

9.Design and Octal to binary Encoder.

10.Explain the working of Four-bit adders using 4 bit full adders.

11.Working of SR latch and Edge Triggered D Flip flop.

12. Explain the differences between Combinational and Sequential Circuits with
their block diagrams and examples.

13. What are decoders? Implement the following Boolean functions with a
decoder: F1(A,B,C) = ∑m(1, 3,4,7),
F1(A,B,C) = ∑m(1, 3,4,7),
F2(A,B,C) = ∑m(0,2,3,6) and
F3(A,B,C) = ∑m(2,3,6,7)
F3(A,B,C) = ∑m(2,3,6,7)

14.What are Multiplexers? Implement the Boolean function F(A,B,C,D) =


∑m(1,3,4,11,12,13,14,15) with a 8:1 MUX.

15. Define Encoder. Design a Four-input Priority Encoder.

16. Write the Verilog program to Implement Full Adder and Subtractor Circuits.
17. Write the Characteristic Table and Equations of SR, JK, D and T Flip Flops.
18.Implement Full adder circuit using 3:8 decoder.

19.With Truth table and K-map simplification, implement the full-adder with basic gates and
using two half adders an OR gate.

20.Design a carry lookahead generator.

21.Explain priority encoder.

∑m(1,3,4,11,12,13,14,15
) with a 8:1 MUX

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