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VLSI Training & Placements

ASIC DESIGN & VERIFICATION

Course Curriculum

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 COURSE MODULES

Module 1 Module 2
Advanced Digital Electronics RTL Design using Verilog HDL

Module 3 Module 4
SystemVerilog for Verification UVM for Verification

Module 5 Module 6
Perl Language for Scripting Design & Verification Projects
& Protocols

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 Demo Sessions - Introduction to VLSI Design
Overview of VLSI Design Flow
Frontend Domain vs Backend Domain
Discussion on Industry Requirements
FPGA vs ASIC vs SOC designs
Moore Law, Nano meter technology
Importance of Digital electronics
Introduction to RTL Design & Verification

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 Module 1 - Advanced Digital Logic Design
Digital Logic Design - All Basic topics
Logic gates, Boolean Algebra, K-maps
All type of Combinational logic circuits
All type of Sequential logic circuits
Shift Registers , Counters designs
FSMs and Its Application examples
Memories
Static Timing Analysis
CMOS Logic Design

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 Module 1 - Advanced Digital Logic Design

Glitches & Hazards

Interview Preparation
Regular Assignments
Mock tests
Interview Preparation

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 Module 2 - RTL Design using Verilog HDL
Language Introduction and Applications
Data types, Operators
All Description Styles – Theory explanation
Behavioral Modelling - Lab sessions
Dataflow Modelling - Lab sessions
Gate Level Modelling - Lab sessions
Switch Level Modelling - Lab sessions
Types of Procedural Statements
Types of Continuous Statements

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 Module 2 - RTL Design using Verilog HDL
Blocking and Non-Blocking Assignments - Lab Sessions
Introducing the Process of Synthesis
Coding RTL for Synthesis
Modelling of Combinational Circuits, Latches, Flipflop, Registers,
Counters
RTL Design FSMs & Memories
RTL Design and Verification of FIFO | RAM | ROM
Testbench concepts for Verification from Basics to PRO
Regular Assignments, Mock Tests
Interview Preparation
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 Module 3 - SystemVerilog for Verification
SystemVerilog Overview
Standard Data types & Literals & Operators
User-Defined Data types & Structures
Testbench Architecture & Connectivity
Testbench Components
Static, Dynamic, Associative Arrays
Queues
Tasks & Functions
Interfaces, Virtual Interface Verification Features
Clocking Blocks, Mod ports
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 Module 3 - SystemVerilog for Verification
Object Oriented Programming, Classes | Objects
Polymorphism and Virtuality
Inheritance, Encapsulation
Random Stimulus
Class-Based Random Stimulus
Systemverilog Coverage analysis
Code Coverage, Cross Coverage
Deep into Functional coverage
Toggle Coverage
Assertion Based Verification(ABV)
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 Module 3 - SystemVerilog for Verification
SystemVerilog Assertions
Direct Programming Interface(DPI)
Interprocess Synchronization
Testbench Components
Testbench Examples
Testplans, Testcases
All topics theory + Lab sessions
Regular assignments
Mock tests
Interview Preparation
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 Module 4 - UVM for Verification
Indepth of UVM in SOC | IP level Verification
Detailed explanation on UVC in SOC | IP Verification
Introduction to UVM, Features
Testbench Hierarchy, Components
UVM Sequence Item, Sequence, Sequencer
Configuration, UVM config_db
UVM Phases
UVM Driver
UVM Monitor
UVM Agent
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 Module 4 - UVM for Verification
UVM Scoreboard
UVM Environment
UVM Test
Creating all components in a flow
Understanding of UVM RAL Model
Deep into UVM TLM
Callback, Events
UVM Test
UVM Testbench Examples
UVM Testplan Creation
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 Module 4 - UVM for Verification
DTPs(Detailed Test Plan Explanation)
Testcase scenarios
Detailed feature wise test implementation
All topics theory + Lab sessions
Regular assignments
Mock tests
Interview Preparation

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 Module 5 - Scripting Language - Perl
Introduction to Linux Setup
Importance of Perl Scripting
How to run the commands
Idea on Coverage analysis
Upload and extract the coverage report
Walk through perl concepts
Coding standards
Importance of Regressions | How to Run the Regression
How to check test pass or fail in SOC | IP Level
Idea on debugging testcases, execution flow
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 Module 6 - Projects & Protocols
Project 1- UART Protocol - RTL Design Using Verilog HDL
Theory
Introduction to UART Protocol: Features and Applications
Functional Block Diagram of UART
Signal Definitions and Timing Diagram
Implementation
Transmitter Design: FSM Implementation, Baud Rate Generator
Receiver Design: FSM Implementation, Data Sampling
RTL Coding of UART Transmitter and Receiver
Testbench Creation and Simulation
Debugging and Waveform Analysis

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 Module 6 - Projects & Protocols
Project - 2 I2C Protocol Implementation and Verification
Theory
I2C Protocol Overview: Features, Signals, and Modes of
Operation
Multi-Master and Multi-Slave Configurations
Timing Diagram and Bit-Level Analysis
Implementation
RTL Design of I2C Controller
Writing Test Cases in SystemVerilog
Testbench Creation and Verification using SystemVerilog
Coverage Metrics and Analysis

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 Module 6 - Projects & Protocols
Protocols - AMBA Protocols (APB, AHB, AXI)
Theory
Deep Dive into AMBA Protocols: Overview and Features
Detailed Signal Features of APB, AHB, and AXI Protocols
Comparison and Use Cases in Industry
Functional Features of APB, AHB, AXI
Detailed understanding on Master & Slave transactions
Pipeline & Non-pipeline structure, Burst transfers
Out of order transaction features, Multiple outstanding etc..

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 Module 6 - Projects & Protocols
Project -3 AMBA Protocols (APB, AHB, AXI)
Implementation
APB Protocol: RTL Design and Verification using
SystemVerilog
AHB Protocol: RTL Design and UVM-Based Verification
AXI Protocol: Advanced RTL Design and UVM-Based
Verification
Developing Comprehensive Test Plans and Writing Test Cases
Debugging and Coverage Analysis for AMBA Protocols
Developing our own testcases & testplans

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 Module 6 - Projects & Protocols
3 Major Projects - Selective Projects

DMA Controller
Router
Digital Alarm, Traffic light controller
4 Port Calculator
RISC V Project
Advanced Protocols like PCIE | USB | Ethernet | DDR..

All Projects are implemented in RTL design & Verification using SV,
UVM

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 Why ProV Logic ?

Structured
Course Tool Access Lab Mock Interviews
Curriculum Sessions Resume guide

Best Live Sessions 1:1 Mentorship Placement

Doubt discussions Guaranteed

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 Excellence in World class
VLSI Training & Placements

Do follow for updates & enquires

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