SEMICONDUCTORS | AI | DESIGN | PACKAGING | MEMS | DISPLAYS

OCTOBER 2024

Semi-damascene
Metallization p. 28

How SiC is Conquering

E-mobility p. 34

Selecting an MES
Migration
Strategy p. 37

Maximizing the Value

of Wastewater p. 40

Ion Beam Technology

Enabling Mobile Communications p. 20

www.semiconductordigest.com
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 October 2024 | Volume 6 Number 7

FEATURES
20 ION BEAMS
Ion Beam Technology – Enabling the Ever-evolving
Mobile Communications Landscape
Ion beam technology ensures that today’s mobile networks
remain robust and efficient, paving the way for future
innovations in the ever-evolving landscape of mobile
communications. MANDY GEBHARDT, SCIA SYSTEMS
28 INTERCONNECTS
Semi-damascene Metallization: Inflection Point in
Back-end-of-line Processing?
When used in combination with a patternable metal such
as Ru, semi-damascene promises to be RC, area, cost and
power efficient – offering an interconnect scaling path.
COVER: Bosch has tailored its semiconductor ZSOLT TOKEI, IMEC FELLOW, AND PROGRAM DIRECTOR OF
development to the demands of the automotive NANO-INTERCONNECTS AT IMEC
industry (pg. 34). Source: Bosch.
34 MATERIALS

Columns
How Silicon Carbide Semiconductors Are Conquering
E-mobility
Bosch has tailored its semiconductor development to the
2 EDITORIAL demands of the automotive industry.
Natcast Launches NSTC 37 FACTORY INTEGRATION
Membership Program Selecting an MES Migration Strategy for
PETE SINGER, EDITOR-IN-CHIEF
Semiconductor Process Optimization
INDUSTRY OBSERVATIONS Migrating to a new MES platform can lower the total cost
47 Navigating the Complexities of of ownership of automation and production assets, increase
Semiconductor Supply Chains Amidst efficiency, revenue, and ultimately, profitability, safety and
M&A Surge, TAMMY MAX, DIRECTOR OF environmental sustainability. TOM BEDNARZ, SALES MANAGER
TECHNICAL CONTENT AT ACCURIS TECH EUROPE, CRITICAL MANUFACTURING
48 Managing the Impact of Semiconductor 40 WATER TREATMENT
Manufacturers’ Use of Freshwater, Maximizing the Value of Wastewater Generated During
VINCENT PUISOR, GLOBAL BUSINESS Semiconductor Fabrication
DEVELOPMENT DIRECTOR, WATER AND The semiconductor aims to reduce pollutants and
WASTEWATER AT SCHNEIDER ELECTRIC freshwater consumption, reuse water, and recycle resources.
52 Cracking the Chip Code to Meet AI’s ZHAOHUI YAN, GLOBAL MARKET SEGMENT LEAD FOR
Growing Demands, MOZ AHMED, EDGE MICROELECTRONICS AT DUPONT WATER SOLUTIONS
& EMBEDDED TECHNOLOGY SOLUTIONS
44 WORKFORCE DEVELOPMENT
MANAGER AT MOBICA
Solving the Skilled Tech Talent Gap

Departments By implementing strategic workforce management and

partnering with experienced experts, semiconductor
companies can effectively navigate the talent shortage, build
4 NEWS a sustainable workforce, and position themselves for long-
50 AD INDEX term success. CRAIG WALTERS, VICE PRESIDENT BUSINESS
PROCESS OUTSOURCING, SEMICONDUCTOR, KELLY
www.semiconductordigest.com Semiconductor Digest October 2024 | 1
Editorial
Natcast Launches NSTC
Membership Program
• Strengthening U.S. semiconductor leadership: Through

N
ATCAST, THE NON-PROFIT ENTITY DESIGNATED TO OPERATE THE
National Semiconductor Technology Center (NSTC) innovative and member-driven research initiatives, the NSTC
by the U.S. Department of Commerce, officially will address industry and academia’s most pressing semicon-
launched its Membership program in late September. ductor R&D challenges and extend U.S. leadership in founda-
NSTC members can benefit from dynamic and cross-sector tional technologies for future applications and industries.
collaboration; access to leading-edge R&D facilities; devel- • Reducing time from lab-to-fab: By providing members
opment of member-driven research agendas; unique oppor- access to collaborative opportunities and leading-edge facili-
tunities to research, prototype, and scale up semiconductor ties and capabilities, the NSTC will reduce the time and cost
technologies; and workforce best practices and initiatives to explore, prototype, and validate innovative semiconductor
developed through the NSTC Workforce Center of Excellence. designs and technology.
These resources, several of which are planned to become • Expanding the U.S. semiconductor workforce: Develop-
available throughout 2025, are aimed at reducing barriers for ing and distributing critical workforce and education pro-
members to bring new technologies from lab-to-fab as well as gramming and resources, the NSTC will support members
supporting member efforts to build and sustain a strong U.S. in expanding and sustaining a strong U.S. semiconductor
semiconductor workforce development ecosystem. workforce development ecosystem.
“As a public-private consortium, the NSTC represents a NSTC membership is offered in two categories, Core and
bold vision for U.S. semiconductor innovation,” said Deirdre Affiliate, tailored to support the needs of the broad semicon-
Hanford, Natcast CEO. “Today’s launch of the NSTC Mem- ductor ecosystem. Core membership is designed for entities
bership program is a critical step in our evolution as we can now that are directly involved in semiconductor technology
welcome and officially admit members into the consortium.” development of materials, tools, processes, design, package or
The NSTC represents the foundation for the next wave of systems. Affiliate membership is designed for organizations
technological breakthroughs, serving as the anchor institution that do not conduct semiconductor research but would like to
where we shape the future of semiconductor innovation,” said participate and contribute to the ecosystem in areas such as
Secretary of Commerce Gina Raimo. workforce, investments, consortia, or professional services.
The mission of the NSTC is to convene a diverse set of Learn more about the benefits of becoming an NSTC member
members from across the semiconductor ecosystem around and join the mission at natcast.org/NSTCmembership.
three shared and strategic goals: —Pete Singer, Editor-in-Chief

Kerry Hoffman, Publisher Dave Lammers, Contributing Editor

[email protected] [email protected]
978-580-4205
John Blyler, Contributing Editor
Pete Singer, Editor-in-Chief [email protected]
[email protected]
Dick James, Contributing Editor
978-470-1806 [email protected]

Shannon Davis, Web and News Editor Cindy Chamberlin, Art Director
[email protected]
Rich Mehta, Website Design

October 2024 VOL. 6 NO. 7 •

Semiconductor Digest ©2024
ISSN 2643-7058 (print) ISSN 2643-7074 (online).
Semiconductor Digest is published eight times a
For subscription information, please visit year by Gold Flag Media LLC, 58 Summer St.,
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2 | October 2024 Semiconductor Digest www.semiconductordigest.com
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news
First CHIPS
Commercial
Fabrication
Facilities Award
eBeam Initiative Survey Goes to Polar
Predicts Photomask Semiconductor
Market Growth and CHIPS Investment Expected to Nearly
Double U.S. Production Capacity of Sensor

Increasing Investments and Power Chips at Bloomington, Minnesota

Manufacturing Facility
The eBeam Initiative, a forum dedicated to the education and pro- The U.S. Department of Commerce
motion of new semiconductor manufacturing approaches based on announced its first award under the CHIPS
electron beam (eBeam) technologies, recently completed its 13th Incentives Program’s Funding Opportunity
annual eBeam Initiative Luminaries survey. Industry luminaries repre- for Commercial Fabrication Facilities of up
senting 49 companies from across the semiconductor ecosystem – in- to $123 million in direct funding to Polar
cluding photomasks, electronic design automation (EDA), chip design, Semiconductor. The award will expand and
equipment, materials, manufacturing and research – participated in this modernize the company’s manufacturing
year’s survey. facility in Bloomington, Minnesota. The
Department will distribute the funds based
on Polar’s completion of project milestones.

The investment will support Polar’s efforts

to almost double its U.S. production capacity
of sensor and power chips within two years.
This award catalyzes a total investment of
more than $525 million from private, state,
Participants in the 13th Annual eBeam Initiative Luminaries survey and federal sources to transform Polar from
predict increases in future equipment purchases for multi-beam mask a majority foreign-owned in-house manufac-
writing and mask inspection over the next three years. Source: eBeam turer to a majority U.S.-owned commercial
Initiative. foundry. Through Polar’s semiconductor
manufacturing operations, the Administra-
100 percent of survey respondents predict that mask revenues in 2024 tion’s investment is expected to create over
will increase (74 percent) or stay the same (26 percent) compared to 2023. 160 manufacturing and construction jobs in
Luminaries were also positive on future equipment purchases over the Minnesota.
next three years, with increases predicted for multi-beam mask writers Polar plans to:
(93%), mask inspection (85%) and laser mask writers (48%). In addition, • Double production capacity, ramping up
the percentage of luminaries that believe that fabs without EUV can reach from approximately 20,000 wafers per
5nm within 7 years has increased from 12 percent last year to 19 percent month to nearly 40,000 wafers per month
this year. • Upgrade and modernize its facility to be-
New questions were added to the Luminaries Continued on page 6 come globally competi- Continued on page 8

4 | October 2024 Semiconductor Digest www.semiconductordigest.com

news continued
Continued from page 5
• 55 percent say that some critical its 15th annual photomask meeting –
survey this year to gauge percep- layers of leading-edge nodes are demonstrating the continued strong
tions on EUV pellicles and high-NA using ILT today, up from 46 percent support across the semiconductor
stitching. 81 percent think that last year and 35 percent from two ecosystem for this collaborative forum,”
stitching for high-NA EUV masks years ago stated Aki Fujimura, CEO of D2S,
will require designers to be aware • Mask shop software infrastructure the managing company sponsor of
of the stitching boundaries during continues to remain the biggest the eBeam Initiative. “It’s truly an ex-
design. 33 percent believe that EUV concern in producing masks with citing time to be a part of the photomask
mask lifetime is at least 3x longer with curvilinear shapes industry, which has seen such strong
pellicles than without. • Predictions on deep learning growth in recent years – a testament
Additional Perceptions from the adoption have slipped a year, with to the amazing talent within the mask
Luminaries Survey (conducted in July 54 percent predicting that deep community, as well as to the industry’s
2024) learning will become a competitive growing importance in driving semi-
• 74 percent agree that curvilinear advantage for any step in the mask conductor innovation. It’s welcome
inverse lithography technology making process by 2025, compared news that the vast majority of partic-
(ILT) is useful for 193i for non- to 56 percent who said by 2024 in ipants in this year’s eBeam Initiative
EUV leading-edge nodes – with 29 last year’s survey Luminaries survey, who represent top
percent strongly agreeing with that “We look forward to an exciting business and technology experts in the
statement compared to 24 percent week at SPIE Photomask where industry, see this growth trend con-
last year the eBeam Initiative will be hosting tinuing in 2024.”

$400 Billion in 300mm Fab Equipment

Investment Planned Over Next Three Years
Global spending on 300mm fab Worldwide, 300mm fab equipment ramp of global 300mm fab equipment
equipment is expected to reach a spending is projected to grow by spending in 2025 sets the stage for a
record US$400 billion from 2025 to 4% to US$99.3 billion in 2024, and record-setting three-year period of
2027, SEMI highlighted in its quar- further increase by 24% to US$123.2 semiconductor manufacturing invest-
terly 300mm Fab Outlook Report to billion in 2025, surpassing the ments,” said Ajit Manocha, SEMI
2027 report. The robust spending is US$100 billion level for the first time. President and CEO. “The world’s
being driven by the regionalization of Spending is forecast to experience ubiquitous need for chips is boosting
semiconductor fabs and the increasing 11% growth to US$136.2 billion in spending on equipment for both
demand for artificial intelligence (AI) 2026 followed by a 3% increase to leading-edge technologies addressing
chips used in data centers and edge US$140.8 billion in 2027. AI applications and mature technol-
devices. “The magnitude of the expected ogies driven by automotive and IoT
applications.”

Regional growth
China is projected to maintain its
position as the top spending region on
300mm equipment globally until 2027,
investing over US$100 billion in the
next three years driven by its national
self-sufficiency policies. However,
spending is anticipated to gradually
decrease from a peak of US$45 billion
in 2024 to US$31 billion by 2027.
Korea is projected Continued on page 8

6 | October 2024 Semiconductor Digest www.semiconductordigest.com

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news continued
Continued from page 6 Segment growth during the same period, marking the
to rank second and invest US$81 Foundry equipment spending is pro- beginning of another segment growth
billion in the next three years to further jected to reach approximately US$230 cycle. Within Memory, investment in
its dominance in memory segments billion between 2025 and 2027, fueled DRAM-related equipment is projected
including DRAM, high-bandwidth by investments in sub-3nm cutting-edge to surpass US$75 billion, while in-
memory (HBM), and 3D NAND Flash. nodes as well as continued spending vestment in 3D NAND is expected to
Taiwan is forecast to spend US$75 on mature nodes. Investment in 2nm reach US$45 billion.
billion on 300mm equipment over the logic processes and development of key The Power-related segment ranks third,
next three years, ranking third as the technologies at 2nm, such as gate-all- with an expected investment of over
region’s chipmakers build some new around (GAA) transistor structure and US$30 billion over the next three years,
fabs overseas. Leading-edge logic below back-side power delivery technology, including around US$14 billion for
3nm is the primary driver of Taiwan fab is crucial to meet future high-perfor- compound semiconductor projects. The
investments. mance and energy-efficient computing Analog and Mixed-signal segment is
The Americas is projected to invest needs, particularly for AI applications. projected to reach US$23 billion during
US$63 billion from 2025 to 2027, while Cost-effective 22nm and 28nm pro- the same period followed by Opto/
Japan, Europe & Mideast, and SE Asia cesses are expected to see growth due Sensors at US$12.8 billion.
are expected to spend US$32 billion, to increasing demand for automotive Part of the SEMI Fab Forecast
US$27 billion, and US$13 billion, electronics and IoT applications. database, the SEMI 300mm Fab Outlook
respectively, over the three-year period. The Logic and Micro segment is Report to 2027 report lists 420 facil-
Notably, these regions are anticipated projected to spearhead the equipment ities and lines globally, including 79
to more than double their equipment spending expansion over the next high-probability facilities expected to
investment in 2027 compared to 2024 three years, with an anticipated total start operation during the four years be-
due to policy incentives earmarked investment of US$173 billion. Memory ginning in 2024. The report reflects 169
to alleviate concerns on the supply of comes in second, expected to con- updates and nine new fabs/lines projects
crucial semiconductors. tribute over US$120 billion in spending since its last publication in June 2024.

SEMI and IESA Join to Strengthen

Semiconductor Ecosystem
In a strategic move to further solidify the flagship event aimed at bringing Ajit Manocha, President and CEO,
India’s position in the global semicon- together global leaders, semiconductor SEMI, expressed his excitement
ductor value chain, SEMI®, the global industry experts, and key stakeholders about this milestone, stating, “India
industry association that connects the under the theme of “Shaping the Semi- holds immense potential in the semi-
semiconductor and electronics design conductor Future.” conductor space, and many global
and manufacturing value chain, has This unification is set to bolster companies are already exploring the
announced a strategic agreement India’s ambition to become a “Semicon- opportunities within the country’s
with the India Electronics and Semi- ductor Powerhouse” by advancing its semiconductor industry. This part-
conductor Association (IESA), the design and manufacturing ecosystem. nership will help SEMI grow a strong
leading industry body representing the Together, the associations will enhance presence in this critical emerging
electronics and semiconductor sectors domestic manufacturing in line with In- market and enable both organizations
in India. IESA will become part of dia’s “Make in India” initiative, support to identify tangible strategies that
the global SEMI family and represent workforce development, improve global leverage our combined strengths to
SEMI in India. IESA will continue to competitiveness, and foster greater enhance supply chain resilience.”
use its current brand while beginning to technological self-reliance. Additionally, Dr. Veerappan, Chairperson, and
implement SEMI’s processes and select SEMI members will now have direct Ashok Chandak, President, IESA,
initiatives. access to India’s growing semicon- emphasized the strategic significance
The announcement comes at a pivotal ductor market, tapping into new growth of the partnership, saying, “This
time, the start of SEMICON India 2024, opportunities. milestone is a major Continued on page 10

8 | October 2024 Semiconductor Digest www.semiconductordigest.com

DROWNING IN DATA?
VISUAL DATA SCIENCE CAN HELP

www.spotfire.com
news continued
Continued from page 4 Information and Broadcasting, saw elevated the forum with valuable
tive through economies of scale participation from over 100 industry insights, offering guidance to both
• Deliver cutting-edge semiconduc- leaders from SEMI member com- the government and industry on how
tor solutions to the U.S. automo- panies, with a significant participation to transform the current industry
tive, aerospace, defense, opto- of IESA members. Fourteen members momentum into sustained business
electronics, MEMS, and medical (CxOs) from SEMI and IESA engaged growth. SEMICON India 2024, with
device industries, and in an interactive discussion with the 250+ exhibitors, 650+ booths, 100+
• Create 160+ new jobs, strength- Hon’ble Prime Minister of India, global companies and 50+ CxOs
ening Polar’s commitment to its Mr. Narendra Modi, focusing on the in attendance 11-13th Sept 2024, is
community and driving economic fast-track development of the semi- shaping up to be the largest semicon-
growth in the State. conductor ecosystem. Global CxOs ductor event in India’s history.
“As a domestic U.S.-owned sensor
and advanced power semiconductor
merchant foundry, we will support
technology and design innovation,
protect intellectual property,
NY CREATES Receives
facilitate onshoring and technology
transfers, and provide efficient $4.7M NSF Grant to Launch
low- to high-volume manufacturing
with world-class quality,” said Surya Semiconductor Workforce
Iyer, President and Chief Operating
Officer of Polar Semiconductor. Development Program
The New York Center for Research, running in semiconductor careers.
Continued from page 8
Economic Advancement, Technology, EASEL will also provide similar
win for India, SEMI, and IESA. It Engineering, and Science (NY experiences to teachers and instructors
positions India to become a global CREATES) announced it has been to better prepare them to educate the
semiconductor powerhouse, accelerates awarded a $4.7 million grant from the nation’s semiconductor workforce.
economic growth, and fosters inno- National Science Foundation (NSF) to Senate Majority Leader Charles
vation. By combining our capabilities support the establishment of the Edu- Schumer said, “This $4.7 million from
with SEMI’s global standards, network, cation Alliance for Semiconductor Ex- my CHIPS & Science law will help
and resources, we are fortifying India’s periential Learning (EASEL) program. college students from across America
ambitions and attracting global part- This workforce development initiative come to Albany NanoTech to get
nerships and investments to scale up aims to help address the growing hands-on training and become the next
design, manufacturing, and production national demand for a skilled workforce generation of America’s semiconductor
capacities.” in the semiconductor industry, a critical workforce. It will bring together com-
This agreement will also pave the need highlighted by the U.S. CHIPS & munity colleges, including Onondaga
way for joint policy advocacy efforts, Science Act. Community College, who are launching
with IESA and SEMI working closely The U.S. CHIPS & Science Act, chip technician programs now and give
with both Central and State govern- a transformational investment in the them access to the most cutting-edge
ments to drive incentives for product nation’s semiconductor industry, will research facilities to get them ready
development and manufacturing, help create an estimated 280,000 jobs for good-paying jobs at companies like
leveraging key programs such as the across the computer chip industry, with Micron and GlobalFoundries.”
Production Linked Incentive (PLI) nearly half of those positions requiring Senator Kirsten Gillibrand said, “This
and Design Linked Incentive (DLI) skilled technicians. EASEL will play a is a long overdue investment in one of
models. pivotal role in filling these technician the Capital Region’s most important
The Semiconductor Executive positions by providing hands-on, bridges. I’m proud to have fought for
Forum, held on 10th Sept ahead of the immersive learning experiences for federal funding for this project and
SEMICON India event chaired by Mr. college students from across the U.S. will continue to fight for every dollar
Ashvini Vaishnaw, Hon’ble Minister at NY CREATES’ Albany NanoTech necessary to get this restoration done.”
for Railways, Electronics and IT and Complex to help them hit the ground “We are thrilled Continued on page 12

10 | October 2024 Semiconductor Digest www.semiconductordigest.com

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Continued from page 10

to receive this grant from the

NSF to further train a robust
semiconductor-focused work-
force,” said NY CREATES
President Dave Anderson.
“We look forward to engaging
with our industry partners,
including Micron and Global-
Foundries, as well as with
our initial cohort of aca-
demic institutions to connect
students with this program.
Providing them the vital skills
required to contribute to this
area of research, development,
and manufacturing is critically
important for New York State and the four core community colleges—Co- and faculty participants, providing
U.S., especially given the exciting lumbus State Community College, On- over 43,000 hours of immersive
promise of the U.S. CHIPS & Science ondaga Community College, LaGuardia experiential learning and 4,000 hours
Act which is already driving industry Community College, and Madison Area of faculty technical development.
expansion.” Technical College—and will expand to The project will leverage the unique
The EASEL program will bring include additional institutions across key capabilities of NY CREATES,
together a coalition of community semiconductor manufacturing regions in which operates the largest non-profit
colleges and leading U.S. semiconductor the U.S. 300mm semiconductor R&D facility
manufacturers to develop and implement Over the course of the four-year in North America, offering a com-
multi-modal experiential learning oppor- project, EASEL is expected to plete integrated circuit process flow
tunities. Initially, the alliance will include support up to 660 student learners down to the 5-7nm device node.

Jabil Expands Silicon Photonics Capabilities

Jabil Inc. today announced its con- wire bonding. These advancements development journeys, significantly
tinued investment in silicon photon- will support silicon photonics chip reducing the need for costly trial
ics-based products and capabilities packaging, particularly in high-speed and error in developing their own
to support the increasing demands of connectivity applications such as solutions from scratch,” said Matt
hyperscalers and next-wave cloud and co-packaged optics (CPO) and high- Crowley, Executive Vice President,
AI data center growth. The company speed on-board connections. By lever- Global Business Units.
is set to roll out additional capabil- aging Jabil’s expertise, customers can Jabil continues to pioneer indus-
ities at its Ottawa, Canada, site in benefit from enhanced performance try-first “silicon to solutions” manu-
the fourth calendar-year quarter of and reliability in their photonics solu- facturing approaches that improve the
2024 to support customers’ advanced tions, ultimately driving agility and scalability of current and next-gener-
photonics packaging new product scalability in their operations. ation photonics, including 800G and
introductions (NPIs). “The expansion of our Ottawa 1.6T. The company also continues
The new product introduction site is a game-changer for Jabil. to make investments in next-gener-
(NPI) line will feature innovative This facility will enable us to meet ation silicon photonic technologies
capabilities designed to assist pho- the growing demands for advanced beyond 800G and 1.6T to support AI
tonics customers quickly scale from photonics solutions tailored to AI and cloud computing, focusing on
proof of concept to mass production, and next-generation data centers. optimized performance and reduced
such as fluxless flip-chip, fiber Through our NPI capabilities, we can power consumption for modern data
attachment, precise die bonding, and assist customers in their own product centers.

12 | October 2024 Semiconductor Digest www.semiconductordigest.com

A New Spin on Inspection
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news continued

A New Ventilator-on-a-chip Model

to Study Lung Damage
In a new study, using a ventila- to disease or trauma, but it has been cyclic collapse and reopening of air
tor-on-a-chip model developed at The known for a long time that the me- sacs both led the barrier to become
Ohio State University, researchers found chanical forces exerted on the lungs also leaky, but the cells could recover more
that shear stress from the collapse and cause injury. The damage at the cellular quickly from overinflation than from
reopening of the air sacs is the most level can make the barrier between tiny the repetitive opening and closing of
injurious type of damage. air sacs and capillaries carrying blood air sacs.
This miniature “organ-on-a-chip” become leaky, leading to fluid buildup Englert said the collapse and re-
model simulates not only lung injury that interferes with oxygen getting to opening may be more problematic
during mechanical the lungs. because it makes fluid
ventilation, but also in the lungs move,
repair and recovery, exposing cells to high
in human-derived amounts of shear
cells in real time, stress.
said co-lead author “There really hasn’t
Samir Ghadiali, been a lot of data that
PhD, professor and could allow for the
chair of biomedical comparison of those
engineering at Ohio two injurious forces
State. in the same system,”
“The initial he said. “But now for
damage is purely the first time, we can
physical, but the use the same device
processes after that with the same cells
are biological in and induce both types
nature — and what of injury and see
we’re doing with this what happens. Our
device is coupling the data suggests neither
two,” Ghadiali said. one of them is good,
The team hopes the device will also Of particular value is the ventila- they’re both injurious, but that the col-
help in the hunt for therapies to address tor-on-a chip’s measurement of re- lapse and reopening seems to be more
ventilator-induced lung injury. al-time changes to cells that affect the severe and makes recovery harder.”
“This is an important advance in integrity of that barrier, enabled by an This finding was a demonstration
the field that will hopefully allow for a innovative approach: growing human of the model’s sophistication, Ghadiali
better understanding of how lung injury lung cells on a synthetic nanofiber said.
develops in mechanically ventilated membrane mimicking the complex “We knew for a long time that collapse
patients and identification of therapeutic lung matrix. It’s closer to the authentic and reopening is a pretty injurious force,
targets so that we can give drugs to ventilated lung microenvironment than but we never could measure it in real
prevent that kind of injury or treat it any similar lung chip systems to date, time,” he said. “Now that we know that
when it happens,” said co-lead author the researchers say. collapse and reopening injury happens
Joshua Englert, MD, associate professor The device measures the effects of much quicker and takes a long time to
of pulmonary, critical care and sleep three types of mechanical stress on the recover, we plan to use the ventilator on
medicine at The Ohio State University integrity of the barrier: lung cell stretch a chip to figure out how to prevent this
Wexner Medical Center. from overinflation, increased pressure injury and/or enhance the repair.”
The research was published recently on lung cells, and cyclical collapse and Next steps involve modeling diseases
in the journal Lab on a Chip. reopening of air sacs. such as pneumonia and traumatic
Ventilators save the lives of patients Experiments showed that overin- injuries experienced by ICU patients in
with severe respiratory problems related flation with a high volume of air and combination with mechanical action.

14 | October 2024 Semiconductor Digest www.semiconductordigest.com

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news continued

Record Semiconductor Revenue in 2Q24,

Despite Market Weakness
In a new analysis, Omdia reports that market would be far from reaching a with quarterly revenue now exceeding
total semiconductor revenue reached a new revenue high. Excluding NVIDIA’s $40 billion.
record high of $162.1 billion in 2Q24 , revenue, the record remains 4Q21 with Commenting on the latest industry
marking a 6.7% quarterly total revenue of $155.8 billion, while performance, Cliff
growth. This figure Leimbach, Principal
surpasses the previous Analyst, Omdia stated:
record set in 4Q21 by “The top semiconductor
approximately $500m. companies are growing
The record growth larger. The top ten
was largely driven by companies by revenue
NVIDIA, the industry’s now account for 64%
top revenue generator, of the total market in
which now has quarterly 2Q24, the highest share
semiconductor revenue on record and up seven
$18 billion higher than percentage points over
4Q21. the five-year average of
While 2Q24 set a new 57%. A comparison to
revenue record, not all the last record revenue
companies are bene- quarter in 4Q21 shows
Total semiconductor revenue
fitting. Although revenue that the market gains
for the semiconductor are being concentrated
market is $33 billion higher than a year 2Q24 revenue stands at $138.2 billion - among fewer companies. In 4Q21 the
ago, over 50% of the companies tracked over $17 billion lower. top ten held 57% of the revenue share.
recorded lower semiconductor revenue NVIDIA’s dominant position is “NVIDIA continues to expand
compared to a year ago. This shows that mainly due to AI demand, though its market share, now representing
the market’s revenue growth is not being other semiconductor segments are also 14.8% of the semiconductor market by
shared by half of the companies. Of the benefitting from AI growth. revenue, driven by strong AI demand.
125 companies tracked in both the record Memory firms are benefitting Intel, historically either the top or the
quarters of 4Q21 and 2Q24, more than from AI demand, particularly due to second largest company remains in
70% had lower semiconductor revenue in High-Bandwidth Memory (HBM) chips third place for the third consecutive
2Q24 than in 4Q21. that support AI processors. Addi- quarter. With a 7.5% share in 2Q24, this
NVIDIA’s revenue is now more than tionally, the memory market has seen marks Intel’s lowest market share since
four times greater than it was during an improved supply/demand balance, Omdia began tracking the semicon-
the semiconductor industry’s previous boosting other areas. Following a chal- ductor market, in 1Q02,” concludes
record in 4Q21. Without NVIDIA, the lenging 2023 the market has recovered, Leimbach.

SWAP Hub Team Awarded Project to Develop

High Power, High Frequency Power Converter
The Deptartment of Defense has an- awarded $5M in funding by the CHIPS radar power systems in critical defense
nounced that the Southwest Advanced and Science Act for a Multi-MHz, High applications.
Prototyping (SWAP) Hub based at Ar- Density, Ultra-fast RADAR Power Researchers at the SWAP Hub are
izona State University (ASU) has been Convert project that will advance developing a comprehensive suite of

16 | October 2024 Semiconductor Digest www.semiconductordigest.com

 news continued
technology innovations to unlock the
multi-megahertz promise of gallium
nitride (GaN) to achieve ultra-low size
and weight, high efficiency and order of
magnitude improvements in transient
response and power quality of power
conversion systems.
The project will specifically develop
a multi-megahertz, multi-kilowatt, high-
density ultra-fast radar power converter
that forms the heart of advanced radar
systems. The converters will use GaN-
based switching devices and lead to
dramatic performance improvements
including six times higher power
density, 50% lower losses and ultra-fast regional technology hubs. It connects DOD Microelectronics Commons
response times. It is being funded with the Southwest — the fastest-growing Hubs across the country dedicated
$4.97 million from the Department of and largest semiconductor cluster in to advancing technology for national
Defense in its first year. the United States with more than $100 security.
This is one of five project awards billion in private investment — to The radar power converter project
to the SWAP Hub, part of the CHIPS a growing network of defense and is led by ASU and includes partner
and Science Act-funded Microelec- electronics partners across the country. organizations Lockheed Martin Corp.,
tronics Commons, a network of The SWAP Hub is one of eight U.S. Sandia National Continued on page 18

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news continued
Laboratories, Infineon Technologies Ayyanar said the GaN devices mental conditions and technology
Americas Corp., and ThermAvant need to be robustly characterized for transition.
Technologies. their critical parasitics and long-term • ThermAvant will develop advanced
“This project has potential to enable reliability; active gate drive technology thermal management using its oscil-
increased system power within pre- and packaging need to be advanced lating heat pipe technology.
allocated volume and weight constraints, to efficiently drive the GaN devices at • ASU’s roles include development of
increasing mission capability,” said multi-megahertz frequencies; circuit advanced circuit topologies, adap-
Raja Ayyanar, leader of the project and topologies and control are needed to tive gate driver, high density planar
a professor of electrical, computer and support these frequencies, enable fast magnetics, high performance con-
energy engineering at ASU. response and minimize the volume- trol, converter design, fabrication
In addition to the partner dominant magnetics; low-loss, high and integration.
organizations, other collaborators at frequency magnetic core materials and ThermAvant Technologies is the
ASU are Bertan Bakkaloglu, professor planar designs must be advanced; and leading oscillating heat pipe provider,
of electrical, computer and energy new thermal management solutions primarily for larger-scale aerospace
engineering, Mike Ranjram, assistant will be critical to alleviate hot spot and U.S. defense platforms. Under
professor electrical, computer and temperatures and support the proposed the proposed workplan, novel small-
energy engineering and Ayan Mallik, extreme power densities of the new scale 3-D oscillating heat pipes will
assistant professor at ASU’s Polytechnic devices. be demonstrated to manage the high
School. Each partner organization will bring power-densities and unique packaging
Infineon Technologies Americas specific, yet complimentary expertise to requirements being developed by ASU
Corp., will supply state-of-the-art the project. and its partners, explained Joe Boswell,
GaN-based power devices which can • Infineon Technologies Americas co-founder and CEO of ThermAvant
operate at higher frequencies and higher Corp.’s roles include providing Technologies.
efficiencies compared to the incumbent advanced GaN devices, character- “This is an enormous opportunity for
silicon-based power devices, says ization for multi-MHz operation, oscillating heat pipes to be packaged
Sameh Khalil, senior principal engineer reliability testing and techno-eco- within advanced power converters to
at Infineon Technologies. “Infineon nomic analysis. thermally manage their power-dense
will also perform accelerated lifetime • Sandia’s roles include development components – and do so with minimal
tests and evaluate device robustness and of advanced magnetic materials and size, weight, and cost-or-complexity
reliability,” he added. components, heterogenous inte- when integrating into real-world radar
The superior performance gration and advanced packaging of systems,” Boswell said.
characteristics of the GaN devices is a power devices. “We are eager to pull together all of
key driver, but the other technologies • Lockheed Martin’s roles include de- the pieces of this project and are excited
are critical in enabling the proposed fining system specifications, design to get started on it to see where this
ultra-high switching frequency oversight, simulation, test execution technology advancement will lead to,”
operation of GaN devices. to applicable electrical/environ- Ayyanar added.

SEMI Consortium to Develop

Cybersecurity Strategy and Roadmap
Seeking to strengthen the semicon- partnered with the National Institute of According to research by the Identity
ductor industry’s resilience to cyber- Standards and Technology (NIST) to Theft Resource Center, cyberattacks rose
security threats, the global association develop a semiconductor manufacturing by 72 percentage points in 2023 over the
SEMI announced the creation of a stra- industry profile for NIST Cybersecurity previous all-time high in 2021. As semi-
tegic roadmap for cybersecurity imple- Framework 2.0 (CSF 2.0) that will serve conductor factories become increasingly
mentation throughout the industry. The as the foundation for the aforementioned connected and autonomous, the industry
SEMI Semiconductor Manufacturing roadmap. NIST plans to publish the must respond to the growing security vul-
Cybersecurity Consortium (SMCC) has profile in mid-2025. nerabilities associated with this next level

18 | October 2024 Semiconductor Digest www.semiconductordigest.com

 news continued
of digital reliance and align with broader Research. “This community profile Director for Technology Security at
government efforts to secure the building could allow us to better identify and ONCD, during the Global Executive
blocks of technologies vital to society. execute a path forward.” Cybersecurity Forum at SEMICON West
“Semiconductors are integral to In support of the 2023 National 2024. “This means we have both the
both national security and the global Cybersecurity Strategy’s strategic ob- power and the responsibility to shape it.
economy – we need to do everything jective to secure global supply chains The future of cyberspace where de-
in our power to protect the industry,” for information, communications and fenders have an inherent advantage over
said Cherilyn Pascoe, Director of the operational technology products and attackers starts with preparation, and that
National Cybersecurity Center of services, the White House Office of preparation must begin with securing the
Excellence (NCCoE) at NIST. “NIST is the National Cyber Director (ONCD) building blocks.”
pleased to partner with SEMI SMCC for included a Cybersecurity Framework Prior to completion, the community
the development and adoption of a NIST Profile as part of initiative 5.5.5 in the profile will open for public review and
Cybersecurity Framework 2.0 Profile National Cybersecurity Strategy Im- commentary in accordance with NIST’s
for Semiconductor Manufacturing. This plementation Plan Version 2. SMCC official process. The review period has
collaboration is important to identify recognized the need for a cyberse- yet to be announced. The community
and reduce cybersecurity challenges in curity community profile specific to profile is part of a broader NIST strategy
semiconductor manufacturing.” semiconductor manufacturing and to further standardize cybersecurity
“It’s important to recognize and worked with the federal government protocols for the semiconductor sector, in
address the unique cybersecurity to develop one. line with profiles for other industries.
challenges facing the semiconductor “Unlike air, space, land, and sea, “With the committed resources
industry,” said Jennifer Lynn, SMCC cyberspace is the only battle domain and support from NIST to support
Working Group Chair and Semicon- created entirely by human hands,” said SMCC working groups, we’ll be able
ductor Cybersecurity Lead at IBM Anjana Rajan, Assistant National Cyber to accelerate the Continued on page 50

   

     
    
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ION Beams

Ion Beam Technology — Enabling the

Ever-evolving Mobile Communications
Landscape
MANDY GEBHARDT, s c i a S y s t e m s

Ion beam technology ensures that today’s mobile networks

remain robust and efficient, paving the way for future innovations
in the ever-evolving landscape of mobile communications.
argon ions, is accelerated onto

M
OBILE COMMUNICATION
technology has revolu- a substrate (FIGURE 1).
tionized how we connect, The ions transfer their kinetic
interact, and conduct business. At the energy to the surface atoms,
heart of this revolution are frequency causing them to be ejected, thus
filters. These critical components removing the material. The
ensure signals’ proper transmission and ion beam is typically larger in
reception by isolating specific fre- diameter than the substrate size.
quency bands to minimize interference That ensures sufficient removal
and improve signal clarity. High-quality uniformity and throughput.
filters ensure better signal clarity, During milling, the wafer
reduce interference, and improve overall substrate can rotate for the best
network reliability. uniformity. Chemically reactive
Figure 1. Scheme of an IBE/IBM process that
Among the advanced techniques used gases can be added to enhance
uses a collimated beam of inert gas ions for
to produce high-quality high-frequency structuring or material removal. the etch rate.
filters, ion beam processing technology By varying the angle of
stands out due to its precision and ef- material from the surface and create incidence and the substrate rotation,
ficacy. High-frequency filters in mobile specific patterns or structures. The ion material removal can be adjusted
communication incorporate many beam process combines physical and precisely to achieve a perfect etching
layers of thin films composed of various chemical etching. Physical etching uses structure with superior homogeneity.
materials. The uniformity requirements the kinetic energy of fast
for each film layer are very high. The inert ions bombarding the
application of ion beam processing tech- surface to sputter, releasing
nology for trimming these films to the atoms from the target
required dimensions can significantly surface. That process works
enhance the performance of mobile on all materials facing the
communication systems. ion beam. Chemical etching
utilizes a chemical reaction
Ion beam etching overview between the reactive ions
Ion beam etching (IBE) - also known and the target surface. The
as ion beam milling (IBM) - is ideally reaction products must, Figure 2. Scheme of an IBT process; a focused broad
suited for precise surface processing. therefore, be volatile. ion beam raster scans across the wafer. The local
The technology uses a directed beam of A broad beam of posi- material removal is controlled by adjusting the dwell
high-energy ions to selectively remove tively charged ions, typically time.

20 | October 2024 Semiconductor Digest www.semiconductordigest.com

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www.semiconductordigest.com Semiconductor Digest October 2024 | 21
ION Beams

This allows for the creation of many processes powerful tools for precise An efficient signal transmission only
different geometries in a wide spectrum material processing in various fields, occurs if the signal frequency f matches
of processable materials. such as semiconductor and MEMS the resonance criteria
manufacturing, and materials science.
Ion beam trimming f = v0/Ȝ
Ion beam trimming (IBT) is a particular Surface acoustic wave devices
type of IBE that physically uses a small Modern mobile communications Thereby, v0 is the speed of the
beam of positively charged ions (e.g., depend increasingly on frequency acoustic surface wave propagation and
Ar+) to etch material from a substrate filters since more and more commu- is twice the distance between the comb
by ion bombardment (FIGURE 2). nication standards with often multiple structures of an IDT.
A beam width of typically 8-15 mm frequency bands have been established. Since the available frequency bands
(FWHM) ensures a sufficient lateral A huge part of these filters is realized used in telecommunications are
resolution and a high throughput. using the surface acoustic wave (SAW) limited, the 3G, 4G, and 5G standards
During trimming, a focused broad mechanism, which transports energy use carrier aggregation to increase the
ion beam moves in a meander-shaped through materials exhibiting elasticity data rate. That means parallel trans-
pattern across the substrate surface. by propagating acoustic waves confined mitting on multiple bands. To avoid
By altering the local dwell time, it is to the surface to a depth of about one interference between different bands
possible to precisely adjust the material wavelength. while using them in parallel, the spec-
thickness and, hence, device properties SAW filters have remarkable ef- ifications for bandwidth have become
like the frequency of acoustic filters. ficiency and strong suppression of tighter. That requires a growing
By introducing an additional reactive frequencies outside the transmission precision in the manufacturing of SAW
gas into the ion beam source, a re- bands. Thus, an extremely high Q filters on wafers and an additional tem-
active structuring of the surface – the factor, meaning the oscillating system, perature compensation layer, which is
so-called reactive ion beam trimming is remarkably under-damped. A SAW realized by a SiO2 coating on top of the
(RIBT) – is applied. filter consists of a piezoelectric sub- IDT (FIGURE 4), which also requires
strate, such as quartz, lithium tantalate superior uniformity.
Advantages of ion beam processes
Ion beam processes offer several ad-
vantages. They can be applied to almost
all materials. Ion beam machining is
always contactless and nondestructive
and does not create mechanical stress
on the substrate’s surface, thus avoiding Figure 4. Scheme of a typical TC SAW stack.
subsurface damage. The ion beam
current, energy, and etching rates can be (LiTaO3), or lithium niobate (LiNbO3), Thickness trimming
independently controlled, allowing for and two sets of interleaved metal for SAW devices
precise material removal and excellent electrodes called interdigital trans- A localized trimming process is
uniformity across the etched surface. ducers (IDTs) on top of the substrate necessary to improve the uniformity of
Furthermore, ion beam processes offer (FIGURE 3). Incoming electrical SAW devices and maintain a high yield
high resolution, making them suitable signals at the input transducer generate for mass production.
for detailed, intricate designs and acoustic waves due to the piezoelectric As with all ion beam processes,
sidewall shaping through simple sample effect. These waves propagate along the trimming occurs in a vacuum envi-
tilting. substrate surface and are reconverted at ronment with working pressures from
These advantages make ion beam the second transducer. 8 x 10-5 to 8 x 10-4 mbar. A focused
broad ion beam of Ar+ ions physically
etches the material from the wafer with
ion current densities up to 25 mA/cm².
The ion beam diameter is optimized to
ensure sufficient lateral resolution and
high throughput. The material ablating
Figure 3. Scheme of a basic SAW filter design. is done by a meander-shaped pattern

22 | October 2024 Semiconductor Digest www.semiconductordigest.com

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www.semiconductordigest.com Semiconductor Digest October 2024 | 23
ION Beams

etching removal based on the actual and Guided SAW devices

wanted frequency. The localized cor- on POI wafers
rection to the target dimension is carried With the evolution of the modern
out using an IBT process by altering the communication standard 5G, higher
local dwell time. frequencies are used for receiving and
In general, only an upward frequency sending. RF filters working at such
shift is possible. Therefore, thicker frequencies can be manufactured as a
layers are always applied during the so-called “guided SAW device.” This
preceding coating process. new class of devices utilizes a bonded
Ion beam trimming of a SAW device piezo layer on a standard silicon wafer,
without temperature compensation called a piezo on insulator (POI). The
causes etching of the metal electrodes filter device uses the same principle
and the substrate material. The resulting known from standard SAW filters.
sensitivity function (FIGURES 5 and Building a SAW device on a POI
6) is non-monotonous, arising from wafer involves guiding the acoustic
the etch-rate difference of the metal wave within the piezo layer. This results
electrode and the substrate. The range in a higher coupling factor K2 for larger
Figure 5. Frequency shift depending for a negative frequency shift can be bandwidth filters and built-in tem-
on the thickness change by ion beam
trimming.

movement across the substrate.

The dependency between frequency
shift and removal rate is determined by
test etching a wedge on a test wafer. The
frequency is then analyzed on the “real”
substrates using an external frequency Figure 7. Schematic of a guided SAW device.
prober. The measurement data is
exchanged via files and assigned to the extended by adjusting the process perature compensation for high band
respective substrate via unique wafer parameters. A minimum removal is density.
IDs. The required surface removal is required to generate higher positive Typically, POI wafers consist of two
determined by calculating the necessary frequency shifts. or three different functional layers
(FIGURE 7). Each layer’s thickness
must be adjusted to a specific value by
keeping the surface as flat as pos-
sible. The demand for layer thickness
homogeneity and target thickness
accuracy becomes stricter than methods
like grinding and chemical mechanical
polishing (CMP) can deliver. In this
case, IBT can drastically improve
surface uniformity and desired target
thickness accuracy. Removal up to 1
ȝPLVDGGUHVVHGZKLOHPDLQWDLQLQJORZ
surface roughness.
FIGURE 8 shows the results of a
typically trimmed POI wafer. The av-
erage thickness of 2450 nm was reduced
Figure 6. Pre- and post-frequency trimming of a SiO2 temperature compensation to a target value of 1600 nm, with the
film of a 100 mm wafer. The ion beam trimming process achieves an improvement standard deviation improving from 439
factor of 30. nm to 35 nm (13X improvement). The

24 | October 2024 Semiconductor Digest www.semiconductordigest.com

 ION Beams

Figure 8. Histogram and height profile of 100 mm POI wafer before and after ion beam trimming. The ion beam trimming
process achieves an improvement factor of 13.

thickness distribution after trimming is Bulk acoustic wave devices becomes advantageous against SAW
well centered around the target thickness. Since SAW devices are used pri- for frequencies above 2.4 GHz. The
Likewise, AFM images (FIGURE 9) marily at long wavelengths and devices are tiny and have excellent
of the wafer before and after the lower frequency ranges of mobile performance. Furthermore, pro-
trimming process show that the original communication, high-frequency duction costs have been reduced over
surface roughness was kept throughout filters increasingly apply the bulk the last few years.
the trimming procedure. acoustic wave (BAW) principle. BAW A BAW filter uses a piezoelectric

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ION Beams

frequency. The oscillator’s mass

load additionally influences the
frequency. Thus, mass load trimming
KHOSVWRLPSURYH\LHOGIXUWKHU
(FIGURE 13). By trimming the
acoustic mirror layers, additional
TXDOLW\IDFWRUVRIWKH5)GHYLFHFDQ
be optimized.

Trimming of XBAR components

)XUWKHUGHYLFHGHYHORSPHQWV
no longer establish entirely new
functional principles but optimize
existing solutions. One example
Figure 9. AFM images of a 100 mm POI wafer before and after ion beam trimming.
is XBAR components, which are
film commonly made of aluminum DILQDOGHYLFH\LHOGRIRQO\WR FXUUHQWO\XQGHUGHYHORSPHQW7KH
nitride, which is contacted by two Additional tuning steps, such as IBT, principle corresponds to a freely
electrodes. To generate an acoustic FDQW\SLFDOO\LPSURYHWKHOD\HUXQL- etched, guided SAW on the back.
resonator, the piezoelectric film’s IRUPLWLHVE\DIDFWRURIWR7KXV The fabrication itself is a man-
WKLFNQHVVPXVWPDWFKȜRIWKHZDYH- PRUHWKDQRIILQDOGHYLFH\LHOGV ageable challenge. Due to the lack of
length of the longitudinal acoustic FDQEHDFKLHYHG FIGURE 12). EDFNVLGHVXSSRUWVKHDUYLEUDWLRQV
ZDYH7KDWPHDQVWKHWKLFNQHVVLV IBT can be applied to each layer are now excited in the arrangement.
GHILQHGE\WKHDFRXVWLFYHORFLW\RIWKH in the BAW stack. Thickness ad- Using this principle, filtering fre-
piezo material and the target reso- justments of the AlN piezo layer are quencies in higher and higher GHz
nance frequency. most important because its thickness ranges is now possible.
Additionally, the resonator needs directly defines the resonance
to be acoustically isolated from
the substrate. There are two dif-
ferent types. Film bulk acoustic
UHVRQDWRU )%$5 GHYLFHVXVHD
FDYLW\EHWZHHQWKHVXEVWUDWHDQGWKH
resonator (FIGURE 10). Solidly
mounted resonators (SMRs), which
are shown in FIGURE 11, use an
DFRXVWLFPLUURUWRDFKLHYHLVRODWLRQ Figure 10. Scheme of a (thin)
from the substrate. The acoustic FBAR device.
PLUURULVPDGHRIDOWHUQDWLQJȜ
films with high and low acoustic im-
pedance. With typical materials like
silicon dioxide and tungsten, only
DIHZOD\HUVDUHQHHGHGWRDFKLHYH
excellent isolation.
7KHILQDOIUHTXHQF\RIHDFKGHYLFH
is adjusted by an additional mass load
on top, which is deposited on the top
electrode (e.g., silicon nitride).
The requirements for the layer
uniformity of each material, especially
the aluminum nitride (AlN) piezo layer,
Figure 11. Scheme of SMR.
DUHYHU\KLJK$UHDOLVWLFGHSRVLWLRQ
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26 | October 2024 Semiconductor Digest www.semiconductordigest.com

 ION Beams

Conclusion
As mobile networks continue to evolve
with the advent of 5G and beyond, the
demand for advanced frequency filters
will only increase. Ion beam processing
technology provides an ideal approach

Figure 13. Pre- and post-trim results on an AlN layer for a BAW filter. An
improvement factor of 41 could be achieved.

for the manufacture of high-quality innovations in the ever-evolving land-

high-frequency filters due to its scape of mobile communications.
Figure 12. Improved resonance frequency precision and efficacy. As a result,
due to IBT. The relative error before this technology meets the stringent About the Author
trimming was 0.35% and after trimming
demands of modern communication Mandy Gebhardt is head of marketing at
was 0.02%. This means an improvement
factor of 17. systems, paving the way for future scia Systems GmbH.
Interconnects

Semi-damascene Metallization: Inflection

Point in Back-end-of-line Processing?
ZSOLT TOKEI, i m e c f e l l o w , a n d p r o g r a m d i r e c t o r o f n a n o - i n t e r c o n n e c t s a t i m e c

When used in combination with a patternable metal such

as Ru, semi-damascene promises to be RC, area, cost and
power efficient — offering an interconnect scaling path.

schemes with better figures of merit at overfilled – meaning that the metal depo-

I
N 1997, THE INTRODUCTION OF CU DUAL-
damascene integration schemes tight metal pitches. sition continues until a layer of metal is
in the back-end-of-line (BEOL) After filing an initial patent in 2017, formed over the dielectric. This metal is
of logic and memory chips marked imec presented a new metallization layer is subsequently masked and etched
an inflection point in semiconductor concept to the semiconductor community to form the second interconnect layer,
history. Chip makers moved away in 2020 and named it ‘semi-damascene’ with lines orthogonal to the first layer.
from subtractive Al patterning to wet [1]. Just like the Al-based metallization, The value proposition of semi-dam-
processes like Cu electroplating and semi-damascene integration starts with ascene is promising. It can be regarded
chemical mechanical polishing (CMP). as a two-layer metallization module
This radical transition was needed to potentially expandable to multiple layers
cope with an increasing RC delay in – making it cost effective. The subtractive
Al-based interconnects, the result of an etch allows for higher metal line aspect
increasing resistance-capacitance (RC) ratios (ARs) than conventional Cu
product. Being cost-effective and ap- interconnects, improving the resistance.
plicable to multiple layers of the BEOL As for the dielectric, the metal lines can
stack, Cu dual-damascene was set to potentially be combined with airgaps in-
enable many subsequent generations of stead of low-k dielectric gap fill. Airgaps
logic and memory technologies. offer a lower dielectric constant, leading
But in a few years from now, the metal to smaller intra-level capacitance. Besides
pitches within the most critical BEOL being RC efficient, semi-damascene also
layers will drop below 20nm. When that Figure 1. Schematic representation eliminates the use of metal CMP, simpli-
happens, Cu dual-damascene, in turn, of imec’s semi-damascene flow: a) Ru fying the process flow and resulting in
will run out of steam. As shrinking metal etch (formation of the bottom local improved line height control. The use of
line dimensions approach Cu’s electron interconnect line (Mx)); b) dielectric gap refractory metals also presents benefits.
fill or airgap formation; c) via etch; and
mean free path, the RC delay will They have the promise to be used without
d) via fill and top line (Mx+1) formation
increase dramatically. In addition, Cu (pink = Ru; blue = low-k dielectric; green barrier layer, hence providing low via
metallization requires a barrier, a liner = hard mask). and line resistance. They are also more
and a cap layer to ensure good reliability resistant to electromigration and overall
and prevent Cu from out-diffusing into the direct patterning (or subtractive met- offer lower resistance than Cu at reduced
the dielectric. But these extra layers start allization) of the first local interconnect dimensions.
to consume a large share of the total metal layer, hence requiring a patternable
available line width, meaning that the metal such as W, Mo, Ru, etc. (FIGURE The industry’s response: a
precious conductive area cannot be fully 1). The via that connects with the next promising but disruptive
utilized by the interconnect metal itself. interconnect layer is then patterned in a technology
These issues force the chip industry single-damascene fashion: a hole etched Since imec introduced semi-damascene
to investigate alternative metallization into the dielectric is filled with metal and integration, multiple organizations

28 | October 2024 Semiconductor Digest www.semiconductordigest.com

 line AR ~2. For subsequent generations
the AR can be increased to 3 or 6 and
then combine into multiple local metal
layers. R&D evidence is growing that
semi-damascene is indeed a valid option,
offering an interconnect scaling path.
At the same time, there are question
marks. Industry is currently consid-
ering moving the first generation of
semi-damascene into development, the
phase before actual production. As with
Figure 2. The imec logic roadmap.

started to research similar new schemes,

and steady progress has been made
through simulations and experiments
[2-5]. Today, the very first step of the
scheme, i.e., the subtractive etch of the
first metal layer, has been successfully
demonstrated and reported at conferences
by multiple organizations. Experiments
have clearly shown that replacing Cu with
subtractively etched Ru in the first local Figure 3. The imec semi-damascene roadmap, introducing subsequent generation
interconnect layer can already provide a of semi-damascene with improved RC (HM = hard mask; DD = dual-damascene; SD =
much-wanted benefit, even at a modest semi-damascene).
Interconnects

any new technology, industry does not to increase the AR of the M0 inter- more research is needed to demonstrate
proceed overnight. Semi-damascene connect line to 3, which will further and mature the next generations of
integration disrupts the conventional lower the resistance, and combine the semi-damascene. The main challenges
technology for fabricating the BEOL. M0 with a barrierless via. As higher can be grouped around multi-layer
It requires new tools and materials, and ARs tend to increase the intra-level semi-damascene integration, increase of
perhaps some of the defect mechanisms capacitance, this generation needs the AR, and exploration of new metals
are not captured in the research phase. airgaps instead of low-k dielectric gap for generation five.
Such investments are of interest only if fill. Besides offering a lower dielectric Below is a grasp of recent progress
the technology can span several tech- constant, working with airgaps also reported by imec researchers. The
nology generations. While the first step avoids the ‘gap fill issue’: the challenge results are not only meant to fill in
with only one metal layer is adequately of filling narrow trenches with dielec- the remaining gaps. They also aim to
documented, the implementation of a trics in a uniform way. trigger the discussion and encourage
two-layer and even multi-layer inte- By adding a via and a second metal other research institutions to com-
gration scheme – where the capabilities layer in semi-damascene fashion, gen- plement imec’s research – to the benefit
and benefits of semi-damascene can eration three will see true semi-dam- of the entire ecosystem.
be fully exploited – is however less ascene integration of both the M0 Towards multi-layer integration
discussed. That’s why imec encourages and M2 local metal layers – the most schemes in advanced interconnect As
the R&D community to open the critical layers of the BEOL. The fourth already mentioned, semi-damascene is
discussion, help filling the remaining generation may see even more layers of in essence a two-metal-layer integration
‘gaps’ and share insights on multilayer semi-damascene. The AR will be grad-
integration at interconnect technology ually ramped up to 4, 5 and even more –
conferences. depending on what will be feasible. Up
to ~AR=6, when combined with airgap,
The imec interconnect roadmap: sufficient RC benefit over other options
introducing 5 generations is expected (FIGURE 3).
of semi-damascene On the longer term, call it generation
Imec proposes to gradually introduce five, imec envisions alternative metals
subsequent generations of semi-dama- to enter the semi-damascene roadmap.
scene. Insertion of the first generation Think about patternable binary or
is envisioned for the imec A10 or A7 ternary compounds with better figures
logic technology node, where the metal of merit than single metals at tight
pitch of the most critical interconnects interconnect pitches. Figure 4. Via resistance distribution
and cross-sectional TEMs for the three
becomes as tight as 18nm (FIGURE 2). As such, semi-damascene can
different FSAV options at 26nm metal
At that point in time, GAA nanosheet become the next inflection point for pitch.
integration is expected to be main- BEOL fabrication. It has an excellent
stream and CFETs will not yet be in value proposition, not only in terms scheme, potentially expandable to
place. Introducing semi-damascene will of resistance, capacitance, and area multiple layers. But process optimiza-
therefore be the only major change that consumption. Experiments and sim- tions for multilayer schemes are still
chip makers will have to cope with. ulations also point towards lower in their infancy. What is the best way
Imec proposes to introduce subtrac- power consumption and better thermal to implement them? Which litho and
tively etched Ru in M0, the first local properties than Cu dual-damascene etch processes, hard masks and resists
metal layer that follows the middle of schemes. At the same time, the stepwise should be used? And how to integrate
line (MOL). This first generation will implementation as outlined above will the vias that connect the extremely
come with a metal line AR 2, which is allow to minimize the risks always narrow interconnect lines of subsequent
slightly higher than today’s typical Cu associated with the introduction of a BEOL layers?
line AR (~1.6). In combination with the new technology. To address the last question, imec
favourable behaviour of barrier-less Ru earlier proposed the fully self-aligned
at tight metal pitches, this approach will Enabling advanced generations via (FSAV) as a key building block to
already give a resistance and reliability of semi-damascene semi-damascene [6]. FSAVs ensure a
benefit over Cu. While generation one and two are proper alignment of the lines and via
In the second generation, imec aims ready to enter the development phase, (at both via top and bottom), which is

30 | October 2024 Semiconductor Digest www.semiconductordigest.com

 Interconnects

demonstrated is limited. Hence, imec

encourages other organizations to com-
plement the puzzle, and let the industry
ecosystem ‘decide’ on the best option
forward.
Incrementally increasing the aspect
ratio of semi-damascene lines: under-
standing and mitigating the roadblocks
A continued decrease of the resistance of
Ru semi-damascene lines is possible by
further increasing their AR. In 2022, imec
Figure 5. Via resistance distribution for overlay across the MX line, showing
overlay margin. In the 3D cartoons, an overlay shift of ~7nm is shown for the three showed first evidence that implementing
FSAV options. semi-damascene with AR 6 (FIGURE

crucial to enable low via-to-line leakage. So

far, several integration schemes for the FSAV
have been presented by multiple research
organisations, including imec.
At IITC 2024, imec was the first to
benchmark different FSAV integration options
(FIGURE 4), aiming to explore how the
FSAV can be best implemented in the 300mm
fab [7]. In other words: how can we meet the
Figure 6. Towards higher AR metal lines.
target via resistance with optimal via-to-line
overlay, and at the same time ensure low
variability and good reproducibility across the 300mm wafer?
Besides the conventional single-damascene scheme (FSAV)

efficient.
to create the via (meaning that the via is created by etching
a hole in a SiO2 dielectric which is then filled with metal),
imec explored two pillar-based FSAV integration schemes
(meaning that the via is formed as a pillar by direct etch of a
metal layer). The two variants are referred to as ‘hybrid pillar’ Simple replacement of Kr+ gas laser
(HP-FSAV) and ‘pillar with an etch stop layer’ (PE-FSAV).
The three integration schemes differ in number of process
steps, and in patterning and etch processes being used, in
hard mask integration and type of resist (e.g., allowing EUV
lithography tone inversion for enabling the pillars). But for
all three cases, the feasibility of reaching target via resistance
and via-to-line overlay margin was showcased (FIGURE
5). The most notable difference is related to the resistance
uniformity achieved across the wafer. All integration schemes TopWave 405 – 1 Watt @ 405 nm
provide sufficient via litho and etch process windows. High coherence diode laser for
Therefore, they are compatible with the direct metal etching lithography and holography
equipment currently available through our tool suppliers.
Other work by imec shows that the self-aligned window • Low cost of operation
• 1 Watt @ 405 nm
also exists for implementing airgaps, which will be needed
• Excellent beam quality, typical M² = 1.15
to continue the capacitance benefit when line ARs increase
further [8].
The status today hence proves that technically viable
options are available to implement at least two layers of
semi-damascene. At the same time the number of wafers

www.semiconductordigest.com
Interconnects

6) can indeed substantially improve lateral attack and line-break formation identified for benchmarking against
the RC metric over lower AR schemes during direct metal etch compared to Cu: the compound’s cohesive energy
[9]. Shortly after, initial experiments stacks without this extra layer. The key and the product of the bulk resistivity
indicated that high-AR lines are also benefit of this ‘defect mitigation layer’ and the mean free path of the carriers.
compatible with multilayer schemes [10]. is that it enables low-defectivity lines Ab-initio simulations revealed a sub-list
While the formation of interconnect of high AR and long lengths, which of candidates, including for example
lines with modest ARs (2 and 3) is LVDSURPLVLQJUHVXOWWRZDUGV$5• intermetallic aluminides, the starting
relatively well understood, increasing Ru semi-damascene. The results were point for further experimental work.
the AR while preserving good line presented at the 2024 VLSI Symposium Today, research groups worldwide
resistance and reliability requires some [12]. The experimental work showed investigate how the resistivity of these
technical mastery. It has shown to good reliability behavior of lines down candidate alloys behaves at reduced
challenge almost every process step – to 24nm pitch (FIGURE 7). But, at dimensions. For example, when inter-
including patterning and etch, cleaning, the same time more work is needed to metallic aluminides are deposited in
and defect control. For example, the optimize and extend the results towards thin films, defect mechanisms involved
direct metal etch ‘attacks’ the sidewalls 18nm pitch, show compatibility with in thin film formation seem to affect
of the Ru lines, leading to line-break de- integrating airgaps and demonstrate the resistivity behavior (FIGURE 8).
fects. And this worsens with increasing sufficient time-dependent dielectric Understanding that correlation will be
AR. Obtaining the lowest possible line breakdown (TDDB) and mechanical key to control the resistance. Imec also
resistance necessitates a more funda- reliability margin. identified global and local composition
mental understanding of the high-AR Advanced interconnects: the quest control as an important knob towards
line formation and reliability. for alternative conductors The work minimizing the resistance. [14]
As a first important insight, researchers on semi-damascene integration so far Once ways are found to optimize
at imec found that the composition of the focused on using Ru as the conductor of the resistance of promising binary and
stack used to form the high-AR metal choice. Several years ago, imec began ternary alloys, the next step is to im-
lines strongly influences the resistance investigating whether there are other plement them in relevant metallization
of the semi-damascene lines. Line break metals with even better prospects. The schemes and address the challenges
defectivity was shown to be the main search expanded from
contributor to the stack-dependent device elemental metals towards
performance. Imec, through multiple binary and ternary
experiments, found an optimal stack, ordered compounds
which starts with depositing 1nm TiN [13]. After a promising
for improved adhesion, followed by preliminary study, several
physical vapor deposited (PVD) Ru. R&D groups worldwide
Compared to other compositions used in started to embrace the
the study, this stack offered the lowest idea and joined the search
resistance over the entire height of the for candidate alloys. The
metal line. Second, the study provided community recently
a first indication that the line defectivity gathered at the VLSI
is influenced by the grain structure and 2024 thematic workshop
crystal orientation of the Ru metal grains. on ‘Novel metals for
Figure 7. Resistance yield of AR 6 lines at various metal
These morphological parameters strongly advanced interconnects’. pitches (18-26nm) for cases with and without defect
depend on the method used for depositing This workshop was orga- mitigation layer (DML).
Ru, favoring the use of PVD. [11] nized by imec to discuss
Besides gaining insights in the param- the state of the art and future research related to semi-damascene processing.
eters affecting the Ru line resistance, directions – from both industrial and Imec encourages universities and
imec recently came up with a unique academic perspective. research groups to collaboratively
approach to further improve the high-AR Since the list of potential alloys is explore patterning and etch strategies
lines from resistance and uniformity enormous, imec started its investigation and set up process directions. Although
point of view: sandwiching a sub-nm with setting up a unique methodology for much work remains to be done, research
TiN or W layer between two Ru layers. down-selecting and ranking the possible into alternative metals is a promising
This stack was found to be less prone to candidates. Two figures of merit were avenue, and steady progress is being

32 | October 2024 Semiconductor Digest www.semiconductordigest.com

 Interconnects

made. Intense collaborations will yet be

needed to eventually introduce them into gen-
eration five of semi-damascene integration.

Conclusion
Semi-damascene metallization may become
the next inflection point in BEOL fabri-
cation, with industry currently debating
about introducing subtractive etch in the first
local interconnect layer. Although not even
the first generation of semi-damascene is
in production today, based on experimental Figure 8. Example of the challenge posed by local composition control in
evidence, imec is already looking ahead to intermetallic aluminides. The atom probe tomography measurement (right)
newer generations of semi-damascene. The shows local composition fluctuations (blue = Al; green = Ni), affecting the
focus is on multiple metal layers and vias, a resistivity (left).
step-by-step increase of the aspect ratios, and About the author
the introduction of new metals. For these next generations to Zsolt Tokei is imec fellow, and program director of nano-inter-
become a reality, joint efforts and more data are needed with connects at imec. He joined imec in 1999 and,
strong input from academia and industry. since then, has held various technical positions
in the organization. He is working on a range of
REFERENCES
1. ‘Semidamascene interconnects for 2nm node and beyond,’ G. interconnect issues, including scaling, metal-
Murdoch et al., IEEE IITC 2020; lization, electrical characterization, module
2. ‘Subtractive Ru Interconnect Enabled by Novel Patterning integration, reliability, and system aspects.
Solution for EUV Double Patterning and Top Via with Embedded
Airgap Integration for Post Cu Interconnect Scaling,’ C. Penny et
al., IEDM 2022;
3. ‘Airgap Integration on Patterned Metal Lines for Advanced
Interconnect Performance Scaling,’ H.K. Chang et al., IEEE IITC 2023;
4. ‘A Novel Integration Scheme for Self-Aligned Ru Top via as Post-
Cu Alternative Metal Interconnects,’ K. Motoyama et al., IEEE IITC
2023;
5. ‘A Study of Resistivity Control for Subtractive Interconnects Using
Ruthenium,’ J. Rogers et al., IEEE IITC 2023;
thermcraftinc.com • (336) 784-4800
6. ‘First demonstration of two metal level semi-damascene
interconnects with fully self-aligned vias at 18MP,’ G. Murdoch et
al., VLSI 2022;
7. ‘Redefining 2-level semi-damascene interconnect technology:
benchmarking three different fully self-aligned via options,’ G.

Semiconductor
Marti et al., IEEE IITC 2024;
8. ‘Airgap integration in MP18 two-level semi-damascene
interconnects with fully self-aligned vias,’ G. Delie et al., IEEE IITC
2024;
9. ‘MP18-26 Ru direct-etch integration development with leakage
improvement and increased aspect ratio,’ A. Pokhrel et al., IEEE
IITC 2022;
HeatingElements
Thermcraft has been supplying
upp
upply
u plyyin
ply n high
ng hiigh qual
q
quality
uallity
ty
10. ‘Two-metal-level semi-damascene interconnect at metal pitch diffusion furnace heating
n
ng
18nm and aspect-ratio 6 routed using fully self-aligned via,’ A. elements to the
Gupta et al., IEDM 2023; semiconductor
11. ‘Impact of Ru deposition method and adhesion layer on electrical industry since 1976.
performance of semi-damascene interconnects,’ G. Delie et al.,
SSDM 2023;
Our high-performance
elements are designed
12. ‘Mitigating line-break defectivity with a sandwiched TiN or
W layer for metal pitch 18nm aspect ratio 6 semi-damascene for the most demanding n p
ng processes.
roc
ocesses.
cesses.
interconnects,’ A. Gupta et al., VLSI 2024; Whether used in annealing silicon wafers,
13. ‘Alternative metals: from ab initio screening to calibrated narrow silicon doping, or other semiconductor
line model’, C. Adelmann et al., IEEE IITC 2018; applications, we will provide a custom
14. ‘Optimizations on resistivity of binary compounds for advanced engineered solution to meet your needs.
interconnect metallization,’ J.-P. Soulié, SSDM 2023.

www.semiconductordigest.com
Materials

How Silicon Carbide Semiconductors

Are Conquering E-mobility
Bosch has tailored its semiconductor development to the
demands of the automotive industry.

The semiconductor manufacturer and au- can block higher voltages with lower on-

P
OWER ELECTRONICS ARE AT THE HEART OF
many electronic systems in tomotive expert Bosch has an optimistic state resistances, making them ideal for
battery-electric vehicles. Here, outlook on the future of silicon carbide. the high-voltage range. In addition, the
semiconductors manage the energy and Silicon carbide belongs to a class improved temperature stability ensures
ensure that it is utilized as efficiently as of materials known as wide bandgap that the semiconductor retains its per-
formance even at temperatures of up to
almost 400 degrees Fahrenheit. Another
key advantage of SiC is its higher charge
carrier mobility, which enables signifi-
cantly higher switching frequencies
compared to conventional silicon-based
solutions. Together, these benefits lead to
improved overall efficiency.

Why SiC is worthwhile

The main benefits of silicon carbide
vary depending on which vehicle com-
ponents the chips are used in. In electric
vehicles, SiC primarily enhances power
electronics, especially the inverter, the

Silicon carbide semiconductors in on-board chargers ensure more efficient

charging and lighter systems.

possible. MOSFETs (metal-oxide-semi- semiconductors. This wider bandgap

conductor field-effect transistors) made offers several advantages over silicon:
of silicon carbide (SiC) are renowned for thanks to the higher breakdown field
taking electromobility to new levels of strength, these special semiconductors
efficiency. While semiconductor tech-
nology is already widely used in some Bosch is systematically expanding
areas, its application is still in its early its manufacturing capacity for silicon
stages in certain automotive applications. carbide chips over the next few years.

34 | October 2024 Semiconductor Digest www.semiconductordigest.com

 Small chip with a big impact: the disadvantages,” explains Anne
semiconductors made of silicon
Bedacht, Head of Product Management
carbide have clear advantages over
conventional semiconductors in for Power Semiconductors at Bosch.
many applications. For her, efficient e-mobility is
therefore closely linked to SiC: “If you
semiconductors are more ex- look at the progress made in both SiC
pensive than comparable silicon and electric vehicles over the last ten
components. The production of to fifteen years, it’s undeniable and
silicon carbide boules requires continues to
very high temperatures – evolve.
around 3,600 degrees Silicon
Fahrenheit – and over
ten mask or structure
levels with more than
300 process steps are
needed before the raw
material turns into a
chip. As a result, the use of
DC/DC converter, and the on-board silicon carbide generally follows
Inverters with
charger. The use of SiC in the inverter a careful cost-benefit calculation. silicon carbide
enables higher efficiency, which Inverters based on silicon carbide semiconductors show their
increases the driving range. technology are therefore currently found advantages particularly in the high-
SiC MOSFETs have higher switching primarily in high-performance vehicles, voltage range.
transients than Si-IGBTs, allowing for where the benefits of SiC semicon-
quicker switching speeds. By increasing ductors are most obvious. “In smaller carbide chips have been conquering the
the switching speed, the overall market for several years, starting with
switching loss is reduced by around 50 the most profitable applications. As
percent. Additionally, SiC technology production scales up, the cost of these
enables higher switching frequencies, chips will eventually decrease – making
reaching up to 24 kHz. their use increasingly worthwhile across
The capability signifi- more vehicle components and models.”
cantly benefits DC/DC
converters and on-board Designed for electric driving
chargers by enabling more Bosch was an early adopter of SiC
compact and lightweight systems technology. The company began de-
with improved efficiency. Inverters veloping the first SiC semiconductors
equipped with SiC semiconductors The Bosch power module in 2001 and had the first MOSFET
enhance the overall efficiency of with silicon carbide semiconductors prototype available by 2011. From the
electric drives, reducing electrical offers high power density. very beginning, Bosch tailored
consumption (kWh per 100 km) in its semiconductor devel-
conjunction with other improvements electric vehicles, which often opment to the de-
in the overall system. This increases use 400-volt batteries, sili- mands of the
the range of electric vehicles or, in other con-based IGBT modules automotive
words, allows the battery capacity to be are still common in industry.
optimized based on the vehicle class and inverters. However, “Semicon-
application to save costs. in vehicles which ductors
are based in vehicles
SiC chips are conquering on 800-volt face entirely
the market technology, different conditions
Despite their numerous advantages, not the advantages of
all electric cars currently contain silicon silicon carbide in the Bosch has been producing MOSFETs
carbide chips. One reason is that SiC inverter clearly outweigh based on silicon carbide since 2001.

www.semiconductordigest.com Semiconductor Digest October 2024 | 35

Materials

existing production facility

in Reutlingen, where mass
production of SiC chips began
in 2021, and at the new wafer
fab in Roseville, California,
which is currently being
converted to silicon carbide.
In Reutlingen, Bosch is
already producing samples of
its first silicon carbide chips
on 200-millimeter wafers for
customer trials. The de-
livery volume is expected to
increase more than tenfold in
the coming years.* With the
new fab in Roseville, Bosch
will reinforce its global port-
Bosch’s wafer fab in Roseville, California: starting in 2026, the first silicon carbide chips will be folio of SiC chips. Starting in
produced in the United States on 200-millimeter wafers.
2026, the first silicon carbide
compared to stationary applications,” The future is all about chips will be produced in
explains Bedacht. “For example, the SiC for Bosch the United States on 200-millimeter
temperature fluctuations that a car is Bosch has positioned itself broadly wafers. “The automotive industry is a
exposed to put significant strain on the in the automotive industry and offers key player in driving the technology
electronics. In addition, we must deal SiC MOSFETS in multiple forms. The forward,” summarizes Bedacht. “With
with higher quality requirements. A company sells bare dies and discretes high production volumes, we will
car is in use for many years, and the directly to OEMs, to tier 1 and 2 achieve economies of scale, which
semiconductor’s lifespan must keep suppliers and to distributors, while also will reduce costs over time and extend
pace. Our chip designs reflect these implementing them in the benefits of silicon
demands.” its own modules and carbide to other applica-
One example is the design of the gate components. From tions.”
oxide in the trench MOSFET. Bosch Bosch’s point of view,
has developed its own manufacturing the two sales channels *The IPCEI ME/CT
process for SiC chips, adapting Bosch’s are by no means con- project is supported by
own trench etching technique. This tradictory, as Bedacht the German Federal
process, commonly referred to in explains: “On the Ministry for Economic
the industry as the “Bosch process”, contrary, both customer Affairs and Climate
was originally developed in 1994 for groups benefit from our Action on the basis
MEMS sensors. It enables high-pre- broad experience in the of a decision by the
cision vertical structures to be etched automotive industry. German Parliament,
Anne Bedacht, product
into the wafer material. Unlike the Many customers have by the Ministry for
manager for silicon carbide
conventional planar structure, the gate long relied on their own semiconductors at Bosch. Economic Affairs,
is vertical. The insulating oxide not designs and systems for Labor and Tourism of
only covers the surface of the chip but greater differentiation, Baden-Wuerttemberg
also protrudes into it. “This structure and we aim to support these OEMs based on a decision of the State
ensures higher power density while and tiers just as much as those who use Parliament of Baden-Wuerttemberg,
guaranteeing a long service life. This is complete modules and components that the Free State of Saxony on the basis of
important because the component will include our SiC semiconductors.” the budget adopted by the Saxon State
be exposed to high voltage for many For Bosch, the future is clearly Parliament, the Bavarian State Ministry
cumulative hours in the vehicle over centered around SiC. The company for Economic Affairs, Regional Devel-
the years,” the semiconductor expert is systematically expanding its opment and Energy, and funded by the
reports. production capacities – both at its European Union — NextGenerationEU.

36 | October 2024 Semiconductor Digest www.semiconductordigest.com

Factory Integration

Selecting an MES Migration Strategy for

Semiconductor Process Optimization
TOM BEDNARZ, S a l e s M a n a g e r T e c h E u r o p e , C r i t i c a l M a n u f a c t u r i n g

Migrating to a new MES platform can lower the total cost

of ownership of automation and production assets, increase
efficiency, revenue, and ultimately, profitability, safety and
environmental sustainability.
robust, cost-efficient platform while • Streamlined integration with en-

I
F YOU HAVE BEEN RUNNING A
semiconductor manufacturing also setting yourself up for valuable new terprise applications, such as ERP,
execution system (MES) for more capabilities. Here are just some of the SCM and PLM.
than 10 years, you already know well MES-enabling capabilities that have • Advanced machine learning and AI
the value of integrated, automated matured within the past decade: • Advanced simulation and modeling,
operations. And you likely know also • Integration with plant devices via digital twins
that MES and automation technol- IIoT • Personalization and customization
ogies have advanced significantly
over the past decade. Maintaining or
enhancing those benefits may require
migrating to a more modern system.
There is, however, more than one way
to approach migration, and getting the
maximum return on your investment
depends on selecting the strategy best
suited for your processes, your business
and your tolerance for risk. Here are
some important things to consider to
make your migration a success.

Why migrate?
Migrating to a new MES platform can
lower the total cost of ownership of au-
tomation and production assets, increase
efficiency, revenue, and ultimately,
profitability, safety and environmental
sustainability.
If your software is at the end of
its life and the vendor is phasing out
support, you will have little choice but
to migrate to a new platform. But even
if your ten-year-old system is not on its
last legs, there are still major benefits to
migrating to a modern system. You can
get your legacy functionality in a more

www.semiconductordigest.com Semiconductor Digest October 2024 | 37

Factory Integration

in both systems at the same time until

Table 1. Tradeoffs in common MES migration strategies
the new one passes readiness tests and
BIG BANG PHASED-IN PARALLEL becomes master, and you switch the
legacy system off.
RISK High Medium Low
EXECUTION TIME Fastest Longest Medium Managing the trade-offs
COST/EFFORT Lowest High Highest Each strategy has its tradeoffs though,
and which migration approach is best
• Flexibility and scalability Phasing in by operating unit involves for you depends on how you manage
• Advanced user interface introducing functional units slowly, tradeoffs among speed of implemen-
• Automated regulatory compliance and within this option, there are at tation, cost and risk. If, for example,
• Cybersecurity least also three approaches: phasing demand for your products is high, you
in area-by-area, process step by step, might optimize for speed-to-market
Migration options or machine by machine, as needed. more so than cost control but if you
Whether you get maximum benefit Regardless of which strategy you have excess unused production capacity
from your migration depends in part on choose, the new and old applications or inventory, cost cutting may be a more
choosing the migration strategy that is must be able to work interchangeably strategic immediate priority.
most compatible with your If you are migrating
needs. This usually involves from spreadsheets or from
making a strategic choice a standalone system that is
either to migrate everything not heavily integrated with
at once, in phases based on your legacy operations, the
production priorities or in big bang approach is likely
parallel. your best and probably only
Total “big bang” option. It is also the fastest
replacement model, often and lowest cost approach
called the big bang or because you don’t have to
rip-and-replace strategy deploy resources to im-
involves disconnecting plement the crossovers.
the legacy system and If your legacy MES is in-
replacing it with the new tegrated into the rest of your
one. After preparation and testing, with each other so that you can share enterprise or incorporated into existing
the migration team switches the and exchange data. automation sequences, and you want to
old system off and the new one on. Phasing in by MES function, such as optimize for speed and cost, a big bang
During the migration, the new MES SPC, recipe management or mainte- approach could be good for you as well,
and master data GUI will sit alongside nance management, requires co-exis- but it does come with high risk. There
the operations GUI. They connect tence between the legacy and new MES, is, for example, no easy way to test the
to the ERP, to other applications and but functional responsibilities would integration with real production data
to a reporting and analytics dataset. never overlap. And phasing in by lot and rolling back to previous function-
Synchronizing the legacy data will might involve upgrading all the modules ality is also challenging.
usually require application downtime, for the target product, running some on You can reduce that risk by going
file change configurations, and appli- the new platform and some on the old. with a phased-in or parallel approach.
cation startup procedures. Application Parallel Strategy While the above With a phased in approach, confidence
migration and process equipment in- phased-in approach may have some and expertise grow steadily as you
tegration happen after synchronizing phases running together, they would not complete each phase and because each
the operations data. typically run the same operations. In a phase is a mini migration unto itself,
Phased in migration strategy parallel migration strategy, however, you have more leeway to roll things
The phased in strategy involves both systems would be configured to back before moving on to the next
implementing new MES modules by run simultaneously and completely, with phase. This is especially true with
manufacturing operating units, MES the legacy system running as the master the parallel strategy, where you have
functions or lots. and the new one as the slave. Data sits virtually unlimited opportunities to

38 | October 2024 Semiconductor Digest www.semiconductordigest.com

 Factory Integration

roll back before switching over to the the migration. swapping out or adding modules.
new systems. But all this learning and The execution phase then covers all One note of caution – regardless of
rolling back takes time and resources, the activities to bring the migration to which strategy you choose, you may
so these approaches will extend com- life. It assumes that you have recon- be tempted along the way to add some
pletion time and increase costs. ciled downtime with production needs. custom touches maybe to preserve
It includes the roll-out and go live, some legacy functionality. This could,
Planning and implementation performance monitoring, phase-in and however, be a recipe for disaster.
The strategy that best matches your phase-out of manufacturing processes Whether you implement it via big bang,
needs, optimizing for cost, speed, and and ultimately, shutdown and removal phased-in, or parallel, the integrity of
risk reduction, depends on a thorough of the legacy system. The closure phase the new product must be preserved. You
upfront planning process, where you covers all post-migration close-down risk not only compatibility issues down
structure the definition, preparation, activities, such as archiving legacy the road, but also missing out on new
execution, and closure of your project. data and decommissioning unnec- functionality that could optimize your
In the definition stage you set the essary hardware. It may or may not processes in ways you hadn’t imagined.
project scope, target and execution include activities necessary to activate Having taken the time to select the
strategy, this is where you would new functionality from the new MES migration strategy that best fits your
commit to a big bang, phased parallel system. business strategy, and clearly articulated
approach. Next, during the preparation objectives, however, will help in both
phase you acquire and install and Adaptable MES the short and the long term.
configure system hardware and other It is quite possible that this may be the For more guidelines on planning
applications and set up development, last full-scale migration you will ever and implementing your migration see
staging and production environments. do. Given the increasing adoption of our white paper Guide to Successful
This is also where you configure, model interoperability standards and software MES Replacement. https://www.
and customize the new MES modules, development advancements tailoring criticalmanufacturing.com/insights/
train users, and adapt the related appli- to accommodate changing market white-papers/guide-to-successful-
cations and utilities needed to support dynamics could be simply a matter of mes-replacement/

www.semiconductordigest.com Semiconductor Digest October 2024 | 39

Water Treatment

Maximizing the Value of

Wastewater Generated During
Semiconductor Fabrication
ZHAOHUI YAN, G l o b a l M a r k e t S e g m e n t L e a d f o r M i c r o e l e c t r o n i c s a t
DuPont Water Solutions

The semiconductor aims to reduce pollutants and freshwater

consumption, reuse water, and recycle resources.

spotlight as water scarcity becomes an regulatory, and litigation risks.

W
ATER IS FUNDAMENTAL IN THE
manufacture of microelec- increasingly pressing issue. In addition “In the midst of increasing regional
tronics, with large volumes to sustainability considerations, water water scarcity and raw material costs,
of water required at every stage of stress can increase operating costs for we’re seeing end-users increase their
the fabrication process. As one of the foundries as they compete with local reclamation of wastewater for reuse
world’s most water-intensive industries, communities for local resources, plus back into their process streams—and
it is understandable why it is in the it may expose them to reputational, recycling other valuable resources

40 | October 2024 Semiconductor Digest www.semiconductordigest.com

 approximately 3.5 Kg NH4+, 1.0 Kg
TMAH, 50 g valuable metals, and 100 g
of silicon particles. This wastewater is
generated during many different front
and back-end process stages, with its
composition varying greatly, requiring
different treatment approaches for
maximum efficiency (FIGURE 1).
For example, TSMC classifies its
process wastewater [1] into 38 types
according to their composition and
concentration of specific compounds
(FIGURE 2). Low-concentration
wastewater most suitable for reuse is
Figure 1. divided into three categories which
directed wastewater streams for
through minimum or zero liquid dis- is now embracing the reclamation of treatment by nine recycling systems.
charge strategies,” said Veronica Garcia resources from wastewater as part of the
Molina, Global Marketing Leader, treatment processes that enable reuse. Treatment Technologies: The wide
Industrial Water & Energy at DuPont This shift reflects the general principle world of membrane filtration
Water Solutions. “We’re seeing a shift of 3Rs; reducing pollutants and fresh- and ion exchange resins
from reuse being viewed as aspirational water consumption, reusing water, and Membrane filtration is a flexible and
to something that is now necessary.” recycling resources. proven method for the concentration
The semiconductor industry is of liquids and separation of materials.
undergoing an evolutionary shift from The scale of the challenge This technological approach is often
simply striving to meet increasingly Producing a typical 12-inch wafer will faster and easier to manage than
stringent regulatory requirements on generate around 10 m3 of wastewater energy-intensive centrifugal separation
discharge, to reusing wastewater, and containing valuable minerals, including or evaporation solutions. The precise

Figure 2.

www.semiconductordigest.com Semiconductor Digest October 2024 | 41

Water Treatment

CLASS PORE SIZE EXAMPLE APPLICATIONS

• Concentration of NH4+ from the CWD and HFD streams
Reverse Osmosis (RO) < 0.001 µm
• Reduction of total dissolved solids (TDS)
• Recovery of fine silica particles following back-grinding or
chemical mechanical polishing
Ultrafiltration (UF) 0.01 – 0.1 µm
• Removal of small biological contaminants, including viruses,
colloids, proteins, and macromolecules.

streams to allow for the reclamation of

ammonia and associated by-products.
Meanwhile, the water purified during
the RO process can be demineralized by
an IX mixed-bed to produce pre-UPW
quality water for reuse (FIGURE 3).
Key considerations in specifying RO
membranes for this application:
• Requirement for high salt rejection
and durable chemical stability to
allow for the concentration of am-
monia up to 6,000ppm to allow for
its subsequent recycling.
Figure 3.
• High oxidation tolerance and resis-
nature of the separation is determined of IER; negatively charged cation resins tance to H2O2 and Fe are needed to
by the membrane’s chemistry: and positively charged anion resins. reduce fouling and extend mem-
• semi-permeable membranes rely on These respectively attract and exchange brane service lifetime.
a combination of size exclusion and positive and negatively charged ions. TMAH Used in the lithography
solution/diffusion permeation to IERs can be used as a pre-treatment process, wastewater streams with low
achieve separation. to remove hardness traces, protecting concentration of TMAH can use a com-
• microporous membranes can be used and increasing the recovery of down- bination of technologies to allow for the
to separate targeted components from stream RO units, or for the recovery recovery of this valuable material. Con-
a feed stream dependent on pressure of minerals including tetramethylam- created TMA can be extracted with the
and the target molecular weight. monium hydroxide (TMAH) and aid of cation resins before the remaining
It is certainly not a case of one copper (Cu). wastewater (now TMAH <10ppm) can
size fits all; there is a huge variety of be treated by RO to produce pure water
membranes available on the market, Recycling valuable by-products for reuse. The concentrated TMA can
developed for different industries, appli- as part of the wastewater then be recycled into TMAH and other
cations, and treatment approaches. The treatment process products with the aid of electrodialysis
different grades and properties of these Membranes and IERs can be combined (FIGURE 4).
membranes determine not just their effi- in multi-tech solutions for the recovery “While reclaiming end of pipe water
ciency and performance characteristics, of various valuable by-products is critical for future sustainable fab
but also their resistance to fouling. contained within wastewater streams, operation, treating discrete wastes
There are two different classes of allowing for their sale to material like TMAH, copper, and ammonium
membranes that are commonly used for processors for recycling. hydroxide can also harvest valuable
wastewater treatment and the recla- Ammonia A combination of uIt- raw materials instead of sending them
mation of resources in the microelec- rapure water (UPW) and ammonium to waste,” said Denise Haukkala,
tronics industry (Table 1). hydroxide (NH4OH) is used for wafer Technical Service Specialist at DuPont
Meanwhile, ion exchange resins cleaning, and the resulting caustic Water Solutions.
(IERs) are polymers with charged func- wastewater is unsuitable for discharge Key considerations in specifying
tional groups that can be used for the without treatment. The concentrated IERs for this application:
selective removal or exchange of ions NH4OH produced after treatment by • Due to high TMAH concentration in
in a liquid solution. There are two types RO can be combined with other waste feed water, high operating capacity

42 | October 2024 Semiconductor Digest www.semiconductordigest.com

 Water Treatment

adopt alongside complying with other

sustainability goals.
A membrane-based wastewater
treatment solution can achieve up to
a 95% recovery rate – minimal liquid
discharge (MLD) – reducing the volume
of water that may require additional
dewatering via thermal ZLD methods.
The water reclaimed through processing
can then be reused and this approach is
considerably more cost-effective than
conventional approaches.
Figure 4.
Upgrading existing water
is required to reduce regeneration January 2021, generating 30 metric reuse solutions
frequency tons of industrial-grade silicon With advancements in water treatment
• The swelling from H form to TMA products [2]. technologies, there are opportunities
form is approximately 160%, Key considerations in specifying UF for existing water reuse systems to
requiring resins with high physical membranes for this application: be upgraded to deliver improved
strength to reduce breakages • Membranes utilizing PES and PVDF performance; benefits aren’t restricted
Silicon Silicon particles gen- fibers offer fouling resistance which solely to new facilities. Often there are
erated in back grinding are cleaned is useful due to the fine silica parti- some quick wins that can be achieved
from wafers using ultra-pure water cles that need to be filtered from the by retrofitting existing infrastructure
(UPW). UF membranes can be used wastewater and with zero or minimal increase in
to concentrate silicon particles ahead • Poor selection could require the use physical footprint.
of their recycling for use in the steel of polymeric coagulants, increasing For example, a foundry was able to
industry. Avoiding the use of chem- chemical usage retrofit an existing standby RO unit
icals for silica extraction, allows for with upgraded membranes to allow RO
an RO polishing stage to remove any Multi-tech solutions to reduce brine from two existing wastewater
remaining contaminants before the energy and cost of MLD or ZLD reclamation systems to be recycled as
water is ready for reuse (FIGURE 5). Regulators are increasingly requiring makeup water for cooling towers [3].
This approach was pioneered by industry to minimize discharge By selecting low-energy membranes
TSMC, who launched a back grinding volumes, with some authorities even and using feed spacers to reduce energy
wastewater recycling system in its Ad- mandating zero liquid discharge consumption, the upgraded solution
vanced Backend Fab 3 in July 2020. (ZLD). Conventional thermal treatment avoided the need for costly and ener-
15,000 metric tons of back grinding solutions for ZLD are energy-in- gy-intensive booster pump upgrades.
wastewater had been processed by tensive and prove challenging to “Optimizing the RO elements for
existing assets or adding energy re-
covery devices can provide quick gains
on reliable operation and achieving
sustainability goals for energy,” added
Denise Haukkala. “Selecting a more
optimal reverse osmosis element can
help save energy, maintenance costs and
increase product lifespan.”
REFERENCES
1. https://esg.tsmc.com/en-US/file/public/e-
all_2023.pdf#page=116
2. https://esg.tsmc.com/en-US/articles/29
3. https://www.dupont.com/knowledge/
Figure 5. water-recycling-at-taiwanese-
semiconductor-plant.html

www.semiconductordigest.com Semiconductor Digest October 2024 | 43

Workforce Development

Solving the Skilled Tech Talent

Gap in the Semiconductor Industry
CRAIG WALTERS, V i c e P r e s i d e n t B u s i n e s s P r o c e s s
O u t s o u r cin g , S e mic o n d u c t o r, Ke l ly

By implementing strategic workforce

management and partnering with experienced
experts, semiconductor companies can
effectively navigate the talent shortage, build a
sustainable workforce, and position themselves
for long-term success

at the forefront of addressing

T
HE U.S. SEMICONDUCTOR INDUSTRY IS AT
a strategic crossroads. Despite this critical talent gap through
being a global technology leader, our expertly designed, custom
the U.S. currently manufactures only business process outsourcing
about 12 percent of the world’s semi- (BPO) solutions. the U.S. domestic semiconductor man-
conductors—not including the most ufacturing workforce has declined by
advanced types. The semiconductor talent challenge 43% since its peak in 2000, leaving the
Recognizing the strategic importance While the CHIPS and Science Act industry with a diminished talent pool.
of this sector, the U.S. government of 2022 represents a significant step Demanding jobs and lack of clear
took decisive action in August 2022 by toward revitalizing the U.S. semicon- pathways contribute to attrition The
signing the Creating Helpful Incentives ductor industry, it does not mitigate semiconductor industry is known for its
to Produce Semiconductors (CHIPS) and the pressing talent shortage facing demanding work environment—char-
Science Act into law. This legislation al- the sector. This challenge is rooted in acterized by long hours, high-pressure
located more than $75 billion to revitalize long-term trends and requires a multi- deadlines, and rapidly evolving technol-
American competitiveness in the industry faceted approach. ogies. These factors, coupled with a lack
and to limit the need for foreign suppliers. Decline in domestic manufacturing of clear career progression pathways in
While this opens up an amazing workforce According to McKinsey data, some companies, make the competition
potential for U.S. companies to take a
larger portion of the highly profitable
global semiconductor market (estimated
to reach $1 trillion by 2030) [1], there
is a significant shortage of skilled tech
talent. The gap between available posi-
tions and qualified workers is expected
to persist through 2030—threatening to
limit growth and innovation.
With nearly 80 years of experience
in workforce management and de-
cades of hands-on experience in the
semiconductor industry, Kelly® is

44 | October 2024 Semiconductor Digest www.semiconductordigest.com

 gap How can operations manager, and is currently a
the American senior operations manager. Rhonda has
semiconductor stated that she’s invigorated by being at
industry fully take the forefront of cutting-edge technology
advantage of funds and by the adventure that each new day
provided by the at work brings.
CHIPS and Science Identify entry points with potential
Act, with such a for growth This approach includes
considerable skilled recognizing the potential of roles that
tech talent gap? do not require a college degree. These
Staffing shortages accessible positions can serve as entry
on this scale put points for individuals to be nurtured
domestic objectives and developed into more advanced
for talent fierce and contribute to at risk. They can drive up labor costs roles over time—creating a pipeline for
employee attrition. and delay or diminish the return on future skilled workers in the industry.
Without well-defined career de- the monumental investments being
velopment plans, employees can feel made in the sector. A semiconductor spotlight on Matt
undervalued and uncertain about their Solving this problem requires a Matt, a former restaurant chef of 12
future within the company, leading significant change from the customary years, found his way to a career as a
them to seek opportunities elsewhere. strategies for cultivating, sourcing, and level one semiconductor technician with
Massive investments and job retaining talent. Kelly. Without an associate or bachelor’s
creation Public and private investments Outcome-driven workforce degree, he was looking for a foot in the
aimed at rapidly expanding the U.S. development Rather than waiting for door in a brand-new industry where his
semiconductor industry are projected to the marketplace to provide skilled finely honed soft skills would translate.
exceed $250 billion by 2032. This influx workers, companies can take an In his role with Kelly, he became a bay
of capital is expected to create more outcome-driven approach to work- captain, a shift lead, a supervisor, and
than 160,000 new jobs in engineering force development. This strategy an operations manager. After five years,
and technician roles, and additional begins with specific business goals. he was hired directly by the semicon-
positions in related construction fields. Management can then work backward ductor company—working today as
The growing talent gap The scale of from those outcomes to identify clear a group leader and a liaison for our
the skilled tech talent shortage becomes career pathways to develop workers on-site talent at the location.
apparent when comparing current grad- with targeted skills and training. Implement training and devel-
uation rates with projected demand. Using this strategy, businesses cir- opment programs Targeted training
Engineers: cumvent the talent shortage to create and development programs are critical
• Approximately 1,500 engineers a sustainable, competitive talent pool to the success of a workforce de-
join the semiconductor industry that supports long-term success in a velopment strategy. Companies can
annually. rapidly developing industry. nurture talent from within, reducing
• By 2029, the demand for semicon- reliance on external hiring for advanced
ductor engineers is forecast to reach A semiconductor roles. Clear career pathways reduce
88,000 workers. spotlight on Rhonda attrition and increase company loyalty.
Technicians: Rhonda, a current Kelly employee, was
• Only about 1,000 new technicians an underwriter trainer for a mortgage A semiconductor spotlight on Dan
enter the field each year. company. After four layoffs, she was Dan immigrated to the U.S. from
• By 2029, demand for these workers in search of a new career path. While Israel in 2012, working as a restaurant
is expected to rise to 75,000 workers. entering the semiconductor industry cook and in retail sales to improve his
According to McKinsey’s analysis, without experience felt intimidating English language skills. Seeking greater
the demand for talent is likely to far at first, she quickly realized she had stability and a consistent work schedule,
exceed available labor—even if nu- transferrable skills that allowed her he accepted a level one semiconductor
merous programs are designed to bridge to thrive and move up in the industry. role with Kelly. His commitment to
the gap in supply and achieve their She started as a level one technician, safety and quality, excellent reliability,
stated aims. and has ascended to a supervisor, an teamwork, and problem-solving
Bridging the semiconductor talent operations manager-in-training, an allowed him to advance to a leadership

www.semiconductordigest.com Semiconductor Digest October 2024 | 45

Workforce Development

role. Currently, Dan is an operations manufacturing leadership until his partner with skilled technicians during
manager for Kelly at the semiconductor company began downsizing. He tool installation projects, to field
company, where he enjoys the oppor- accepted a role as a level one semi- service engineers and supervisors.
tunity to learn and grow daily. conductor technician with Kelly. Rich This unmatched expertise allows us to
Upskilling: a key strategy for work- stood out due to his unique interest provide tailored workforce solutions
force development Upskilling programs in process improvements and team to the industry’s most competitive
can fundamentally change semicon- development, and quickly moved up semiconductor organizations—helping
ductor companies’ talent equation. The to a senior operations manager role. them to build a team of skilled
programs proactively enhance employee Throughout his five-year tenure with workers, well-trained on the company’s
performance by equipping them with Kelly, Rich has had a hand in hiring internal processes.
the latest skills and knowledge. They more than 450 technicians to support Comprehensive semiconductor
cultivate loyalty through clear career the semiconductor company. He cur- workforce solutions By implementing
pathways and improve productivity by rently oversees factory support opera- strategic workforce management and
ensuring employees are engaged and tions and the startup of
up-to-date in their knowledge. a new, remote branch.
Common upskilling programs include: Right talent, right
• Training courses jobs, right time In a
• Mentorship programs rapidly evolving and
• Tuition reimbursement highly competitive
• Job rotations industry, ensuring
• Technology access the right talent is in
Here are five benefits of using the right roles at the
upskilling to strategically and systemat- right time can make
ically develop existing talent: or break success.
1. Training existing employees can be However, finding,
more cost-effective than recruiting hiring, onboarding,
and onboarding new hires, especially and upskilling a large staff can be partnering with experienced experts,
for specialized roles. overwhelming for even the best in- semiconductor companies can effec-
2. By demonstrating their commitment ternal HR departments. Time spent on tively navigate the talent shortage,
to their workforce, companies reduce administrative tasks can detract from build a sustainable workforce, and
attrition and improve job satisfaction. the strategic workforce planning and position themselves for long-term
3. As employees gain new skills, they development initiatives that are critical success in this critical industry. The
become more efficient and effective for long-term success. key lies in working with a partner
in their roles, enhancing organiza- To effectively address the talent who understands how to identify and
tional productivity. shortage, companies need to ensure manage talent across all levels of
4. Upskilling ensures that the workforce they have the right talent available. This technical skills.
remains current with the latest indus- requires a nuanced understanding of the Partnering with Kelly delivers
try developments. skillsets required at each job level, from established BPO solutions, indus-
5. By developing employees’ skills, entry-level to highly specialized roles. try-specific expertise, and a proven
companies can prepare internal track record—allowing semicon-
candidates for future leadership roles, Turn to a BPO solution ductor companies to focus fully on
ensuring smooth transitions and This is where a business process innovation and core business objec-
knowledge retention. outsourcing (BPO) solution from Kelly tives, while ensuring their workforce
By prioritizing upskilling, semicon- becomes a game-changing advantage. needs are met with precision and
ductor companies can create a more With decades of experience providing efficiency.
resilient, adaptable, and skilled work- workforce solutions, Kelly is the leading To learn more, visit www.kellyser-
force capable of meeting the industry’s provider of skilled tech talent for the vices.us/semiconductor-digest/
evolving challenges. semiconductor industry.
REFERENCE
Our team has a deep understanding 1. https://www.mckinsey.com/industries/
A semiconductor spotlight on Rich of the skillsets required for each job semiconductors/our-insights/reimagining-
Rich was working in construction level—from safety mentors who labor-to-close-the-expanding-us-
semiconductor-talent-gap

46 | October 2024 Semiconductor Digest www.semiconductordigest.com

 Industry Obser vation

Navigating the Complexities of

Semiconductor Supply Chains
TAMMY MAX, D i r e c t o r o f T e c h n i c a l C o n t e n t a t A c c u r i s

— are usually communicated under their visibility and insights derived from AI

T
HE SEMICONDUCTOR INDUSTRY HAS
recently experienced widespread current identifier. The internal dynamics empower manufacturers and supply chain
consolidation through merger of companies, including their previous professionals to make more informed de-
and acquisition (M&A) activity. Over M&A history and the use of distributor cisions across their supply chain following
the past several years, there have been or legacy part numbers, compound the M&A activity, pinpointing any deviations
several notable semiconductor acqui- issue of proper identification.. This con- and resolving problems before they arise.
sitions, including Intel’s purchase of fusion may cause production line-down By analyzing historical data, schedules
Mobileye for $15.3 billion and Analog situations or could even force a redesign and sequences, AI can help design engi-
Devices’ acquisition of Linear Tech- in the middle of an electronics manu- neers and procurement teams anticipate
nology for $14.8 billion. factuer’s product lifecycle. demand fluctuations and potential supply
M&A can benefit companies and Electronicproduct manufacturers issues before they materialize, leading
investors in many ways, including can address these issues with best to proactive problem-solving rather than
reduced costs and increased effiencies, practices that capture manufacturer reactive crisis management. The latest
but it can pose significant challenges to and part-number changes over time. supply-chain AI tools can even help with
the supply chain. In an industry where For example, it’s often beneficial to auto-association of historical identifiers
supply-chain disruptions are already assign internal part numbers — which to current indentifiers. If a customer
common — mostly due to natural di- allows for more than one manufactuer uploads a BOM, for example, AI can
sasters, geopolitical tensions, and factory or part-number identifier for the same automatically match the current iden-
closures — M&A adds an extra layer of part — in internal systems such as tifier to the historical identifier, reducing
complexity. Electronic products man- PLM(product lifecycle management) duplication and confusion.
ufacturers, face production delays and platforms and product libraries. The technology can also be leveraged
shortages due to these industry shifts. In the past, not tracking part/man- to track PCN, processes product discon-
ufacturer changes over time required tinuance (PDN), and end of life (EOL)
Why does M&A cause significant manual work to assure PCN/ issuances from component manufac-
supply-chain disruptions? EOL notices were not missed due to turers, immediately notifying sup-
A product’s Bill of Materials (BOM) using legacy part numbers, and often ply-chain processionals of any changes,
doesn’t change. With M&A part numbers lead to duplication of part numbers and and offering insights on how and when
and manufacturer names do change. As missed opportunities to consolidate these should be addressed. Through
a result, semiconductor components im- volumes for purchasing power. the use of AI, supply chain teams can
pacted by M&A will have multiple iden- The good news is that artificial maintain healthy operations following
tifiers, including their original identity intelligence (AI) technology can help M&A and other disruptions.
and any subsequent post-acquisition combat these challenges and streamline As M&A reshapes the semiconductor
identities.. This can lead to confusion and the process of uncovering identity industry, supply chains need to adapt. AI
critical disruptions in a supply chain. discrepancies, preventing disruptions. offers solutions that streamline oper-
For example, obsolescence and ations, manage part duplications, and
product change notices (PCN) — the AI to the rescue improve visibility. By leveraging these
documents issued by manufacturers Over the past few years, AI tools have technologies, companies can navigate
to inform customers about changes captivated the attention of companies as challenges more effectively and maintain
to products or manufacturing process a way to save time and resources. The innovation in a changing market.

www.semiconductordigest.com Semiconductor Digest October 2024 | 47

 Industry Obser vation

Managing the Impact of

Semiconductor Manufacturers’
Use of Freshwater
VINCENT PUISOR, G l o b a l B u s i n e s s D e v e l o p m e n t D i r e c t o r , W a t e r a n d
Wastewater at Schneider Electric

Producing ultrapure water is typically process -which has the capability

T
HE UN PREDICTS THAT BY 2030 THERE
will be a 40% gap between 60 to 350 times more expensive than to reduce plant overall energy con-
global freshwater supply and producing drinking water, mainly due sumption by up to 20% and coagulant &
demand. Amid the escalating decline to the additional purification processes flocculant chemical usage by 5- 20% —
in freshwater availability, industry still and equipment required to remove vir- and it is clear that it is essential that the
accounts for a staggering 20% of global tually all contaminants. This cost is so semiconductor industry focuses efforts
freshwater withdrawals. high because of the energy consumption on the importance of smarter water use
The increased threat of water scarcity, and chemical usage that is needed for across their operations.
competition for water resources due to water treatment processes. With water So, what does this look like in
a growing global population, and new demand showing no signs of slowing practice?
regulations for wastewater discharge, down, it is crucial for manufacturers
has highlighted the urgent need to ad- to review operations now to optimize Creating a data-driven
dress inefficiencies across all industrial processes and reduce their water circular water economy
sectors. consumption. Today, data-driven industrial water
The semiconductor industry is no management technologies are revolu-
exception, with the chip manufacturing The operational case for tionizing how companies can approach
boom increasing water consumption enhanced circularity water management and sustainability.
by 20-30% in the last few years. Today, According to recent analysis from S&P Automation coupled with data and AI
the industry is on average using five Global, “water scarcity is a risk in the are playing a crucial role in enabling
times more water for chip production in coming decade for the tech hardware in- better management of resources,
comparison to ten years ago. In fact, a dustry, particularly the water-intensive optimizing treatment processes, and
single semiconductor fabrication plant semiconductor subsector. Mishandling improving operational efficiencies
can use up to 10 million gallons of of such a risk could hit a chipmaker’s supporting quicker and more precise
water per day, which is equivalent to the operations and creditworthiness.” decision-making than ever before.
daily water consumption of a city with a By 2030, 40% of chip production This is particularly true for industrial
population of 300,000, while an average facilities are predicted to be in high- water management solutions that are
chip manufacturing facility today can or extremely high-water-risk areas. layered with sensors, data, and cloud-
use 10 million gallons of ultrapure water Already many governments across the based platforms to optimize physical
per day—as much water as is used globe are increasing investments in water systems. The integration of
by 33,000 US households every day. domestic semiconductor manufacturing AI, Machine Learning (ML), Data
Furthermore, the demand for high- efforts to safeguard supplies while man- Analytics, Internet of Things (IoT),
quality ultrapure water (UPW) needed aging ESG concerns and environmental sensors, and digital twins provides a
for cleaning and cooling continues to impacts. huge volume of data insights that can be
rise, with the average chip manufac- Combine this threat with the ex- leveraged for quick analysis to measure
turing facility using 10 million gallons panding regulation to include zero water quality and make predictions
of UPW each day. liquid discharge (ZLD) treatment using demand forecasting.

48 | October 2024 Semiconductor Digest www.semiconductordigest.com

Industr y Obser vation Cont.

AI models can optimize processes in daily activities. Regulatory landscape

the semiconductor industry, addressing • Partner with experts and technol- The semiconductor industry is also
key challenges such as reducing energy ogy providers to design and im- subject to increasingly stringent regula-
consumption, improving chemical plement effective water circularity tions related to water use and discharge.
usage efficiency, and extending the solutions. Leveraging external ex- In the United States, the Environmental
lifespan of critical assets. AI models pertise can help identify innovative Protection Agency (EPA) has estab-
can optimize chemical use in wafer approaches and ensure the integra- lished the National Pollutant Discharge
fabrication, reducing waste and tion of new technologies. Elimination System (NPDES) permit
ensuring consistent quality. Energy • Continuously improve and inno- program, which regulates the dis-
optimization AI models can help vate, conducting periodic audits charge of pollutants into water bodies.
semiconductor manufacturers reduce to assess the effectiveness of water Semiconductor companies must obtain
energy consumption by up to 10% by circularity initiatives and make NPDES permits and comply with the
identifying efficiency improvement necessary adjustments to enhance specified limits on pollutant discharge.
opportunities. AI-driven predictive performance. In addition, some regions have imple-
maintenance can extend the lifespan
of critical assets, such as membranes
used in ultrapure water systems, by up Semiconductor companies must set clear
to 12 months, reducing replacement
costs and minimizing unscheduled
goals for reducing freshwater consumption
downtime. by enhancing efficiency and promoting
By leveraging AI-related solutions
and process optimization, water circularity within their operations.
producers will benefits from reduced
overall process energy consumption, • Taking collective action, extend- mented more stringent regulations, such
reduced chemical consumption and ing beyond the semiconductor fac- as California’s State Water Resources
reduced clean water consumption for tory boundaries to encourage your Control Board, which has set a goal of
CIP process. supply chain to reduce water im- reducing water use in the semiconductor
pacts, and partner with other actors industry by 25% by 2025. Companies
Getting started with water in water replenishment programs. that fail to comply with these regula-
circularity models • ESG funding and Green bonds, tions may face significant fines and
To maximize ROI for investments in which are are financial instruments reputational damage.
these technologies, semiconductor specifically designed to support
companies should: projects that have a positive envi- Looking ahead
• Measure water consumption, ronmental impact. Semiconductor Adopting water circularity practices
beginning with a comprehensive manufacturers, with their significant remains crucial for semiconductor man-
assessment of their manufacturing energy consumption and potential ufacturing to ensure a sustainable future.
facility’s water footprint and using environmental footprint, can be Implementation of automation alongside
smart meters and IoT sensors to eligible for such funding. advanced digital technologies can help
monitor water usage in real-time. • Water recycling and conserva- water-intensive industries root out waste,
As part of this, establish key perfor- tion: Implementing water recy- improve operational efficiencies, and
mance indicators to track progress cling systems and reducing water reshape operational processes for more
and identify areas for improvement, consumption. sustainable water management.
as well as reducing waste and im- • Renewable energy adoption: In- Ultimately, the cost of doing
proving water conservation. vesting in renewable energy sources nothing far outweighs the cost of
• Educate and train employees about to power manufacturing operations. taking action. Semiconductor com-
the importance of water conservation By leveraging ESG funding and panies that prioritize water sustain-
and circularity to foster a collective green loans, semiconductor manu- ability will not only contribute to the
culture of sustainability. Companies facturers can accelerate their transi- preservation of this vital resource but
can do this by providing training tion to more sustainable operations also position themselves for long-term
on best practices for reducing water while benefiting from financial success in an increasingly water-con-
waste and optimizing water use in advantages and improved reputation. strained world.

www.semiconductordigest.com Semiconductor Digest October 2024 | 49

news continued
Continued from page 19 recommendations for semiconductor by leveraging the program’s 50-year
development of this semiconductor manufacturing equipment, information history of industry alignment. SMCC is
manufacturing industry community on implementation, and updates on the currently working on developments to
profile creation,” said Brian Korn, development of the community profile. two cybersecurity standards:
Director for SMCC and Staff Technol- SMCC working groups are engaged • E187: Specification for Cybersecuri-
ogist focused on Cybersecurity and with the SEMI Standards program to ty of Fab Equipment
Automation at Intel Foundry. create a standards-based approach sup- • E188: Specification for Mal-
SMCC will provide cybersecurity porting the semiconductor ecosystem ware-Free Equipment Integration

Renesas Intros 4th-Generation

R-Car Automotive SoCs
Renesas Electronics Corporation exceptional TOPS/W performance and ADAS applications such as front
expanded its R-Car Family of sys- power-optimized features make them smart camera systems, surround-view
tem-on-chips (SoCs) for entry-level ideal for entry-level, cost-sensitive systems, automatic parking and driver
Advanced Driver monitoring systems.
Assistance Systems Based on the same
(ADAS). The new advanced 7-nm manufac-
devices, the R-Car V4M turing process technology
series and the expansion as the powerful R-Car
of the existing R-Car V4H series, the new R-Car
V4H series, deliver V4M series delivers deep
robust AI processing learning performance of
capability and fast CPU up to 17 TOPS and boasts
performance, while high-speed image pro-
carefully balancing cessing and precise object
performance and power recognition using on-
consumption. Their board cameras, radar and

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50 | October 2024 Semiconductor Digest www.semiconductordigest.com

 news continued
embedded processor solu-
tions for all vehicle classes
— from entry-level to
luxury-class models — all
under a single development
platform.”
The R-Car V4M and
R-Car V4H series feature up
to four Arm® Cortex®-A76
cores delivering up to 81K
DMIPS performance for
application processing. It
also comes with three Arm
Cortex-R52 lockstep cores
with up to 25K DMIPS
performance for real-time
operation. The new devices
LiDAR. With the addition of the new “We are extending our ADAS of- are extremely power efficient, pro-
R-Car V4M and R-Car V4H devices, ferings to meet the increasing demand viding 9 TOPS/W performance, thanks
customers can now select the best for Level 1 and Level 2 ADAS to their highly integrated design and
suited SoC option in Renesas’ scalable solutions for mass-market vehicles,” leading-edge manufacturing process
ADAS portfolio. These devices offer said Aish Dubey, Vice President & technology. In a typical full-feature
advanced AI technology, performance General Manager, High Performance smart camera with an 8-megapixel
and power efficiency to meet a diverse Computing SoC Business Division at sensor, the R-Car V4M consumes
array of ADAS application require- Renesas. “At the same time, we are around 5 watts of power – 50 percent
ments. The new devices maintain pin developing our new 5th Generation less than similar devices on the market.
compatibility within the same series R-Car SoCs, which will further Renesas is sampling the R-Car V4M
and software compatibility with ex- bolster our offerings in ADAS, and R-Car V4H devices to leading
isting R-Car products, allowing OEMs cockpit, gateway, and infotainment automotive manufacturers now,
and Tier-1 suppliers to reuse existing segments. We are committed to offer with mass production scheduled in
software and reduce engineering costs. the broadest range of automotive Q1/2026.

PRODUCT SHOWCASE
Upgrade ĞĸĐŝĞŶĐLJ͘ŽǁŶƐŝnjĞĞŵŝƐƐŝŽŶƐ͘

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www.semiconductordigest.com Semiconductor Digest October 2024 | 51

 Industry Obser vation

Cracking the Chip Code to

Meet AI’s Growing Demands
MOZ AHMED, E d g e & E m b e d d e d T e c h n o l o g y S o l u t i o n s M a n a g e r a t M o b i c a

solve this problem? ongoing maintenance

A
I IS REVOLUTIONISING ENTIRE
industries. By next year, it’s ex- First, it breaks the link costs. And with fewer
pected the world will generate between performance functions taking up
over 180 zettabytes of data. As a result, and flexibility. This valuable silicon space,
a fundamental shift in computing power means a system can a custom chip not
is needed to cater for the development of scale up to meet only lowers costs but
these data-hungry innovations. increased demands if provides more chips
In response to this need, one solution required. Secondly, by per wafer, improving
that’s gaining traction is heterogeneous taking advantage of in- each wafer’s yield too.
computing. This enables a single system telligent features like smart The emergence of custom
to have multiple computing sub-systems, scheduling, it breaks the link instructions supported by RISC-V
such as CPUs, GPUs, DSPs, FPGAs between flexibility and cost, so as many also provides an opportunity to further
and ASICs. These processors execute processors can be employed for as many optimise the use of custom processors.
core instructions differently, but work in tasks as possible. Finally, this increased
parallel to help increase compute speed flexibility and scalability results in a more A smarter approach for
and lower the time required to complete efficient, cost-effective system, which can AI applications
a task. The result? A more seamless competently manage multiple tasks. There’s no question the demands placed
user experience in instances where vast on chips are steadily growing. Hetero-
amounts of data need to be processed Opting for custom chip designs geneous computing offers the chance
and converted — such as AI and ma- When considering heterogeneous SoCs, to accelerate computing speed, while
chine learning workloads. there are real gains to be made from reducing the time it takes to complete a
custom chip designs or processing task. By delegating different workloads
A balancing act blocks in an SoC. These are tailored to to specialised processors, performance
For those wishing to push ahead, a specific application requirements, while can be optimised and energy effi-
heterogeneous system on chip (SoC) is providing more control when inte- ciency improved. As businesses rush
stacked with possibilities. Typically when grating hardware and software. to embrace the opportunities opened
designing a system, there’s some kind of Custom chip designs can also deliver up with AI and machine learning, a
tradeoff between flexibility, performance greater cost efficiencies. Because the heterogeneous SoC offers a smarter way
and cost. For instance, general purpose chip is designed for a specific use case, to achieve greater performance.
computing might provide the most fewer inessential features are imple- With a long-standing relationship
flexibility, but loses ground on perfor- mented, reducing design and fabrication with many of the world’s leading
mance and cost. And because applica- costs. In turn, there are fewer functions vendors in the semiconductor industry,
tion-specific computing is designed for a consuming power, which minimises Mobica is well positioned to help them
particular use case, it impresses when it energy usage, and auxiliary components support their customers in maximising
comes to performance, but this comes at a can be designed with a lower specifi- the potential of their silicon products.
price and with less flexibility. In contrast, cation on the printed circuit board. A If you need guidance on how to take
embedded computing is the least flexible, simpler design also means simpler imple- advantage of heterogeneous SoCs and
but typically available for the lowest cost. mentation, making the system easier to custom chip designs, visit www.mobica.
How, then, does a heterogeneous SoC manage and troubleshoot, which reduces com/semiconductor.

52 | October 2024 Semiconductor Digest www.semiconductordigest.com

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