1.

Field Effect Transistors

2. DC Biasing of FETs
Introduction

➢ The FET is a device in which the flow of current

through the conducting region is controlled by an
electric field. Hence, the name Field Effect
Transistor (FET).
➢ For the FET an electric field is established by the
charges present, which controls the conduction
path of the output circuit without the need for
direct contact between the controlling and
controlled quantities.
➢ As current conduction is only by majority carriers,
the FET is said to be a unipolar device depending
solely on either electron (n-channel) or hole (p-
channel) conduction.
Introduction

➢ The FET is a three-terminal device (drain, gate

and source)
➢ Types of FETs : the junction field-effect transistor
(JFET), the metal–oxide–semiconductor field-effect
transistor (MOSFET), and the metal–
semiconductor field-effect transistor (MESFET).
➢ Depending upon the majority carriers, JFET has
been classified into n-channel JFET with
electrons as the majority carriers, and p-channel
JFET with holes as the majority carriers.
Introduction

➢ The MOSFET category is further broken

down into depletion and enhancement types.
➢ There is another form of MOSFET formed when
there is an insulating layer between the gate and
the channel known as insulated-gate FET, or
IGFET .
➢ The MESFET is a more recent development and
takes full advantage of the high-speed
characteristics of GaAs as the base
semiconductor material.
Construction of JFET

➢ For n-channel JFET, the major part of the structure

is the n-type material, which forms the channel.
➢ Heavily doped p-type silicon is diffused on both
sides of the n-type silicon channel by which PN
junctions are formed. The embedded layers of p-
type material connected together and to the gate
(G) terminal.
➢ The top of the n-type channel is connected
through an ohmic contact to a terminal referred to
as the drain (D).
➢ The lower end of the same material is connected
through an ohmic contact to a terminal referred to
as the source (S).
Construction of JFET
Construction of JFET
Operations of JFET

➢ When biased for normal operation, the source

terminal is connected to the negative pole of the
battery.
➢ Electrons which are the carriers in the n-type
channel enter the channel through this terminal.
➢ The drain terminal is connected to the positive
pole of the battery.
➢ The majority carriers leave the channel through
this terminal.
Operations of JFET

➢ When VGS = 0 and VDS = 0

• No voltage is applied between drain and source, and
gate and source, the thickness of the depletion regions
around the PN junction is uniform.
➢ When VGS = 0 and VDS > 0
▪ A positive voltage VDD is applied across the channel
and the gate is connected directly to the source to
establish the condition.
▪ The instant the voltage VDD (=VDS) is applied, the
majority carriers (electrons) flow through the n-channel
from source to drain.
▪ The conventional current ID flows from drain to source.
Operations of JFET
Operations of JFET

• The magnitude of the current will depend upon the

number of carriers (electrons) available in the channel,
the length L of the channel, the cross-sectional area A
of the channel and the magnitude of the applied
voltage VDS.
• As VDS increases and approaches a level referred to as
pinch-off voltage VP, the depletion regions of widen,
causing a noticeable reduction in the channel width.
• When VDS = VP, ID becomes maximum, as the reduced
path of conduction causes the resistance to increase.
• When VDS is increased beyond VP, the length of the
pinch-off or saturation region increases. Hence, there
is no further increase of ID .
Operations of JFET
Operations of JFET

➢When VGS < 0 and VDS = 0

• In this case, gate is reverse biased and hence the
thickness of the depletion region increases.
• As VGS is decreased from zero, the reverse bias
voltage across the PN junction is increased and
hence, the thickness of the depletion region in the
channel also increases until the two depletion regions
make contact with each other.
• In this condition, the channel is said to be cut-off.
• The value of VGS which is required to cut-off the
channel is called the cut-off voltage.
Operations of JFET

➢When VGS < 0 and VDS > 0

• When the gate is at a negative voltage less than
the negative cut-off voltage, the reverse voltage
across the junction is further increased.
• Hence for a negative value of VGS, the curve of ID
versus VDS is similar to that for VGS = 0, but the
values of VP are different.
Drain Characteristics of JFET
Transfer Characteristic Parameters of JFET
Transfer Characteristic Parameters of JFET
➢ A linear relationship does not exist between the output
and input quantities of a JFET.
➢ In a JFET, the drain current ID depends upon the drain
voltage VDS and the gate voltage VGS. Any one of these
variables may be fixed and the relation between the
other two are determined.
➢ The transfer characteristics of JFET shows the
relationship between ID and VGS when VDS is constant
➢ The relationship between ID and VGS is defined by
Shockley’s equation.
2
𝑉𝐺𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1 −
𝑉𝑃
where ID is the drain current, IDSS is the drain to source
saturation current and VP is the pinch-off voltage.
Transfer Characteristic Parameters of JFET
➢ Mutual conductance or transconductance, gm is the
slope of the transfer characteristic curves, and is
∆𝐼𝐷
defined by: 𝑔𝑚 = , 𝑉𝐷𝑆 held constant
∆𝑉𝐺𝑆
➢ Drain resistance rd is the reciprocal of the slope of the
∆𝑉𝐷𝑆
drain characteristics and is defined by:𝑟𝑑 = , 𝑉𝐺𝑆
∆𝐼𝐷
held constant.
➢ Amplification factor μ is the ratio of a small change in
the drain voltage to the corresponding small change in
∆𝑉
the gate voltage at a constant drain current μ = 𝐷𝑆, 𝐼𝐷
∆𝑉𝐺𝑆
held constant.
Transfer Characteristic Parameters of JFET
BJT vs JFET
➢ FET operation depends only on the flow of majority
carriers-holes for p-channel FETs and electrons for
n-channel FETs. Therefore, they are called Unipolar
devices. Bipolar transistor (BJT) operation depends
on both minority and majority current carriers.
➢ The BJT transistor is a current-controlled device
whereas the JFET transistor is a voltage-controlled
device
➢ Typical AC voltage gains for BJT amplifiers are a
great deal more than for FETs.
➢ FETs are usually smaller than BJTs, making them
particularly useful IC chips.
 BJT vs JFET
➢ As the input circuit of FET is reverse biased, FET exhibits a
much higher input impedance So, FET can act as an excellent
buffer amplifier but the BJT has low input impedance because
its input circuit is forward-biased.
➢ FET has a negative temperature coefficient at high current
levels, which prevents the FET from thermal breakdown
while BJT has a positive temperature co-efficient at high
current levels which leads to thermal breakdown.
➢ Since FET does not suffer from minority carrier storage
effects, it has higher switching speeds and cut-off frequencies.
BJT suffers from minority carrier storage effects and therefore
has lower switching speed and cut-off frequencies.
➢ FET amplifiers have low gain bandwidth product due to the
junction capacitive effects and produce more signal distortion
except for small signal operation.
➢ BJTs are cheaper to produce than FETs.
Construction of MOSFET
➢ MOSFETs operates by applying a transverse
electric field across an insulator deposited on the
semiconducting material, the thickness and hence
the resistance of a conducting channel of a
semiconducting material can be controlled.
➢ The terms depletion and enhancement define their
basic mode of operation of MOSFETs.
➢ In a depletion MOSFET, the controlling electric
field reduces the number of majority carriers
available for conduction, whereas in the
enhancement MOSFET, the application of electric
field causes an increase in the majority carrier
density in the conducting regions of the transistor.
Construction of depletion MOSFET
➢ A slab of p-type material is formed from a silicon
base and is referred to as the substrate. It is the
foundation on which the device is constructed
➢ The source and drain terminals are connected
through metallic contacts to n-doped regions
linked by an n-channel.
➢ The gate is also connected to a metal contact
surface but remains insulated from the n-channel
by a very thin silicon dioxide (SiO2)
layer
Construction of depletion MOSFET
Operation of depletion MOSFET

➢ With VDS some positive voltage, VGS at 0 V, an attraction of

the free electrons of the n-channel for the positive voltage
at the drain. The result is a current similar to that flowing
in the channel of the JFET.
➢ When VGS is set at negative voltage, positive charge
consisting of holes is induced in the channel through SiO2
of the gate-channel capacitor.
➢ The introduction of the positive charge causes depletion of
mobile electrons in the channel.
➢ Thus, a depletion region is produced in the channel.
➢ When VDS is increased, ID increases and it becomes
practically constant at a certain value of VDS , called the
pinch-off voltage. The drain current ID almost gets
saturated beyond the pinch-off voltage.
Operation of depletion MOSFET
Construction of enhancement MOSFET
➢ In a n-channel enhancement-type MOSFET, a slab of
p-type material is formed from a silicon base and is
again referred to as the substrate.
➢ Two highly doped n+ regions are diffused in a lightly
doped p-type silicon substrate.
➢ One n+ region is called the source S and the other one
is called the drain D.
➢ A thin insulating layer of SiO2 is grown over the
surface of the structure and holes are cut into the
oxide layer, allowing contact with source and drain.
➢ Then a thin layer of metal aluminium is formed over
the layer of SiO2. This metal layer covers the entire
channel region and it forms the gate G.
Construction of enhancement MOSFET
Operation of enhancement MOSFET

➢ If VGS is set at 0 V and a voltage applied between the

drain and the source of the device, the absence of an n-
channel results in a current of 0 A
➢ With VDS some positive voltage, VGS at 0 V, and terminal
SS directly connected to the source, there are in fact two
reverse-biased p–n junctions between the n-doped
regions and the p-substrate to oppose any significant
flow between drain and source.
➢ The negative charge of electrons which are minority
carriers in the p-type substrate forms an inversion layer.
➢ As the positive voltage on the gate increases, the induced
negative charge in the semiconductor increases.
➢ Hence, the conductivity increases and current flows from
source to drain through the induced channel.
Operation of enhancement MOSFET
Drain and Transfer Xtics of MOSFET
DC Biasing of JFET

➢For the proper functioning of a linear FET

amplifier, it is necessary to maintain the operating
point Q stable in the central portion of the pinch off
region.
➢The Q-point should be independent of device
parameter variations and ambient temperature
changes.
➢This can be achieved by suitably selecting the gate
to source voltage (VGS) and drain current(ID) which
is referred to as biasing.
DC Biasing of JFET

Fixed Bias
Configuration
DC Biasing of JFET

Fixed Bias Configuration

➢ Applying KVL to the gate-to-source section
−𝑉𝐺𝐺 − 𝑉𝐺𝑆 = 0
Thus, 𝑉𝐺𝑆𝑄 = −𝑉𝐺𝐺
➢Since VGG is a fixed dc supply, the voltage VGS is
fixed in magnitude, resulting in the designation
“fixed-bias configuration.”
➢Applying KVL to the drain-to-source section
𝑉𝐷𝑆 + 𝐼𝐷 𝑅𝐷 − 𝑉𝐷𝐷 = 0
𝑉𝐷𝐷 − 𝑉𝐷𝑠
𝐼𝐷𝑄 =
𝑅𝐷
DC Biasing of JFET

Self Bias
Configuration
DC Biasing of JFET

Self Bias Configuration

➢The self-bias configuration eliminates the need
for two dc supplies, with a resistor RS introduced
in the source leg of the configuration.
➢Applying KVL to the gate-to-source section
−𝑉𝐺𝑆 − 𝑉𝑅𝑆 = 0
Thus, 𝑉𝐺𝑆𝑄 = −𝑉𝑅𝑆 = −𝐼𝐷 𝑅𝑆
➢Applying KVL to the drain-to-source section
𝑉𝐷𝑆 + 𝐼𝐷 𝑅𝐷 + 𝐼𝐷 𝑅𝑆 − 𝑉𝐷𝐷 = 0
𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 (𝑅𝐷 + 𝑅𝑆 )
𝑉𝐷𝐷 − 𝑉𝐷𝑆
𝐼𝐷𝑄 =
𝑅𝐷 + 𝑅𝑆
DC Biasing of JFET

Voltage Divider
Configuration
DC Biasing of JFET

Voltage Divider Bias Configuration

➢Using Voltage Divider
𝑅2
𝑉𝐺𝐺 = 𝑉𝐷𝐷
𝑅1 + 𝑅2
➢Applying KVL to the gate-to-source section;
𝑉𝐺𝐺 − 𝑉𝐺𝑆 − 𝑉𝑅𝑆 = 0
Thus, 𝑉𝐺𝑆𝑄 = 𝑉𝐺𝐺 − 𝑉𝑅𝑆 = 𝑉𝐺𝐺 − 𝐼𝐷 𝑅𝑆
➢Applying KVL to the drain-to-source section
𝑉𝐷𝑆 + 𝐼𝐷 𝑅𝐷 + 𝐼𝐷 𝑅𝑆 − 𝑉𝐷𝐷 = 0
𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 (𝑅𝐷 + 𝑅𝑆 )
𝑉𝐷𝐷 − 𝑉𝐷𝑆
𝐼𝐷𝑄 =
𝑅𝐷 + 𝑅𝑆
DC Biasing of JFET

Common Gate
Configuration
DC Biasing of JFET

Common Gate Bias Configuration

➢The gate terminal is grounded and the input signal
typically applied to the source terminal and the
output signal obtained at the drain terminal
Applying KVL to the gate-to-source section;
−𝑉𝐺𝑆 − 𝐼𝑆 𝑅𝑆 +𝑉𝑆𝑆 = 0
Thus, 𝑉𝐺𝑆𝑄 = 𝑉𝑆𝑆 − 𝐼𝑆 𝑅𝑆
➢Applying KVL to the drain-to-source section
𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 − 𝐼𝑆 𝑅𝑆 − 𝑉𝐷𝑆 + 𝑉𝑆𝑆 = 0
𝑉𝐷𝑆 = 𝑉𝐷𝐷 + 𝑉𝑆𝑆 − 𝐼𝐷 (𝑅𝐷 + 𝑅𝑆 )
𝑉𝐷𝐷 + 𝑉𝑆𝑆 − 𝑉𝐷𝑆
𝐼𝐷𝑄 =
𝑅𝐷 + 𝑅𝑆
 Practice Questions
1. When the reverse gate voltage of JFET changes from 4.0 to 3.9 V,
the drain current changes from 1.3 to 1.6 mA. Find the value of
transconductance.
2. An FET has a drain current of 4 mA. If IDSS = 8 mA and VGS(off) =
– 6 V. Find the values of VGS and VP.
3. a. Given IDSS = 12 mA and VP = -4 V, sketch the transfer
characteristics for the JFET transistor.
b. Sketch the drain characteristics for the device of part (a).
4. Given IDSS = 9 mA and VP = -4 V, determine ID when:
a. VGS = 0 V.
b. VGS = -2 V.
c. VGS = -4 V.
d. VGS = -6 V.
5. An N-channel JFET has IDSS = 8 mA and VP = – 5 V. Determine
the minimum value of VDS for pinch-off region and the drain
current IDS, for VGS = – 2V in the pinch-off region.
 Practice Questions

6. Calculate the operating point of the self-biased JFET

having the supply voltage VDD= 20 V, maximum value of
drain current IDSS = 10 mA and Vgs = – 3 V at ID = 4 mA.
Also, determine the values of resistors RD and Rs to obtain
this bias condition.
7. Calculate the values of Rs required to self bias an N-
channel JFET with IDSS = 40 mA, VP = – 10 V and VGSQ = –
5 V.
8. A JFET amplifier with a voltage divider biasing circuit
has the following parameters: VP = – 2 V, IDSS = 4 mA, RD =
910 Ω , Rs = 3 k Ω, R1 = 12 M Ω, R2 = 8.57 MΩ and VDD =
24 V. Find the value of the drain current ID at the
operating point. Verify whether the FET will operate in
the pinch-off region.
 Recommended Text

1. Electronic Devices and Circuit Theory by Robert L.

Boylestad and Louis Nashelsky. Prentice Hall
Publications.
2. Electronic Devices, Circuits, and Applications by
Christopher Siu. Springer Nature Switzerland