Module 3
Module 3
ACCESSING I/O-DEVICES
• A single bus-structure can be used for connecting I/O-devices to a computer (Figure
7.1).
• Each I/O device is assigned a unique set of address.
• Bus consists of 3 sets of lines to carry address, data & control signals.
• When processor places an address on address-lines, the intended-device responds to the
command.
• The processor requests either a read or write-operation.
• The requested-data are transferred over the data-lines.
Concept of interrupts:
When processor is handling interrupts, it must inform device that its request
has been recognized. This may be accomplished by INTA signal.
• The processor first completes the execution of instruction at the address i.
• Current Program Counter (PC) contents to be saved in some temporary storage
location.
• Then, processor loads the PC with the address of the first instruction of the
ISR.
• After the execution of ISR, the processor has to come back to instruction at the
address i+1.
• A return at the end of ISR reloads the PC with the return address from that
temporary storage location.
• This causes the execution to resume at instruction i+1.
• The task of saving and restoring the information can be done automatically by
the processor.
• The processor saves only the contents of PC & Status register.
This interruption is temporary, and after the ISR finishes, the processor resumes
normal activities.
*********Q. Define interrupt. Point out and explain the various ways of
enabling and disabling interrupts (10 M)*****
An interrupt is a signal emitted by hardware or software that alerts the
processor indicating an immediate attention.
The arrival of an interrupt request from an external device causes the processor
to suspend the execution of one program and start the other one.
INTERRUPT HARDWARE
• Most computers have several I/O devices that can request an interrupt.
• A single interrupt-request (IR) line may be used to serve n devices (Figure 4.6).
• All devices are connected to IR line via switches to ground.
• To request an interrupt, a device closes its associated switch.
• Thus, if all IR signals are inactive, the voltage on the IR line will be equal to Vdd.
• When a device requests an interrupt, the voltage on the line drops to 0.
• This causes the INTR received by the processor to go to 1.
• The value of INTR is the logical OR of the requests from individual devices.
INTR=INTR1+ INTR2+ . . . . . +INTRn
• A special gates known as open-collector or open-drain are used to drive the INTR line.
• The Output of the open collector control is equal to a switch to the ground that is
→ open when gates input is in ”0‟ state and
→ closed when the gates input is in “1‟ state.
• Resistor R is called a Pull-up Resistor because it pulls the line voltage up to the high
voltage.
Priority structure
Q. With neat diagram explain the use of DMA controllers in computer
system.
DIRECT MEMORY ACCESS (DMA)
• The transfer of a block of data directly b/w an external device & main-memory
w/o continuous involvement by processor is called DMA.
• DMA controller
→ is a control circuit that performs DMA transfers as shown in figure.
→ is a part of the I/O device interface.
→ performs the functions that would normally be carried out by processor.
• While a DMA transfer is taking place, the processor can be used to execute another
program.
• There are 2 ways in which the DMA operation can be carried out:
1) Processor originates most memory-access cycles.
➢ DMA controller is said to "steal" memory cycles from processor.
➢ Hence, this technique is usually called Cycle Stealing.
2) DMA controller is given exclusive access to main-memory to transfer a
block of data without any interruption. This is known as Block Mode (or
burst mode).
Q. Explain registers involved in DMA interface, to illustrate DMA(6 M)
• DMA interface has three registers (Figure 8.12):
1) First register is used for storing starting-address.
2) Second register is used for storing word-count.
3) Third register contains status- & control-flags.
BUS ARBITRATION
The device that is allowed to initiate data transfers on the bus at any given time is called the
bus master. When the current master relinquishes control of the bus, another device can
acquire this status. Bus arbitration is the process by which the next device to become the bus
master is selected and bus mastership is transferred to it. The selection of the bus master must
take into account the needs of various devices by establishing a priority system for gaining
access to the bus.
Two types ; centralized and distributed.
In centralized arbitration, a single bus arbiter performs the required arbitration.
In distributed arbitration, all devices participate in the selection of the next bus master.
• The timing diagram shows the sequence of events for the devices connected to the
processor.
• DMA controller-2
→ requests and acquires bus-mastership and
→ later releases the bus. (Figure: 4.21).
• After DMA controller-2 releases the bus, the processor resources bus-mastership.
Q.With a neat diagram explain how to interface printer to the processor
(10 M)
PRINTER INTERFACED TO PROCESSOR
-The printer operates under control of the handshake signals Valid and Idle. When it is ready to
accept a character, the printer asserts its Idle signal. The interface circuit can then place a new
character on the data lines and activate the Valid signal. In response, the printer starts printing the
new character and negates the Idle signal, which in turn causes the interface to deactivate the Valid
signal.
The interface contains a data register, DATAOUT, and a status flag, SOUT. The SOUT flag is set to 1
when the printer is ready to accept another character, and it is cleared to 0 when a new character is
loaded into DATAOUT by the processor.
Q. Consider the daisy chain arrangement. Assume that after a device generates an
interrupt-request, it turns off that request as soon as it receives the interrupt
acknowledge signal. Is it still necessary to disable interrupts in the processor before
entering the interrupt service routine? Why?
Solution:
Yes, because other devices may keep the interrupt-request line asserted.
Problem 1:
Three devices A, B, & C are connected to the bus of a computer. I/O transfers for
all 3 devices use interrupt control. Interrupt nesting for devices A & B is not
allowed, but interrupt-requests from C may be accepted while either A or B is being
serviced. Suggest different ways in which this can be accomplished in each of the
following cases:
(a) The computer has one interrupt-request line.
(b) Two interrupt-request lines INTR1 & INTR2 are available, with
INTR1 having higher priority. Specify when and how interrupts are enabled and
disabled in each case.
Solution:
(a) Interrupts should be enabled, except when C is being serviced. The
nesting rules can be enforced by manipulating the interrupt-enable flags in
the interfaces of A and B.
(b) A and B should be connected to INTR , and C to INTR. When an
interrupt-request is received from either A or B, interrupts from the other
device will be automatically disabled until the request has been serviced.
However, interrupt-requests from C will always be accepted.
Problem 2:
A disk unit has 24 recording surfaces. It has a total of 14,000 cylinders. There
is an average of 400 sectors per track. Each sector contains 512 bytes of data.
(a) What is the maximum number of bytes that can be stored in this unit?
(b) What is the data-transfer rate in bytes per second at a rotational speed of
7200 rpm?
(c) Using a 32-bit word, suggest a suitable scheme for specifying the disk
address.
Solution:
(a) The maximum number of bytes that can be stored on this disk is 24 X 14000 X
400 X 512 =
68.8 X 109 bytes.
(b) The data-transfer rate is (400 X 512 X 7200)/60 = 24.58 X 106 bytes/s.
(c) Need 9 bits to identify a sector, 14 bits for a track, and 5 bits for a surface.
Thus, a possible scheme is to use address bits A8-0 for sector, A22-9 for track,
and A27-23 for surface identification. Bits A31-28 are not used.