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11 views4 pages

EDA Question

Uploaded by

dopeso3698
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Ref: ET/T/415

BETCE 4th Year, 1st Semester Evaluation 2021


Subject: Electronic Design Automation ( Elective paper)

Full Marks: 100

All the questions under Q.1 is compulsory ( 30 Marks)


Rest of the questions ( Q.2-Q.6) contains A or B options ( 70 marks)

Q.1 Answer All question. 15 x 2 = 30

a. Briefly explain the requirement of synthesis

b. Can FPGA be by any chance be ASIC?

c. In recent router cum modem all are integrated in a single package. Is it ASIC or ASSP?

d. What is the difference between RISC and CISC?

e. Configurable logic block requires which type of routing?

f. Give two example of technology library

g. What is Back annotation?

h. What is timing analysis ?

i. Give an example of discrete stochastic model.

j. What is event scheduling in VHDL ?

k. What is false alarm in inertial propagation delay ?

l. Resolution function takes which type of array?

m. What is LVS?

n. In SPICE model what is the priority level among electrical and physical parameter?

o. In PLA, extra crosspoint in AND-array gives to what kind of fault?


Q.2 A 4+6+4=14

a. Explain the operation of signal driver for inertial delay model

b. Develop a VHDL code of a 4 to 1 MUX that selects among four unsigned 6 bit integer.

c. Write a package declaration and how a package has been compiled?

Or
Q.2 B 3+3+8=14

a. What is the difference between inertial and transport delay model

b. Write the VHDL code of following FSM

Q.3 A 2+6+6=14

a. What is resolution function? Write the code for resolution function and its output process for
multiple signal driver assignment

b. Write a VHDL model for a 12 bit register that stores an unsigned integer value.

Or
Q.3 B 3+3+6+2=14

a. Write a Test bench of 2 input Xor gate. Also write the main programme of the Xor gate.

b. Write a code for Mealy Machine.

c. What is array attributes?

Q.4 A 5+5+4=14

a. Explain the basic differences between full custom and semi custom IC designs.

b. Explain the design cycle of ALU-RTL level in Y chart.

c. Draw and explain the logic synthesis steps from RTL level to physical design. What is
component library?
Or
Q.4 B 4+6+4=14

a. Explain the difference between verification and validation.

b. What are the different stages in simulation?

c. Explain event driven simulation

Q.5 A 4+4+4+2=14

a. What is the VLSI design cycle?

b. Explain the difference between global and local routing

c. What is partitioning technique? How signal integrity is taken care in partitioning process.

d. In a multilayer chip module how interconnect delays are addressed?

Or
Q.5 B 4+1+4+1+4=14

a. Explain the level 1 model of a MOS transistor with equivalent circuit. What are parasitic
parameters?

b. Explain the difference between different kinds of modeling in transistor.

c. what is compact modeling?

d. Deduce the drain current in linear and saturation level, gate capacitance, intrinsic gate delay
and power density for constant voltage scaling.

Q.6 A 3+2+3+3+3=14

a. What is the difference between parametric failure and catastrophic failure? Is there any
correlation among them?

b. What is total yield?

c. Explain designable and noise component on typical CMOS based circuit parameters.
d. The dependence of the mobility on temperature is determined empirically as. Derive the
expression for ∆µ/µ in terms of ∆T/T

300
= .

300

Or
Q.6 B 1+3+2+3 +1+4=14

a. What is Stuck at Zero fault model. In the function F = AB+BC+A/C, what can be the
redundancy removal circuit and function?

b. Write three processing type faults? Is it possible to have a combinational circuit with some
signal line S and a test vector T such that T detects both S/0 and S/1 faults

c. What is defined as Response surface model? A CMOS chip with three signal input terminals,
one output terminal, one power supply terminal, and one ground terminal is presented to you.
The input signal voltages can vary from 0 to 5 V, the power supply voltage can vary from 4.5 V
to 5.5 V, and the device operating temperature can range from 0 to 85 0C. We want to design an
experiment so that the DC response of the chip can be described by a quadratic response surface
model for three inputs, power supply voltage, and temperature.

Design a full factorial experiment.

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