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EDA UG Sem 2021

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15 views4 pages

EDA UG Sem 2021

Uploaded by

dopeso3698
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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BETCE 4th Year, 1st Semester Evaluation 2021

Subject: Electronic Design Automation ( Elective paper)

Full Marks: 70

Q.1 is compulsory and answer all questions from Q.2 to Q.6. Each Questions (Q.2 –Q.6) have two
options

Q.1 Answer All question. 10x 2 = 20

a. Briefly explain the requirement of synthesis

b. In Configurable logic block requires which type of routing are use?

c. Give an example of discrete stochastic model.

d. What is LVS and in which step it is used?

e. What is false alarm in inertial propagation delay ?

f. In SPICE model what is the priority level among electrical and physical parameter?

g. In PLA, extra crosspoint in AND-array gives to what kind of fault?

h. What is logical effort of a gate and why it is compared with inverter?

i. Can P V T model forms a rhombus instead of cube?

j. Give an example of response variable in One way Anova

Q.2 A 5x2= 10

a. Write the code for resolution function and its output process for multiple signal driver
assignment

b. What is the difference between inertial and transport delay model

Or

Q.2 B 4+6=10

a. Explain the operation of signal driver for inertial delay model.

b. Develop a VHDL code of a 4 to 1 MUX that selects among four unsigned 6 bit integer.
Q. 3A 5x2= 10

a. Write a code for following state machine

b. Write a VHDL code for 4 bit parallel adder.

Or

Q.3 B 5x2= 10

a. Write a Test bench of 2 input Xnor gate. Also write the main programme of the Xnor gate.

b. Write a VHDL programme for Dual edge D flip flop.

Q.4 A
5x2= 10
a. Explain the basic differences between full custom and semi custom IC designs.
b. Explain the design cycle of ALU-RTL level in Y chart.

Or
Q. 4 B
5x2= 10
a. How a queue process can be initiated in an event driven simulation?

b. Explain briefly whether event driven simulation can be level triggered or edge triggered?

Q. 5 A
5x2= 10

a. How zero bias threshold voltage is modeled in SPICE level 1 and level 2?

b. Deduce the drain current in linear and saturation level, gate capacitance, intrinsic gate delay
and power density for constant voltage scaling.

Or
Q. 5 B
6+4=10

Estimate small signal gain. Is the above circuit conditionally stable, explain?

Q.6 A
5x2= 10

a. In the following figure which of the fault are undetectable when y= 0

b. For a weighted circuit shown in the figure below, what should be the probability of obtaining
a logic 1 value at Y1, when the probability of obtaining a logic 1 value at X1, X2, X3, X4 are a1,
a2, a3 and a4 respectively.

Or
Q.6 B
5x2= 10

a. An engineer designs a 22 design with n = 4 replicates to study the effects of bit size (A) and
cutting speed (B) on routing notches in a printed circuit board. The signs in the AB column are
the signs that result when multiplying the A and B columns.

What is the average effect of Factor A and Factor B? What is the sum of square effects?

b. Draw the flowchart to generate response surface model in comparison to SPICE model.

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