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Field Effect Transistor

Electronic notes for all engineering branches of engineering students

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0% found this document useful (0 votes)
21 views9 pages

Field Effect Transistor

Electronic notes for all engineering branches of engineering students

Uploaded by

truptibodke37
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Field Effect Transistor

❖ FET :
• It is a three terminal semiconducting device.
• It is a type of transistor which uses an electric filed to control flow of
current in semiconductor.
• It is also known as unipolar transistor (single carrier type operation).
• The FETs are either electrons (-) or holes (+) when they are in
operation.
• FETs control the flow of current by the application of a voltage to the
gate, which in turn alters the conductivity between the drain and source.
• All the forms of FET have high input impedance.
• A field-effect transistor’s terminals have applied a voltage through
which conductivity is regulated.
• The voltage that was applied to the gate creates an electric field in the
device which causes repulsion and attraction to charges that are carried
amid the two terminals.
• The conductivity is also affected due to the density of those charge
carriers.

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❖ Types of FET :
There are two main types of field effect transistor are as
follow :
1. Junction field effect transisito (JFET)
2. Metal oxide semiconductor field effect transistor (MOSFET).

❖ JFET :
• JFETs are voltage-controlled devices.
• In JFET, the current flow is due to the majority of charge carriers.
• JFETs are unidirectional.
• The current conduction is controlled by means of an electric field
between the gate electrode and the conduction channel.

❖ Construction :
• It consists of an n – type silicon bar forming the conduction channel for
the charge carriers.
• The pn – junction forming diodes are connected internally and a
common terminal called GATE is taken out from the p - Region.
• The other two terminals viz.
• Source and Drain are taken out from the bar.

▪ P channel JFET :
• It consists of a p – type silicon bar forming the conduction channel for
the charge carriers.
• The pn – junction forming diodes are connected internally and a
common terminal called GATE is taken out from the n - Region.
• The other two terminals viz.
• Source and Drain are taken out from the bar.

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❖ Working :
• Case-i:
• When a voltage VDS is applied between drain and source terminals and
voltage on the gate is zero.
• The two pn junctions at the sides of the bar establish depletion layers.
• The electrons will flow from source to drain through a channel between
the depletion layers.
• The size of the depletion layers determines the width of the channel and
hence current conduction through the bar.

• Case ii :
• When a reverse voltage VGS is applied between gate and source
terminals.
• the width of depletion layer is increased.
• This reduces the width of conducting channel, thereby increasing the
resistance of n-type bar.
• the current from source to drain is decreased.
• when the reverse bias on the gate is decreased, the width of the
depletion layer also decreases.
• This increases the width of the conducting channel and hence source to
drain current.

❖ Symbol : JFET
• N channel :

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• P channel :

❖ Characteristics of JFET :
▪ Output V-I characteristics:

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▪ Drain source voltage :

▪ Transfer characteristics :

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❖ FET Parameters :
▪ Gate Cut Off Voltage(VGS(off)): After a certain gate to source voltage
(VGS), the drain current ID becomes zero. This voltage is known as Cut
Off Gate Voltage (VGS(off)).
▪ Shorted Gate Drain Current (IDSS): This is the maximum drain current
that can flow through the channel when the gate terminal is in ground
potential.
▪ Pinch off voltage(VP): It is the minimum drain-source voltage at which
the drain current becomes constant.
▪ Transconductance(gm): Transconductance is the ratio of change in drain
current (δID) to change in the gate to source voltage (δVGS) at a constant
drain to source voltage (VDS = Constant).

▪ This is the ratio of change of drain to source voltage (δVDS) to the change
of drain current (δID) at a constant gate to source voltage (VGS =
Constant). The ratio is denoted as rd.

▪ Amplification Factor(μ): The amplification factor is defined as the ratio of


change of drain voltage (δVDS) to change of gate voltage (δVGS) at a
constant drain current (ID = Constant).

❖ FET Terminal :
▪ Source :

• The Source terminal FET is the one through which the carriers enter
the channel.
• The Source terminal can be designated as S.
• The current entering the channel at Source terminal is indicated as Is.

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▪ Gate :

• The Gate terminal plays a key role in the function of FET by


controlling the current through the channel.
• By applying an external voltage at Gate terminal, the current through it
can be controlled.
• Gate is a combination of two terminals connected internally that are
heavily doped.
• The Gate terminal can be designated as G.
• The current entering the channel at Gate terminal is indicated as IG.
▪ Drain :

• The Drain terminal in a FET is the one through which the carriers leave
the channel.
• The Drain to Source voltage is designated as VDS.
• The Drain terminal can be designated as D.
• The current leaving the channel at Drain terminal is indicated as ID.

MOSFET

❖ MOSFET :
• MOSFET stands forMetal Oxide Silicon Field Effect Transistors
• MOSFETs are electronic devices used to switch or amplify
voltages in circuits.
• The MOSFET are invented to overcome the disadvantages posed
by FETs, such as the slow operation, high drain resistance, and
moderate input impedance.
• It is a current controlled device and is constructed by three
terminals.
• The terminals of MOSFET are named as follows:
➢ Source
➢ Gate
➢ Drain
➢ Body

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❖ Construction of MOSFET :

• The p-type semiconductor forms the base of the MOSFET.


• The two types of the base are highly doped with an n-type
impurity which is marked as n+ in the diagram.
• From the heavily doped regions of the base, the terminals source
and drain originate.
• The layer of the substrate is coated with a layer of silicon dioxide
for insulation.
• A thin insulated metallic plate is kept on top of the silicon dioxide
and it acts as a capacitor.
• The gate terminal is brought out from the thin metallic plate.
• A DC circuit is then formed by connecting a voltage source
between these two n-type regions.

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❖ Working of MOSFET :

• The main principle of the MOSFET device is to be able to control the


voltage and current flow between the source and drain terminals.
• It works almost like a switch and the functionality of the device is based
on the MOS capacitor.
• The MOS capacitor is the main part of MOSFET.
• The semiconductor surface at the below oxide layer which is located
between the source and drain terminal can be inverted from p-type to n-
type by the application of either a (+) or (-) gate voltages respectively.
• When we apply a repulsive force for the (+) gate voltage, then the holes
present beneath the oxide layer are pushed downward with the
substrate.
• The depletion region populated by the bound (-) charges which are
associated with the acceptor atoms.
• When electrons are reached, a channel is developed.
• The (+) voltage also attracts electrons from the n+ source and drain
regions into the channel.
• If a voltage is applied between the drain and source, the current flows
freely betn the source and drain and the gate voltage controls the
electrons in the channel.
• Instead of the (+) voltage, if we apply a negative voltage, a hole channel
will be formed under the oxide layer.

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