AN OFFSET COMPENSATED FULLY DIFFERENTIAL

CMOS CURRENT COMPARATOR

G. Paimisano - G. Palumbo
Dipartimento Elettrico, Elettronico e Sistemistico
UNIVERSITA' DI CATANIA
Vide Andrea Dona, 6 1-95125 CATANIA - ITALY
Phone 39.95.339535 Fax 39.95.330793

ABSTRACT charge-injection compensated, and is designed following

some of the design guide lines previously introduced [5-
A novel fullydifferential current comparator is 81.
proposed which is based on a double folded-cascode structure.
Thanks to an offset and charge-injection compensation, it 11. CIRCUIT DESCRIPTION
provides a sensitivity as good as 20 nA. Moreover, it achieves a
switching time better than 30 ns with a 0.5-p.4 input step The proposed comparator is shown in Fig. 1. It is
current while dissipating 45 pW. based on the double folded-cascode structure and includes
a compensation circuit which provides offset and charge-
I. INTRODUCTION injection compensation as well as common-mode output
voltage control.
Current-mode analog integrated circuits (ICs) in The uncompensated comparator is made up of
CMOS technologies have received great interest in recent transistors M3-M6 and current source transistors M7, M8.
years [I-21. This approach seems particular interesting Diodeconnected transistors M1 and M2, and current
because it takes advantage from the use of digital sources I,, and set the input bias current and the
processes for implementetion of ICs. Indeed, A/D input bias voltage.
converters, filters, nonlinear circuits, etc. with small area The compensation circuit is composed of the
and low power consumption can be designed by adopting Werential stage, M9-Ml0, the current generator, I,,, the
current mode approach [3-4]. Moreover, many signal storage capacitors, CHI and C,,, and the switches, SA1
sources such as temperature sensors, photo-sensors, etc., and SA2. Thanks to the perfect symmetry of the circuit,
provide current signals, and, in these and in other the diodeconnected transistors MlOA, MlOB set the bias
current-mode circuits, the Current comparator is a current in M8A and M8B to IB3/2. Moreover, the gate-
fundamental building block. source voltage of M9 together with the gate-source
An important feature of a comparator is its voltage of M7 provide the output bias voltage.
accuracy which is principally aEfected by the offset. A When switches SA1 and S A 2 are closed, the
general technique for the offset compensation, was uncompensated comparator and the compensation circuit
proposed in [5j. This technique has, however, the are connected through two different loops, one for the
drawback of reducing the comparator gain and the differential signal, the other for the common-mode signal.
accuracy is limited by a residual offset due to the charge- When switches SAL and SA2 are opened, the two loops
injection error. A less general offset compensation are disconnected and the common-mode output level and
approach which does not afEct the comparator gain, but the output offset voltage are both frozen in the hold
does not provide charge-injection compensation, was capacitors.
presented in [ 6 ] .Up to now the better solution seems to be
the circuit proposed by the authors in [7]. It is offset and Offset compensation
charge-injection compensated.
In t h ~ scommunication we propose a new current As far as the Merential loop is concerned, the
comparator which provides differential input and output circuit can be represented with the diagram in Fig. 2
terminals. FullydBerential topology has, in fact, the which is the single-input single-output version of the
intrinsic advantages of accuracy and power supply noise comparator.
rejection. Moreover, the availability of a differential input The compensation is based on a feedback loop
could be very useful in applications where the input is a which includes switch SA, the differential stage, here
floating current source. The comparator is offset and represented with block A, and common source transistor
0-7803-2972-4/96$5.00@1996IEEE

1038

Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on January 11,2025 at 08:34:26 UTC from IEEE Xplore. Restrictions apply.
M8 which belongs to the output branch of the the switch terminals [9-121. Generally, in order to reduce
uncompensated comparator. Current Iosl and voltage V, it, common remedies are the use of a CMOS switch, a
are the input offset current of the uncompensated larger capacitance C,, andor the use of a dummy switch.
comparator and the input offset voltage of the differential However, in the comparator in Fig. 1, switches SA1 and
stage, respectively. S A 2 have equal voltages at their terminals, and, hence,
This approach is similar to the compensation they inject equal charges into capacitors CHI and CHI,.
approach in [5], but here the transconductance element, Therefore, setting equal the hold capacitors, the charge
which is performed by transistor M8, is in series with the injection gives rise to a common mode signal wtuch is
output branch. Thus, the output impedance of the original rejected by the differential topology.
comparator is now preserved.
Assuming as an initial condition switch SA to be 111. CIRCUIT SIMULATION
open and capacitor CH to be discharged, the output offset
voltage, Vos, of the overall circuit is The circuit in Fig.1 has been simulated using
SPICE and the model parameters of a 2-pm CMOS
O
'S = %'OS1 + A0gm8roV0s2 (1) process, by setting the transistor aspect ratio as shown in
Table I.
where ro, A, and gM8 are the equivalent output resistance With bias currents I,, and 1, equal to 1 pA and
of the uncompensated comparator, the gain of block A, a 5-V power supply, the overall power dissipation is
and the transconductance of transistor M8, respectively. around 45 pW. A sensitivity simulation with a slowly
The equivalent offset current to the comparator input, I,,, varying triangular input current is shown in Fig. 3, where
is easily obtained dividing by ro eq. (1). curve 1 is the input current and curve 2 is the output
voltage. A sensitivity better than 20 nA is acheved.
A transient simulation with an input step current
from -0.5 pA to 0.5 pA is illustrated in Fig. 4. The
When switch SA turns on, the loop around the output switching time from 2.5 V to 3.5 V is lower than 30 ns,
branch of the comparator is closed, and the output offset while that from 2.5 V to 1.5 V is lower than 20 ns.
voltage, Vosc, becomes
IV. REFERENCES

PI C. Tomazou, F. Lidgey, D. Haigh, Analogue IC design: the

current-mode approach, IEE, 1990.
PI C. Tomazou, J. Hughes, N. Battersby, Swirched-Currents an
where term A&8r0 is the loop gain. When switch SA analogue techniquefor digital technology, IEE, 1993.
turns off, voltage Vo, is stored on capacitor C ,, and [31 P. Crolla,"A Fast Latching Current Comparator for 12-Bit A/D
maintained in the output node. Thus, the equivalent offset Applications," IEEE Jour. of Solid-Stare Circuits, Vol. SC-17,
N0.6, pp.1088-1093, Decemeber 1982.
current, I, to the comparator input is now given by r41 D. Nairn, C. Salama, "Current-Mode Algorithmic Analog-to-
Digital Converters,"IEEE Jour. of Solid-state Circuits, V01.25,
N0.4, pp.997-1004, August 1990.
(4) G. Palmisano, G. Palumbo, "An offset Compensation Technique for
CMOS Current Comparators",Electronics Leffers, Vo1.30, N. 11,
pp.852-854, May 1994.
G. Di -do, G. Palmisano, G. Palumbo, S. Pennisi, "An
Therefore, despite the additional offset component due to Accuratee offset-Compensated Current Comparator,'' Proc. IEEE
the compensation circuit, a very low input offset current is MDWSTW, 1994.
achieved. t71 G. Palmisano, G . Palumbo, "Offset-Compensated Low Power
Substituting A, with the actual value gm9/gm10, Current Comparators", Electronics Letters , Vo1.30, N.20,
pp.1637-1639, Sept. 1994.
eq. (4) becomes G. Palmisano, G. Palumbo, S. Pennisi, "A High-Accuracy, High-
Speed CMOS Current Comparator,''Proc. IEEE ISCAS94, 1994.
D. Allstot, "A Precision Variable-Supply Cmos Comparator,"IEEE
(5) J. Solid-Stare Circuirs, vol. SC-17, no.6, pp. 1080-1087, Dec.
1982.
R. Gregorian, G. C. Tema, Analog MOS Integrated Circuits for
signalsprocessing, John Wiley & Sons, 1986.
J. Shieh, M. Patil, B. Sheu, "Measurement and Analysis of Charge
Charge Injection Injection in MOS Analog Switches," IEEE J. Solid-Stare Circuits,
vol. SC-22, no.2, pp.277-281, Apr. 1987.
G . Wegmann, E. Vittoi F. Rahali, "Charge Injection in Analog
The charge A Q injected into CH depends on the MOS Switches," IEEE J. Solid-State Circuits, vol. SC-22, 110.6,
total amount of the switch channel charge, the shape of pp.1091-11097, Dec. 1987.
the clock edges, and the ratio between the capacitances at

1039

Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on January 11,2025 at 08:34:26 UTC from IEEE Xplore. Restrictions apply.
 I
I 1 I

I
M8B M8A -1 MlOB MlOA
I
-
M5B M3B

t vo I
I
I
dl I
SA1
M9B M9A

M7B M7A

vs s I
I

I
I
uncompensated
I c o m p e n s a t i o n circuit
comparator

TABLE I

Fig. 2 Simblifed block diagram of the compensated comparator

1040

Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on January 11,2025 at 08:34:26 UTC from IEEE Xplore. Restrictions apply.
 f

secs

Fig. 3 Sensitivity: (1) itlput current;(2) output response

T I E in Sees

Fig. 4 Time response: (1) input step current; (2) output response

1041

Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on January 11,2025 at 08:34:26 UTC from IEEE Xplore. Restrictions apply.