1

Module -1

Metal Oxide Semiconductor Field effect transistor (MOSFET)

Metal Oxide Silicon Field Effect Transistors commonly known as MOSFETs are electronic devices used to switch
or amplify voltages in circuits. It is a voltage controlled device and is constructed by three terminals. The terminals
of MOSFET are named as follows:

● Source
● Gate
● Drain
● Body

MOSFET Types
● The classification of MOSFET based on the construction and the material used is given below in the
flowchart.

● MOSFETs are of two classes: Enhancement mode and depletion mode. Each class is available as n-
channel or p-channel

Types of E-MOSFET
Based on the type of charge carriers (electrons or holes), E-MOSFET can be classified into two types:
● N-Channel E-MOSFET
● P-Channel E-MOSFET

N-Channel E-MOSFET
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● This type of MOSFET is called as n-channel MOSFET because the flow of current takes place by
conduction of negative charge carriers, i.e., electrons.
Construction of N-Channel E-MOSFET
● A n-channel E-MOSFET consists mainly of three terminals: Source(S), Gate(G) and Drain(D).
● A substrate (SS) is made up of a p-type semiconductor and is internally connected with source
terminal or sometimes brought out in a form fourth terminal.
● The other three terminals, i.e., drain, gate and source as connected to each other by n-doped
region through metallic contacts. The figure given below shows the construction of N-Channel E-
MOSFET:

Fig 2.1 symbol

● The full form of E-MOSFET is Enhancement- Metal Oxide Semiconductor Field Effect Transistor.
It is called as enhancement MOSFET because for a creating a conduction channel between drain
and source terminal, a positive voltage is required at the gate terminal.
● Metal is for the metallic contacts that are used to connect drain(D), gate(G) and source(S) terminals.
● Oxide is for the silicon dioxide (SiO2) layer which is used as an insulating layer between substrate and gate
terminal. Semiconductor is for the structure which is used in the construction of this transistor. To sum up,
the name E-MOSFET is given to this type of device.
P-Channel E-MOSFET
● This type of MOSFET is called as p-channel MOSFET because the flow of current takes place by conduction
of positive charge carriers, i.e., holes.
Construction of P-Channel E-MOSFET
● A p-channel E-MOSFET consists mainly of three terminals: Source(S), Gate(G) and Drain(D). A substrate
(SS) is made up of a n-type semiconductor and is internally connected with source terminal or sometimes
brought out in a form fourth terminal.
● The other three terminals, i.e., drain, gate and source as connected to each other by p-doped region through
metallic contacts. The figure given below shows the construction of p-channel E-MOSFET:
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Fig 2.2a Symbol

Circuit symbol of p-channel E-MOSFET is shown above

Two-Terminal MOS Structure

Fig 2.3
● The MOSFET is the metal-oxide-semiconductor capacitor shown in Figure 2.3. The metal may be
aluminum or high-conductivity polycrystalline silicon layer deposited on the oxide.
● A positive voltage applied to the gate shown in Figure 2.4a, positive charge now exists on the top
metal plate and the induced electric field is in the opposite direction.
● In this case, if the electric field penetrates the semiconductor, holes in the p-type material
will experience a force away from the oxide-semiconductor interface.
● Now as the holes are pushed away from the interface, a negative space-charge region is
created shown in fig 2.4b, because of the fixed acceptor impurity atoms. This is called depletion mode.
● The negative charge in the induced depletion region corresponds to the negative charge on
the bottom “plate” of the MOS capacitor.
● Figure 2.4c shows the equilibrium distribution of charge in the MOS capacitor when we
applied gate voltage. When a larger positive voltage is applied to the gate, the magnitude
of the induced electric field increases.
● Minority carriers called electrons in this case are attracted to the oxide semiconductor interface,
as shown in Figure 2.4c. This region of minority carrier electrons is called an electron inversion layer.
The magnitude of the charge in the inversion layer is a function of the applied gate voltage.
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Fig 2.4

The MOS capacitor with an n-type substrate

● The same charge distributions can be obtained in a MOS capacitor with an n-type semiconductor substrate.
Figure 2.5a shows this MOS capacitor structure, with a positive voltage applied to the top gate terminal.
● After this positive charge is created on the top gate and an electric field is induced in the direction shown.
● In this situation, an accumulation layer of electrons is induced in the n-type semiconductor.
● Figure 2.5b shows the case when a negative voltage is applied to the gate terminal. A positive space-charge
region is induced in the n-type substrate by the induced electric field.
● When a larger negative voltage is applied, a region of positive charge is created at the oxide-semiconductor
interface, as shown in Figure 2.5c.
● This region of minority carrier holes is called a hole inversion layer.
● The magnitude of the positive charge in the inversion layer is a function of the applied gate voltage.

Fig2.5

Working of E-MOSFET
● Figure 2.6a shows an n-channel enhancement-mode MOSFET with the source and substrate
terminals connected to ground.
● The gate-to-source voltage is less than the threshold voltage, with small drain-to-source voltage
bias configuration, there is no electron inversion layer, and hence the drain current is zero.
● When the value of gate-to-source voltage is positive then the holes in p-doped region would
be repelled by the positive terminal voltage which is applied at gate terminal.By this a depletion region
is created near silicon dioxide layer.
● When there is increase in positive voltage from gate-to-source terminal, the gathering of electrons near
insulating layer of silicon dioxide increases shown in fig 2.6b
● This results in formation of induced n-channel between n-doped region of drain to source terminal.
● This induced channel connects drain and source terminals internally and current starts flowing through it.
The minimum voltage at which current starts flowing through it is called as threshold voltage (VT).
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Fig2.6

● The working of p-channel E-MOSFET is exactly opposite to that of p-channel E-MOSFET, i.e., all
voltage polarities are reversed and thus the flow of current is also reversed.

Characteristics of E-MOSFET
● There are two types of characteristics of E-MOSFET- drain characteristics and transfer characteristics.
Both type of E-MOSFET, i.e., n-channel E-MOSFET and p-channel E-MOSFET have these characteristics,
and are discussed below:
Characteristics of N-Channel E-MOSFET
● Characteristics of n-channel E-MOSFET refers to the curves which relate the current and voltage of device
with each other. There are mainly two types of characteristics in n-channel E-MOSFET:
● Drain Characteristics: These curves provide the relationship between drain current (ID) and drain-to-source
voltage (VDS) shown in Fig2.7 . When different values of drain current and drain-to-source voltage are plotted
on graph, it gives respective values of gate-to-source voltage (VGS). These characteristics are also called as
V-I characteristics of a curve.
● From the graph shown below, it is observed that when the positive value of VGS is increased, the current ID
will also increase. This graph consists of two regions: non-saturated region and saturated region. The non-
saturated region of the curve is also called as ohmic region, in this region when drain current is increased
then subsequently the value of drain-to-source voltage also increases.
● The idealcurrent–voltage characteristics in this region are described by the equation

● Ohmic region lasts till when the value of drain-to-source voltage reaches a threshold value called as
threshold voltage (VTN). After this voltage saturation of n-channel E-MOSFET takes place. Hence, the
region of curve after threshold voltage is achieved is called as saturated region.
● In the saturation region, the ideal current–voltage characteristics for VGS > VT N are
described by the equation

● The parameter Kn is sometimes called the transconduction parameter for the n-channel device.

where W, L, and Cox are the channel width, length, and oxide capacitance per unit area.
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Fig 2.7
● Transfer characteristics: These curves below provide the relationship between drain current (ID) and gate-
to-source voltage (VGS) shown in Fig 2.8. When different values of drain current and gate-to-source voltage
are plotted on X- axis and Y-axis respectively, it provides different values of drain-to-source voltage (V DS).
These curves are also called as transconductance curves.
● From the transfer characteristics of n-channel E-MOSFET shown below it is observed that when
the value of gate-to-source voltage is below the threshold voltage (VTN) then no drain current
flows. When gate-to-source voltage is increased, and it reaches to threshold voltage then drain
current (ID) starts flowing.

Fig 2.8

Characteristics of P-Channel E-MOSFET

● Characteristics of p-channel E-MOSFET refers to the curves which relate the current and voltage
of device with each other. There are mainly two types of characteristics in p-channel E-MOSFET:
Drain Characteristics:
● These curves provide the relationship between drain current (ID) and drain-to-source voltage (VDS) shown in
Fig 2.9. When different values of drain current and drain-to-source voltage are plotted on graph, it gives
respective values of gate-to-source voltage (VGS).
● From the graph shown below, it is observed that when the negative value of VGS is increased,
the current ID will also increase. The graph of p-channel E-MOSFET consists of two regions:
non-saturated region and saturated region. The non-saturated region of the curve is also called
as ohmic region, in this region when drain current is increased then subsequently the value of
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drain-to-source voltage also increases.

● For the p-channel device biased in the nonsaturation region,the current is given by

● In non-saturated or ohmic region Enhancement MOSFET works as amplifiers. Ohmic region lasts till when
the value of drain-to-source voltage reaches a threshold value called as threshold voltage (V TP).
● After this voltage p-channel E-MOSFET works under saturated region. Hence, the region of curve after
threshold voltage is achieved is called as saturated region. In this region Enhancement-MOSFET work
as a voltage-controlled resistor.
● In the saturation region, the current is given by

The parameter Kp is the conduction parameter for the p-channel device and is given by

where W, L, and Cox are the channel width, length, and oxide capacitance per unit
area.

Fig 2.9

● Transfer characteristics: These curves provide the relationship between drain current (ID) and gate-to-source
voltage (VGS) shown in Fig 2.10. When different values of drain current and gate-to-source voltage are plotted on
X- axis and Y-axis respectively, it provides

different values of drain-to-source

voltage (VDS).

Fig 2.10

Depletion type MOSFET

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● Fig 2.10(a) shows the cross section of an n-channel depletion-mode MOSFET.When zero volts are applied to
the gate, an n-channel region or inversion layer exists under the oxide as a result, for example, of impurities
introduced during device fabrication.
● Since an n-region connects the n-source and n-drain, a drain-to-source current may be generated in the
channel even with zero gate voltage. The term depletion mode means that a channel exists even at zero gate
voltage.
● A negative gate voltage must be must be applied to the n-channel depletion-mode MOSFET to turn the
device off.
● Fig2.10(b) shows the n-channel depletion mode MOSFET with a negative applied gate-to-source voltage. A
negative gate voltage induces a space-charge region under the oxide, thereby reducing the thickness of the n-
channel region. The reduced thickness decreases the channel conductance, which in turn reduces the drain
current.
● When the gate voltage is equal to the threshold voltage, which is negative for this device, the induced space-
charge region extends completely through the n-channel region, and the current goes to zero.
● A positive gate voltage creates an electron accumulation layer, as shown in Figure 2.10(c) which increases
the drain current.
● The general iD versus vDS family of curves for the n-channel depletion mode MOSFET is shown in Figure
2.11
● The current–voltage characteristics defined apply to both enhancement- and depletion-mode n-channel
devices. The only difference is that the threshold voltage VTN is positive for the enhancement mode
MOSFET and negative for the depletion-mode MOSFET.
● The conventional circuit symbol for the n-channel depletion-mode MOSFET is shown in Fig 2.12 The
vertical solid line denoting the channel indicates the device is depletion mode.

Fig.2.10C

Fig 2.11 Fig 2.12

CMOS Inverter:
● The CMOS inverter is shown below. It consists of a series connection of a PMOS and an NMOS.
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VDD represents the voltage of logic 1, while the ground represents logic 0.
● Whenever the input is high or 1, the NMOS is switched on while the PMOS is turned off. Thus output Y is
directly connected to the ground and thus comes to be logic 0.
● When the input is logic 0, the reverse happens – NMOS goes off and PMOS goes on. This provides a
direct path between VDD and output Y. Hence Y becomes high. This is the basic principle of operation
of a CMOS inverter.

● From the above analysis, we can infer that for implementing any boolean function using CMOS
technology, we need to make a switching circuit with PMOS switches in the upper block that
turns on when its inputs are low, and NMOS switches in the lower block that turns on when its
inputs are high.
● The two blocks must operate in a complementary sense. The upper block consisting of only
PMOS is called a pull-up network (PUN) because it pulls up the output to VDD or logic high.
The lower block consisting of NMOS is called a pull-down network (PDN) because it pulls
down the output to ground or logic low. Any boolean function can be realized using PUN and
PDN.

SiC based MOSFETS

● Silicon carbide is produced at high temperature combining silica - a form of silicon with carbon.
SiC MOSFET circuit design considerations
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● SiC MOSFETs are now tending to dominate a number of areas of electronic circuit design, especially
within a number of areas of power supply electronics design.
● The fundamental operation of SiC FETs is very similar to that of the more traditional silicon based
MOSFETs, but there are a few design considerations that need to be taken into consideration.
● In many instances the circuit may need a few alterations like
● Gate drive requirements: One of the main areas where SiC MOSFETs differ from their silicon
counter parts is with the gate voltage requirements.
● These devices require a higher gate-to-source voltage to achieve the lowest VDS saturation voltage at
high drain current levels. SiC MOSFETs typically require 15 V to 20 V VGS to achieve low VDS
saturation.
● Specific SiC MOSFET gate driver ICs are available to provide the required gate signals and at the
right voltages.
● Isolation between input and output: Because SiC MOSFETs are used for many power switching
applications, this means that it is necessary to have isolating transformers between the input and
output.
● Electromagnetic interference, EMI: The very much faster switching of SiC MOSFETs can give rise
to electromagnetic interference. As a result this must be considered within the electronic circuit
design of any system using these electronic components.
● Additional source pin: Although many SiC MOSFETs have three connections like any other
MOSFET, some have an extra connection which might be confusing at first sight.

● RDS(ON) variance with temperature: One significant factor with SiC MOSFETs is the low
RDS(ON) figure and the fact that it changes by a fact which can be as little as 1.3 to 1.4 over the
operating temperature range.
● High VDS specification: The high breakdown voltages associated with SiC FETs can bring many
dividends in the electronic circuit design of various items, especially for power supply applications:
switch mode power supplies, voltages converters and power control, etc.
● SiC MOSFETs have a reverse recovery time of ten measured int he low tens of nanoseconds whereas
equivalent high voltage silicon MOSFETs may have times of around three quarters of a millisecond.
● Current density: SiC MOSFETs provide a much higher current density than silicon MOSFETs.
● High temperature operation: Silicon carbide MOSFETs can operate at much higher temperatures than
their silicon equivalents. This means that they can utilise the higher current density that SiC offers without
the need for having to be so aware of the actual device temperature.

GaN MOSFET
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GaN transistor structure & operation

GaN HEMTs
● When the aluminium gallium nitride, AlGaN layer is grown on top of the gallium nitride, GaN
crystal, the interface between the two crystal lattices does not completely match and therefore a strain
is set up.
● The strain induces a 2 dimensional electron gas, 2DEG. This two dimensional electron gas is highly
conductive because the electrons are confined within a very small region at the interface. This
virtually doubles the electron mobility.
● GaN HEMTs are available in both depletion mode and enhancement mode varieties.
Depletion mode GaN transistor
● The basic structure for a depletion mode GaN HEMT consists of the three electrodes, source, drain
and gate as would normally be expected for a field effect transistor.
● The source and drain are fabricated so they do not sit on the AlGaN layer, but instead they contact
directly with the GaN region and hence the 2DEG.

● As this is a depletion mode HEMT, this creates a short circuit between the drain and the source.
● To reduce the flow of electrons through the 2DEG a negative potential is applied to the gate relative
to the drain and source, this depletes the channel of electrons, thereby reducing the channel
conductivity.
Deletion mode GaN HEMTs have also been fabricated using an insulating layer and then depositing a
metal gate onto this.
Enhancement mode GaN transistor
Some of the main structure techniques are described below:
● Implanted gate: One method for creating an enhancement mode GaN FET is to implant fluorine
atoms into the AlGaN barrier layer in the region of the gate. The fluorine atoms create a negative
charge in the AlGaN layer and this depletes the electrons from the 2DEG plane in this region.
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● The Schottky gate on top of this region provides control because when a positive bias is applied,
electrons will be attracted back into the 2DEG plane in this region and current will flow. in the
channel.
● Recessed gate structure: The recessed gate structure is created by thinning the AlGaN barrier region
above the 2DEG plane. This reduces the voltage generated by the piezo-electric effect in this region.
A point is reached where the voltage generated by the stress in the crystal structure is less than the
built in voltage of the Schottky metal gate and with zero bias the 2DEG plane is eliminated here.

● If a positive bias is placed on the gate, electrons are attracted back to the interface between the two
semiconductor material and current is able to flow dependent upon the level of bias.
GaN transistor applications
● Power systems: With everything from switch mode power supplies, power switching, electric
vehicles and the like needing power switching devices, the GaN HEMT lends itself to many of these
applications.
● RF power amplifiers: The combination of high power capability and high speed means that GaN
FET technology is an ideal candidate for RF power amplifiers.
● GaN RF switches: Another application for GaN FETs is as RF switches. There are many situations
where RF switching is required, and these electronic components provide the ideal means of
switching the RF circuitry.
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BIPOLAR JUNCTION TRANSISTOR

3.1 INTRODUCTION
● The transistor is a three terminal device and consists of three distinct layers. Two of them are doped
to give one type of semiconductor and the there is the opposite type, i.e. two may be n-type and one
p-type, or two may be p-type and one may be n-type..
● They are arranged so that the two similar layers of the transistor sandwich the layer of the opposite
type. As a result these semiconductor devices are designated as either PNP transistors or NPN
transistors according to the way they are made up.
● A bipolar junction transistor (BJT) in which operation depends on the interaction of both majority
and minority carriers and hence the name bipolar. It is used as amplifier and oscillator circuits, and as
a switch in digital circuits. It has wide applications in computers, satellites and other modern
communication systems.

Fig 3.1
● The names for the three electrodes widely used but their meanings are not always understood:
Base: The base of the transistor gains its name from the fact that in early transistors, this
electrode formed the base for the whole device. For the operation of the transistor, it is essential
that the base region is very thin. In today's transistors the base may typically be only about 1µm across.
It is the fact that the base region of the transistor is thin that is the key to the operation of the device
Emitter: The emitter gains its name from the fact that it emits the charge carriers.
Collector: The collector gains its name from the fact that it collects the charge carriers.
npn Transistor: Forward-Active Mode Operation
● A transistor can be considered as two P-N junctions placed back to back. One of these, namely the
base emitter junction is forward biased, while the other, the base collector junction is reverse biased.
This configuration called the forward-active operating mode, or simply the active region.
Transistor currents
● Figure 3.2 shows an idealized npn bipolar transistor biased in the forward-active mode. Since the B–E
junction is forward biased, electrons from the emitter are injected across the B–E junction
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Fig 3.2
into the base, creating an excess minority carrier concentration in the base.
● Since the B–C junction is reverse biased, the electron concentration at the edgeof that junction is
approximately zero.
● The base region is very narrow so that, in the ideal case, the injected electrons will not recombine with any
of the majority carrier holes in the base. Because of the large gradient in this concentration, electrons that are
injected, or emitted, from the emitter region diffuse across the base, are swept across the base–collector
space-charge region by the electric field, and are collected in the collector region creating the collector
current.
● Emitter Current: Since the B–E junction is forward biased, the current through this junction to be an
exponential function of B–E voltage.We can then write the current at the emitter terminal as

where the approximation of neglecting the (−1) term is usually valid VBE> VT.in most cases The parameter
VT is the usual thermal voltage. The multiplying constant, IEO, contains electrical parameters of the junction.
Typical values of IEO are in the range of 10−12 to 10−16 A.
● Collector Current
The number of electrons reaching the collector per unit time is proportional to the number of electrons
injected into the base, which in turn is a function of the B–E voltage. To a first approximation, the collector
current is proportional to evBE /VT and is independent of the reverse-biased B–C voltage
We can write the collector current as

● The emitter and collector currents are related by iC = αiE .

● We can also relate the coefficients by IS = αIEO. The parameter α is called the common-base current gain
whose value is always slightly less than unity.
● Base Current
● The base current in a pnp device is the sum of two components. The first component,iB1, comes from

write iB1 ∝ exp(vEB/VT ). The second component, iB2, comes from the flow of electrons supplied through the
electrons flowing from the base into the emitter as a result of the forward-biased E–B junction. We can then

base terminal to replace those lost by recombination with the minority carrier holes injected into the base

so iB2 ∝ exp(vEB/VT ). Therefore the total base current is iB = iB1 + iB2 ∝ exp(vEB/VT ). The direction
from the emitter. This component is proportional to the number of holes injected into the base,

of the base current is out of the base terminal. Since the total base current in the pnp device is an
exponential function of the E–B voltage, we can write

Common-Emitter Current Gain

In the transistor, the rate of flow of electrons and the resulting collector current are an exponential
function of the B–E voltage, as is the resulting base current. This means that
the collector current and the base current are linearly related.
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Therefore, we can write

or

The parameter β is the common-emitter current gain. The value of β is usually in the range of 50 < β < 300.

Current Relationships
If we treat the bipolar transistor as a single node, then, by Kirchhoff’s current law, we have
------(i)
If the transistor is biased in the forward-active mode, then
---(ii)
Substituting (ii) in (i) we will have

we obtain a relationship between the collector and emitter currents as

We can write iC = αiE so

we can state the common-emitter current gain in terms of the common-base current gain:

pnp Transistor: Forward-Active Mode Operation

● The complementary device to npn transistor is the pnp transistor. The flow of holes and electrons in a pnp
device biased in the forward-active mode. Since the B–E junction is forward biased, the p-type emitter is
positive with respect to the n-type base, holes flow from the emitter into the base, the holes diffuse across the
base, and they are swept into the collector.
● The collector current is a result of this flow of holes.Again, since the B–E junction is forward biased, the
emitter current is an exponential function of the B–E voltage. We can write equation for IE as

● The collector current is an exponential function of the E–B voltage, and the direction is out of the collector
terminal, which is opposite to that in the npn device. We can now write

where α is again the common-base current gain.

● The base current in a pnp device is the sum of two components. The first component,iB1, comes from

write iB1 ∝ exp(vEB/VT ). The second component, iB2, comes from the flow of electrons supplied through the
electrons flowing from the base into the emitter as a result of the forward-biased E–B junction. We can then

base terminal to replace those lost by recombination with the minority carrier holes injected

so iB2 ∝ exp(vEB/VT ). Therefore the total base current is iB = iB1 + iB2 ∝ exp(vEB/VT ). The direction
into the base from the emitter. This component is proportional to the number of holes injected into the base,

of the base current is out of the base terminal. Since the total base current in the pnp device is an
exponential function of the E–B voltage, we can write
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● The relationships between the terminal currents of the pnp transistor are exactly the same as those of the npn
transistor and are summarized in Table below

Table 3.1

Current–Voltage Characteristics
● Figures 3.3(a) and 3.3(b) are common-base circuit configurations for an npn and a pnp bipolar transistor,
respectively. The current sources provide the emitter current.
● The collector current iC was nearly independent of the C–B voltage as long as the B–C junction was reverse
biased. When the B–C junction becomes forward biased, the transistor is no longer in the forward-active
mode, and the collector and emitter currents are no longer related by iC = αiE .
● Figure 3.4 shows the typical common-base current–voltage characteristics. When the collector–base junction
is reverse biased, then for constant values of emitter current, the collector current is nearly equal to iE.

Fig 3.3 Fig 3.4

● The common-emitter circuit configuration provides a slightly different set of current–voltage characteristics,
as shown in Figure 3.6.
● For these curves, the collector current is plotted against the collector–emitter voltage, for various constant
values of the base current. These curves are generated from the common-emitter circuits shown in Figure 3.5.
● In this circuit, the VBB source forward biases the B–E junction and controls the base current iB. The C–E
voltage can be varied by changing VCC.
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Fig 3.5 Fig 3.6

● Fig 3.7 shows current–voltage characteristics plotted for constant values of the B–E voltage. The curves are
theoretically linear with respect to the C–E voltage in the forward-active mode.
● The slope in these char acteristics is due to an effect called base-width modulation. The phenomenon is
generally called the Early effect. When the curves are extrapolated to zero current, they meet at a point on the
negative voltage axis, at vCE =−VA.
● The voltage VA is a positive quantity called the Early voltage.

Fig 3.7
● For a pnp transistor, this same effect is true except the voltage axis is vEC.
● The linear dependence of iC versus vCE in the forward-active mode can be described by

here IS is assumed to be constant. This output resistance is determined from