45 HOURS LECTURE SCHEDULE

Unit Lecture schedule Hours

No.
Unit 1 Introduction to ARM architecture family, Condition Flags, Reset, Register set 3
ARM Core Dataflow model, ARM 3 stage and 5-stage pipeline organization 2
Unit 2 ARM Instruction Set 11
ARM Assembly Language Programming Examples 1.5
Thumb Instructions, ARM interrupt Processing and handling schemes 5.5
Unit 3 ARM coprocessor interface and Instructions, Floating Point Format and VFP 6
Unit 4 Memory hierarchy- Cache Memory Organization in ARM 5
Memory Protection Units (MPU), Virtual Memory, Memory Mgt (MMU) in 4
ARM
Unit 5 Architectural support for System Development, ARM programming tools 3
AMBA architecture (ASB, AHB, APB) 1
Peripherals (DMA, RTC, ADC, DAC and PWM) 1
I2C and SPI protocols , USART and GPIO 1
Other ARM Processor cores (ARM9, ARM10, ARM11) and Advanced 1
Features
Total 45

IITM NPTEL Seer IESA Project

45 HOURS LECTURE PLAN: Back

45 Hours Lecture Plan

Learning
Session Topics Covered Hours Outcome
1 Types of computer Architectures, ISA's and ARM History 1 L1,L2
Embedded System Software and Hardware, stack implementation in ARM, L3,L4
2 Endianness, condition codes 1
Processor core VS CPU core, ARM7TDMI Interface signals, Memory L1,L3,L4,L6
3 Interface, Bus Cycle types, Register set, Operational Modes 1
Instruction Format, ARM Core Data Flow Model, ARM 3 stage Pipeline, L3,L4,L6
4 ARM family attribute comparision 1
ARM 5 stage Pipeline, Pipeline Hazards, Data forwarding - a hardware L3,L4,L6
5 solution 1
ARM ISA and Processor Variants, Different Types of Instructions, ARM L3,L4,L6
6 Instruction set, data processing instructions 1
Shift Operations, shift Operations using RS lower byte, Immediate value L1,L2,L3
7 encoding 1.5
8 Dataprocessing Instructions 1 L1,L2,L3
9 AddressingMode-1, Addressing Mode -2 1 L1,L2,L3
10 Addressing Mode -2, LDR/STR, Addressing mode -3 with examples 1.5 L1,L2,L3
11 Instruction Timing, Addressing Mode - 4 with Examples 1.5 L1,L2,L3
12 Swap Instructions, Swap Register related Instructions, Loading Constants 1 L1,L2,L3
Program Control Flow, Control Flow Instructions, B & BL instructions, BX L1,L2,L3
13 instruction 1
14 Interrupts and Exceptions, Exception Handlers, Reset Handling 1.5 L1,L2,L3
15 Aborts, software Interrupt Instruction, undefined instruction exception 1.5 L1,L2,L3
16 Interrupt Latency, Multiply Instructions, Instruction set examples 1 L1,L2,L3,L5
Thumb state, Thumb Programmers model, Thumb Implementation, Thumb L1,L2,L3,L5
17 Applications 1
18 Thumb Instructions, Interrupt processing 1.5 L1,L2,L3,L5
19 Interrupt Handelling schemes, Examples of Interrupt Handlers 2 L1,L2,L3,L5
20 Coprocessors 1.5 L3,L5,L6
Coprocessor Instructions, data Processign Instruction, data transfers, L3,L5,L6
21 register transfers 1.5
22 Number representations, floating point representation 1.5 L3,L5
Flynn's Taxonomy, SIMD and Vector Processors, Vector Floating Point L3,L5
23 Processor (VFP), VFP and ARM interactions, An example vector operation 1.5
Memory Technologies, Need for memory Hierarchy, Hierarchical Memory L3,L4
24 Organization, Virtual Memory 1.5
25 Cache Memory, Mapping Functions 2 L3,L4
Cache Design, Unified or split cache, multiple level of caches, ARM cache L3,L4
26 features, coprocessor 15 for system control 1.5

IITM NPTEL Seer IESA Project

 Processes, Memory Map, Protected Systems, ARM systems with MPU, L3,L4
27 memory Protection Unit (MPU) 1.5
28 Physical Vs Virtual Memory, Paging, Segmentation 1 L3,L4
MMU Advantage, virtual memory translation, Multitasking with MMU, L3,L4,L5,L6
29 MMU organization, Tightly coupled Memory (TCM) 1.5
ARM Development Environment, Arm Procedure Call Standard (APCS), L3,L5,L6
30 Example C program 2
Embedded software Development, Image structure, linker inputs and L3,L5,L6
31 outputs, memory map, application startup 1
AMBA Overview, Typical AMAB Based Microcontroller, AHB bus features, L3,L5,L6
32 AHB Bus transfers, APB bus transfers, APB bridge 1
33 DMA, Peripherals, Programming Peripherals in ARM 1 L3,L5,L6
34 Protocols (I2c, SPI), UART, GPIO 1 L3,L5,L6
35 ARM ISAs, ARMv5, ARMv6, ARM v7, big.little technology, ARMv8 1 L3,L5,L6
45

IITM NPTEL Seer IESA Project