PLL

Phase locked loops are used as modulators, demodulators, oscillators, synthesizers, clock signal recovery
circuits and the list goes on.
Phase refers to the relative phase difference between an input signal and the loop’s internal oscillator.
Locked means that the oscillator’s phase maintains a constant relationship of that of the input signal. This
also means the frequencies of the two signals are the same, otherwise the phase difference would change.
Loop comes from the feedback loop that controls the internal oscillator’s frequency to remain in sync with
that of the input signal.
Feedback is key to the PLL’s function.
The PLL has three basic components, seen in Figure 1 — the phase detector, the loop filter and a voltage-
controlled oscillator (VCO). The output from the phase detector (Ve(t) in Figure 1) is a signal that contains
the frequency and phase difference between the input signal and VCO output. The loop filter creates the
VCO control voltage based on the difference signal. The VCO changes frequency in response to the control
voltage until the two frequencies are the same.

Figure 1

QUALITATIVE CHARACTERIZATION OF LOOP COMPONENTS

Phase detector (PD):
• Analog multiplier for analog PLL(APLL)
• PD produces an error signal that is proportional to the phase error,
i.e., to the difference between the phases of input and output signals
of the phase-locked loop
Loop filter:
• Low-pass filter
• It is characterized by its transfer function F(s)
• Low-pass filter suppresses the noise and unwanted PD outputs. It
determines the dynamics of phase-locked loop
Voltage-controlled oscillator (VCO):
• VCO generates a sinusoidal signal
• The instantaneous VCO frequency is controlled by its input voltage
Type of PLL
There are several variations of PLLs. Some terms that are used are analog phase-locked loop (APLL) also
referred to as a linear phase-locked loop (LPLL), digital phase-locked loop (DPLL), all digital phase-
locked loop (ADPLL), and software phase-locked loop (SPLL).
Analog or linear PLL (APLL)
Phase detector is an analog multiplier. Loop filter is active or passive. Uses a voltage-controlled
oscillator (VCO).
Digital PLL (DPLL)
An analog PLL with a digital phase detector (such as XOR, edge-trigger JK, phase frequency detector).
May have digital divider in the loop.
All digital PLL (ADPLL)
Phase detector, filter and oscillator are digital. Uses a numerically controlled oscillator (NCO).
Software PLL (SPLL)
Functional blocks are implemented by software rather than specialized hardware.
Neuronal PLL (NPLL)
Phase detector, filter and oscillator are neurons or small neuronal pools. Uses a rate controlled
oscillator (RCO). Used for tracking and decoding low frequency modulations (< 1 kHz), such as those
occurring during mammalian-like active sensing.

The VCO is a special type of oscillator that has a frequency controlled by an applied voltage. The frequency
of the VCO without any control signal applied is called the free-running frequency, f0.

The phase detector is just that — a type of mixer.

 A PD is a circuit that senses two periodic inputs and produces an output whose
average value is proportional to the difference between the phases of the inputs
 The input/output characteristic of the PD is ideally a straight line, with a slope called
the “gain” and denoted by KPD

As one familiar circuit example, an analog multiplier or mixer can be used as a phase detector. Recall
that the mixer takes the product of two inputs. v (t) = A(t)B(t). If,
e

Since the two inputs are at the same frequency when the loop is locked, we have one output at twice
the input frequency and an output proportional to the cosine of the phase difference. The doubled
frequency component must be removed by the low-pass loop filter. Any phase difference then shows
up as the control voltage to the VCO, a DC or slowly varying AC signal after filtering.
After LPF
|KPD| is maximum at φ=π/2 and is zero at φ= 0 and π

Vav

Figure 2

When an input signal is applied to the PLL, the phase comparator compares the phase and frequency of the
signal input with the VCO frequency and generates an error voltage proportional to the phase and frequency
difference of the input signal and the VCO. The error voltage, Ve(t), is filtered and applied to the control
input of the VCO. Ve(t) varies in a direction that reduces the frequency difference between the VCO and
signal-input frequency. When the input frequency is sufficiently close to the VCO frequency, the closed-
loop nature of the PLL forces the VCO to lock in frequency with the signal input; i.e., when the PLL is in
lock, the VCO frequency is identical to the signal input, except for a finite phase difference.
This changing voltage causes the VCO to respond very quickly, reducing the difference between the VCO
and input frequencies. Consequently, the loop filter’s output voltage is also reduced, making smaller and
smaller changes in the VCO frequency. Within a short time (typically a few milliseconds for RF PLLs) the
VCO frequency is equal to that of the input signal and the loop is “locked.” Any change in either the PLL
input or VCO frequencies is tracked by a change in the loop filter output, keeping the two frequencies the
same.
This process of adjust and hold is called capture. The minimum and maximum input frequencies to which
the loop can move the VCO as it captures an input signal is called the capture range as shown in Figure 3.
The segments of the capture range above and below f0 are called the pull-in range.
As the control signal is proportional to the cosine of the phase difference, it will be zero when the phase
difference is 90° (cos 90° = 0). It will be a maximum when the two signals are in phase (cos 0° = 1) or out
of phase (cos 180° = –1). This defines the range over which the PLL can keep the input and VCO
frequencies locked together. As the input frequency moves farther and farther from f 0, the VCO’s free-
running frequency, the loop’s control action will keep the VCO frequency the same as the input frequency,
but with a phase difference that gets closer to 0 or 180°, depending on which direction the input frequency
changes. If the input frequency has moved so far that the phase difference between it and the VCO
frequency is either 0 or 180°, any further change will cause the control signal to move back toward its 90°
value and the VCO frequency away from the input signal. The loop is no longer locked and the input and
VCO frequencies are no longer the same. The range of input frequencies between the value at which the
loop is locked with a phase difference of 0° and 180° is called the loop’s lock range. The lock range above
and below f0 are called the loop’s hold ranges. The lock range is not always centered on f0.
The phase difference φ generates a corrective control voltage vc to shift the VCO frequency from f0 to fi
and thereby maintain the lock. Once locked, PLL tracks the frequency changes of the input signal. Thus, a
PLL goes through three stages (i) free running, (ii) capture and (iii) locked or tracking.

Figure 3

Two key parameters of a PLL system are its lock and capture ranges. They can be defined as follows :

The range of input frequencies between the value at which the loop is locked with a phase difference of 0°
and 180° is called the loop’s lock range.
The lock and capture ranges of a PLL can be illustrated with reference to the following figure, which shows
the typical frequency-to-voltage characteristics of a PLL. In the figure, the input is assumed to be swept
slowly over a broad frequency range. The vertical scale corresponds to the loop-error voltage.

Figure 4
In the upper part of the above figure, the loop frequency is being gradually increased. The loop does not
respond to the signal until it reaches a frequency f1, corresponding to the lower edge of the capture range.
Then, the loop suddenly locks on the input, causing a negative jump of the loop-error voltage. Next, Vd
varies with frequency with a slope equal to the reciprocal of the VCO voltage-to-frequency conversion gain,
and goes through zero as fs = fo. The loop tracks the input until the input frequency reaches f2, corresponding
to the upper edge of the lock range. The PLL then loses lock, and the error voltage drops to zero.

If the input frequency is now swept slowly back, the cycle repeats itself as shown in the lower part of the
preceding figure. The loop recaptures the signal at f3 and traces it down to f4. The frequency spread between
(f1, f3) and (f2, f4) corresponds to the total capture and lock ranges of the system; that is, f3 - f1 = capture
range and f4 - f2 = lock range. The PLL responds only to those input signals sufficiently close to the VCO
frequency fo to fall within the lock or capture range of the system. Its performance characteristics, therefore,
offer a high degree of frequency selectivity, with the selectivity characteristics centered about fo.

Lock Range. Range of frequencies in the vicinity of fo, over which the PLL can maintain lock with an input
signal. It is also known as the tracking or holding range. Lock in range is limited by the output of the PD.
Lock range increases as the overall gain of the PLL is increased bw is reduced. This effect is also called
steady-state stability.

Capture Range. Band of frequencies in the vicinity of fo where the PLL can establish or acquire lock with
an input signal. It is also known as the acquisition range. It is always smaller than the lock range, and is
related to the low-pass filter bandwidth. It decreases as the filter bandwidth is reduced. This effect is also
called a transient stability.

14 pin IC: 565 PLL

IC 566 VCO

R A Gayakwad