NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

MICROPROCESSOR:- A microprocessor is a multipurpose

programmable clock driver register based semiconductor device,
manufactured by using VLSI technique to perform all computation in
digital computer. It is denoted by the symbol µp, Very Large-Scale
Integration(VLSI).

MICRO COMPUTER:- The integration of microprocessor, memory

and input output devices is called Microcomputer.

BIT:- A binary digit 0 or 1 is known as Bit.

NIBBLE:-Group of 4 half byte.
BYTE:- A group of 8 bits.
WORD:- A group of bits that computer recognized and processes at
the same time.
APPLICATIONS OF MICROPROCESSOR
1. Word processing
2. Reservation of airlines and railways
3. Industrial and commercial application
4. Use of computer in graphics
5. Use of computer far data analysis
6. Use of computer in DBMS
7. Use of computer in banks
 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

ADVANTAGES OF MICROPROCESSOR

1. It performs all types of computation.

2. High speed data processes and it controls the data.
3. Intelligence has been bought to the system.
4. Automation of industrial process and office automation.
5. Mare flexible.
6. Compact in size.
7. Easy of maintenance.

DISADVANTAGES OF MICROPREOCESSOR

1. It might get overheated.

2. It imposes on the size of the data.

SCHEMATIC DIAGRAM OF DIGITAL COMPUTER SYSTEM

 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

1. Input unit
2. Control processing unit(CPU)
• ALU
• Timing and control unit
• Registers
3. Memory unit
4. Output unit

KEY FEATURES OF 8085 MICROPROCESSOR

➢ 8085 is an 8-bit microprocessor.

➢ Manufacture with MOS technology[Metal Oxide
Semiconductor]
➢ It has 16-bit address bus, it can support upto 216 =65,536 bytes
(64k) through 𝐴16 − 𝐴0 .
➢ The first 8 lines of address bus and 8 lines of data bus are
multiplex 𝐴𝐷7 − 𝐴𝐷0.
➢ It supports external interrupt request.
➢ It has 16-bit program counter.
➢ It has 16-bit stack pointer.
➢ It has six 8 bits general purpose register are available in pairs.
➢ This 8085 microprocessor operates with power supply +5v and
runs 3.2MHZ.
➢ 8085 microprocessor has 40pins DIP[Dual Inline Package].
 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

THE REGISTER OF 8085 MICROPROCESSOR

1. ACCUMULATOR:-
• The accumulator is an 8-bit register which is denoted by A.
• It is used as input to the ALU for any arithmetic or logical
operations.
• After arithmetic or logical operation from the ALU is
completed the output will be stored in accumulator itself.

2. GENERAL PURPOSE REGISTER:-

• The general-purpose register is identified as B,C,D,E,H,L.
• These are used to store 8-bit data during the program execution.
• They can combine as register pairs to perform 16-bit operations.

3. STACK POINTER:-
• It is a 16 bit register and used as a memory pointer which is
linked to a memory location called as Stack,
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MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

• This stack can be used for read and write data into memory
location.

4. PROGRAM COUNTER:-
• It is a 16-bit register used as a memory pointer. The program
counter holds the address of starting memory location of set of
instructions.
• The program counter will be incremented each time when the
opcode is fetched the program counter will be incremented.

FLAG REGISTER OF 8085 MICROPROCESSOR(8 BIT)

 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

The 8085 microprocessor uses 5 flag registers to check the result

conditions in the accumulator. They are:-
1. Sign flags(S)
2. Zero flags(Z)
3. Auxiliary flags(AC)
4. Parity flags(P)
5. Carry flags(Cy)

1. SIGN FLAGS:- After execution of any arithmetic and logical

operation. If D7 after the result in the accumulator is 1 then the
sign flag is set (S=1) otherwise it will be result (S=0). The D7 is
reserved for indicating the sign of the number.
• If S=0 the number in the accumulator is positive.
• If S=1 the number in the accumulator is negative.

2. ZERO FLAGS:- If the result of arithmetic and logical operator

is 0, then zero flag is set otherwise it is reset. To check the
content of the accumulator for 0 or non-zero numbers you
should refer the zero flag.
• Z=0 → Non-zero number.
• Z=1 →Content of accumulator is zero.

3. AUXILIARY CARRY FLAGS:- In an arithmetic operation

when a carry is generated by digit D3 and passed on to digit D4
the auxiliary carry flag is set(AC) otherwise it is reset.
• If AC=0 → Carry mot generated from D3 to D4.
• If AC=1 → Carry occurred from D3 to D4.
 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

4. PARITY FLAGS:- If the result of the arithmetic and logical

operation from the ALU contains even number of 1’s then the
parity flag is set otherwise it is reset.
• If P=0 → Odd parity
• If P=1 → Even parity

5. CARRY FLAGS:- If the result of the arithmetic operation is in

carry, then the carry flag is set otherwise it is reset.
• If Cy=0 →No carry
• If Cy=1 →Carry
SYSTEM BUS OF 8085 MICROPROCESSOR
System bus are group of lines which are used to connect peripheral
and memory devices to CPU are microprocessor. There are 3 types of
buses. They are:-
1. Address bus
2. Data bus
3. Control bus
 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

1. ADDRESS BUS:-
• An address bus is a group of 16 lines identified as 𝐴0 −
𝐴15 and the address bus is unidirectional because the bits
flow from microprocessor to peripheral devices or memory
device in single direction.
• That identifies memory location upto 216 =65,536 (64k)
kilo bytes of memory location.
• This memory location ranges from 000H to FFFFH.
2. DATA BUS:-
• The data bus is a group of 8 lines identified as 𝐷0 −
𝐷7 and the data bus is bidirectional because it carries
8 bits of data between microprocessor and external
units [ I/O and memory devices].
• The data bus ranges from 00H to FFH.
3. CONTROL BUS:-
• The control bus contains various single lines which
have specific function for co-ordinating and
controlling µp operations.
• The µp generates various signals such as memory
read/write or I/O read/write control signals and its
signals are carried out by specific control lines.
 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

ARCHITECTURE OF 8085 MICROPROCESSOR

The architecture of 8085 consist of 7 main sections. They are:-

1. Arithmetic and logic unit (ALU)
2. Register section
3. Instruction register and decoder
4. Timing and control section
5. Serial input and output control
6. Interrupt control
7. Address bus and address/data bus
1. ARITHMETIC AND LOGICAL UNIT:- Arithmetic
and logic unit is a main section of the 8085 µp which deals
with all the computing operations carried out by the
instruction decoder with the help of accumulator,
temporary register, flag flip flops etc.
 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

2. REGISTER SECTION:-Register section of 8085 µp

consist of six [8 bit] general purpose registers and two
special purpose [16 bit] register known as Program counter
and Stack pointer.

3. INSTRUCTION REGISTER AND DECODER:- They

are the parts of ALU .When 8085 µp fetches instructions
from its memory for execution it needs to be converted
into opcode and this section produces necessary control
signals using timing and control unit.

4. TIMING AND CONTROL SECTION:- It is a section of

CPU which generates timing and control signals which
are necessary to communicate with memory and I/O
devices.

5. SERIAL INPUT AND OUTPUT CONTROL:- This

unit uses SID(Serial Input Data) and SOD(Signal Output
Data) controls signals for serial data transmission because
some of the I/O devices uses serial data stream to send the
input. This control unit converts serial data stream to
parallel data and stores into the accumulator.

6. INTERRUPT CONTROL UNIT:- This unit controls

necessary to transfer data between µp peripheral devices
the processor will discontinue temporarily and attend
peripheral device’s request after completing peripheral
devices work it will get back to the actual process.

7. ADDRESS BUS AND ADDRESS/DATA BUS:- A

address bus is a group of 16 lines identified as 𝐴0 − 𝐴15
 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

and the address bus is unidirectional because the bits flow

from µp to peripheral devices in single direction. That
identifies memory location upto 216 =65,536 (64k) kilo
bytes of memory location. Memory location ranges from
0000H to FFFFH.

SCHEMATIC DIAGRAM OF DEMULTIPLEXED ADDRESS

AND DATA BUS WITH CONTROL SIGNALS
 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

PIN CONFIGURATION OF 8085 MICROPROCESSOR

POWER SUPPLY AND FREQUENCY SIGNALS:-

• Intel 8085 is an 8-bit microprocessor is designed and created
using NMOS technology with 40pin DIP.
• It requires +5v DC power supply for its operation and its clock
speed is 3MHZ.
• It is capable to address 64KB of memory.
• 8085 pins are classified into 6 groups. They are:-
1. Power supply and frequency signal
2. Address bus
3. Multiplexed address/data bus
4. Control and status signal
 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

5. Externally initiated signals

6. Serial I/O parts

1. POWER SUPPLY AND FREQUENCY SIGNALS:-

8085 µp needs single +5v DC power supply and a clock
frequency of 3MHZ, which can be obtained by connecting
6MHZ crystal oscillation between the class 𝑥1and 𝑥2 .

2. ADDRESS BUS(HIGH ORDER):- 8085 µp uses higher

order 8-bit address bus (𝐴8 − 𝐴15) to address the most
significant 8 bits of memory location ranging from 0100H
to FFFFH. These lines are unidirectional so CPU uses
these lines to address the higher order memory location for
read/write data.

3. MULTIPLEXED ADDRESS/DATA BUS:- For reading

lower 8 bit of address 𝐴0 − 𝐴7 lines are used but the lower
8 bit address lines are multiplexed with 8 bit data bus so
they are called as 𝐴𝐷7 − 𝐴𝐷0 to use same 8 lines for dual
propose. Demultiplex latch has been provided in between
these two buses so that it can address least significant 8-bit
address of the memory locations.

4. CONTROL AND STATUS SIGNAL:- This section has

3 control signals ALE,𝑅𝐷̅̅̅̅ and ̅̅̅̅̅
𝑊𝑅 [read, write] and as 3
status signals IO/ are active low signals that is this signal
will get low at the time of read or write operation.
• ̅̅̅̅̅̅
𝐀𝐋𝐄:- address latch enable this signal is used
to demultiplex address/data bus, this signal
goes high during the first clock cycle.
 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

At the end of the first clock cycle ale signal

goes low for the multiplex of 𝐴𝐷7 − 𝐴𝐷0
becomes data bus 𝐷7 − 𝐷0.
• ̅̅̅̅:- It is an active low read signal and this
𝐑𝐃
signal goes low the microprocessor read data
from I/O or memory.
• ̅̅̅̅̅
𝐰𝐑:- It is an active low write signal when this
signal when this signal goes low the data on
the data bus are return into a I/O are memory
devices.
• IO/𝐌 ̅ :- This signal which indicates whether
the operation is belongs to memory or I/O
devices.
If the signal goes high it belongs to I/O
operation else it is memory operation.
• 𝐬𝟎 𝐚𝐧𝐝 𝐬𝟏 They are output status signal used
to identify the various I/O operation of the µp.

̅
IO/𝐌 ̅̅̅̅̅̅) 𝐬𝟏
(𝐰𝐑 ̅̅̅̅̅̅̅𝐬𝟎
(𝐑𝐃) Operations
0 0 0 HALT
0 0 1 Memory write
0 1 0 Memory read
1 0 1 I/O Write
1 1 0 I/O Read
0 1 1 Opcode fetch
1 1 1 Interrupt acknowledge

5. EXTERNALLY INITIATED SIGNALS:-

• READY:- It is an active high input signals
and it goes high during read/write cycle. That
indicates the memory or I/O devices is ready
 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

to send or receive the data. If this signal goes

low the µp must wait till it goes to high.
• HOLD:- When this signal goes high then the
DMA [Direct memory access] is requesting to
use address/data bus. It indicates this signal
that another master process is requesting to
use address and data bus.
• HLDA [Hold acknowledge]:- It is an output
signal which acknowledges the hold request.
The HLDA signal request goes high when
hold request acknowledges. After the removal
of hold request the HLDA goes low.
• ̅̅̅̅̅̅̅̅̅̅̅̅
𝐑𝐄𝐒𝐄𝐓 𝐈𝐍:- When this signal goes low the
program counter is set to 0.
• RESET OUT:- This signal goes high when
resetting is in progress, this signal can also be
used to reset the memory and I/O devices.
• INTR [INPUT]:- This signal goes high when
resetting is in progress, this signal can also be
used to reset the memory and I/O devices.
• INTA [OUTPUT]:- Interrupt acknowledge
goes low when an interrupt arrives into the
µp.
• RST 7.5,6.5 AND 5.5 [INPUTS]:- This pins
are also called as maskable restart interrupts,
this interrupts is used to transfer the program
control to specific memory location.
• TRAP [INPUT]:- It is a non-maskable
interrupt and has the highest priority. When
this signal arrives to the CPU, the processor
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MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

saves the content of program counter into the

stack and control goes to 24H address.

6. SERIAL I/O PARTS:-

• SID
• SOD
When RIM instruction is executed then 7 th bit of the accumulator is
loaded with the data on SID line [read interrupt mask].
When SIM [Set interrupt mask] instruction is executed then 7 th bit
of the accumulator is placed on SOD line.
TIMING DIAGRAM

1. INSTRUCTION LINE/CYCLE:- The time taken to

compare the execution of one instruction. One instruction
cycle consists of 1-6 machine cycle.
2. MACHINE CYCLE:- The time required to access the
memory or I/O devices is called as Machine cycle. One
machine cycle consists of 3-6 T-states.
3. T-STATES:- A portion of an operation carried out in one
system clock period is called as T-states. Opcode fetch
requires 4 T-states by the 8085 µp. Memory read write
operation requires 3 T-states by the 8085 µp.
Instruction cycle contains 2 cycles. They are:-
1. Fetch cycle
2. Execute cycle

1. FETCH CYCLE:-The time required to fetch an

opcode from the memory is called as Fetch cycle. It
requires 4 T-states or 6 T-states.
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MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

2. EXECUTE CYCLE:- The time required to execute

the instruction after decoding is done. It requires the
time required for execute cycle depends on the
instructions.
IO/𝐌̅ 𝐬𝟏 𝐬𝟎 ̅̅̅̅
𝐑𝐃 ̅̅̅̅̅
𝐰𝐑 Operations
0 0 1 1 0 Memory write
0 1 0 0 1 Memory read
1 0 1 1 0 I/O write
1 1 0 0 1 I/O read
0 1 1 0 1 Opcode fetch
 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

TIMING DIAGRAM FOR OPCODE FETCH OPERATION

Status signal Control signal Operations

IO/𝐌̅ 𝐬𝟏 𝐬𝟎 ̅̅̅̅
𝐑𝐃 ̅̅̅̅̅
𝐰𝐑
0 0 1 1 0 Memory write
0 1 0 0 1 Memory read
1 0 1 1 0 I/O write
1 1 0 0 1 I/O read
0 1 0 1 1 Opcode fetch
 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

TIMING DIAGRAM FOR MEMORY READ

Status signal Control signal Operations

IO/𝐌̅ 𝐬𝟏 𝐬𝟎 ̅̅̅̅
𝐑𝐃 ̅̅̅̅̅
𝐰𝐑
0 0 1 1 0 Memory write
0 1 0 0 1 Memory read
1 0 1 1 0 I/O write
1 1 0 0 1 I/O read
0 1 0 1 1 Opcode fetch
 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

TIMING DIAGRAM FOR MEMORY WRITE

TIMING DIAGRAM FOR I/O READ

 NRUPATHUNGA G, HOD BCA DEPT, GTIMSR BANGALORE SUNKADAKATTE

MICROPROCESSOR ARCHITECTURE AND ITS

OPERATION

TIMING DIAGRAM FOR I/O WRITE