CPE 203: INTRODUCTION TO

DIGITAL COMPUTER SYSTEMS

CLASS NOTE 1a
Ninan O. D.
Department of Computer Science & Engineering
Obafemi Awolowo University
 Addition Operations
• OBJECTIVES
• At the end of this lecture, you will be able to:
- Perform binary addition, subtraction, multiplication, and division on
two binary numbers
- Manipulate signed binary numbers using the 2’s-complement system.
- Understand the BCD addition process.
- Describe the basic operation of an arithmetic/logic unit.
• Digital computers and calculators perform the various arithmetic operations
on numbers that are represented in binary form.
• addition of two binary numbers is performed in exactly the same manner as
the addition of decimal numbers.

• The least-significant-digit (LSD) position is operated on first, producing a sum

of 7.
• The digits in the second position are then added to produce a sum of
13,which produces a carry of 1 into the third position.This produces a sum of
8 in the third position.
• The same general steps are followed in binary addition.
• However, only four cases can occur in adding the two binary digits (bits) in
any position.

• The last case occurs when the two bits in a certain position are 1 and there is
a carry from the previous position. examples of the addition of two binary
numbers.

• in all digital systems the circuitry that actually performs the addition can
handle only two numbers at a time.
• When more than two numbers are to be added, the first two are added
together and then their sum is added to the third number, and so on.
• Addition is the most important arithmetic operation in digital systems
• Most modern digital computers and calculators actually use only addition as
their basic operation.
 REPRESENTING SIGNED NUMBERS
• In digital computers, the binary numbers are represented by a set of binary
storage devices (e.g., flip-flops). Each device represents one bit. For
example, a six-bit FF register can store binary numbers ranging from 000000
to 111111 (0 to 63 in decimal). This represents the magnitude of the
number.
• Since most digital computers and calculators handle negative as well as
positive numbers, some means is required for representing the sign of the
number (1 or 2). This is usually done by adding to the number another bit
called the sign bit.
• In general, the common convention is that a 0 in the sign bit represents a
positive number and a 1 in the sign bit represents a negative number.
• The circuit implementation of the sign-magnitude system is more complex
than in other systems, calculators and computers do not normally use it

•
 1’s-Complement Form
• The 1’s complement of a binary number is obtained by changing each 0 to a 1
and each 1 to a 0. In other words, change each bit in the number to its
complement. E.g. the 1’s complement of 101101 is 010010.

2’s Complement Form

• The 2’s complement of a binary number is formed by taking the 1’s
complement of the number and adding 1 to the least-significant-bit position.

010011 is the 2’s complement representation of 101101.

• Another example of converting a binary number to its 2’s-complement
representation:

• The 2’s-complement system is used to represent signed numbers because, it

allows us to perform the operation of subtraction by actually performing
addition.
• This is significant because it means that a digital computer can use the same
circuitry both to add and to subtract, thereby realizing a saving in hardware.
The 2’s-complement system for representing signed numbers:
• If the number is positive, the magnitude is represented in its true binary form,
and a sign bit of 0 is placed in front of the MSB.
• If the number is negative, the magnitude is represented in its 2’scomplement
form, and a sign bit of 1 is placed in front of the MSB.
 Sign Extension
• The size of a register (number of flip-flops) determines the number of binary
digits that are stored for each number.
• The storage registers is made up of 4, 8, 12, 16, 32, or 64 bits.
• In a system that stores eight-bit numbers, seven bits represent the
magnitude and the MSB represents the sign.
• If we need to store a positive five-bit number in an eight-bit register, we
simply add leading zeros. The MSB (sign bit) is still 0, indicating a positive
value. E. g binary value for 9 is 000 0 1001.
• To store five-bit negative numbers in an eight bit register, e. g the five-bit,
2’s-complement binary representation for -9 is 1 0111.
• If we appended leading 0s, this would no longer be a negative number in
eight-bit format. The proper way to extend a negative number is to append
leading 1’s. Such that for -9 is 111 1 0111.
 Negation
• Negation is the operation of converting a positive number to its negative
equivalent or a negative number to its positive equivalent.
• When signed binary numbers are represented in the 2’s-complement system,
negation is performed simply by performing the 2’s-complement operation.

• This negation changes the number to its equivalent of opposite sign.

• Whenever a signed number has a 1 in the sign bit and all 0s for the
magnitude bits, its decimal equivalent is 2N , where N is the number of bits
in the magnitude. For example,
1000 = 23 = - 8
10000 = 24 = - 16
100000 = 25 = - 32

• Note that in this special case, taking the 2’s complement of these numbers
produces the value you started with.
• If you extend the sign of these special numbers, the normal negation
procedure works.
• For example, extending the number 1000 (-8) to 11000 (five-bit negative 8)
and taking its 2’s complement you get 01000 (8), which is the magnitude of
the negative number.
• We can then state that the complete range of values that can be represented
in the 2’s-complement system having N magnitude bits is

• There are a total of 2N+1 different values, including zero.

• For example, Table in the next slide lists all signed numbers that can be
represented in four bits using the 2’s-complement system (note there are
three magnitude bits, so N = 3). Note that the sequence starts at -2N = -23
= - 810 = 10002 and proceeds upward to +(2N - 1 ) = +23 - 1 = +710 = 01112
by adding 0001 at each step as in an up counter.
• Decimal Value Sign Binary Using 2’s Complement
 ADDITION IN THE 2’s-COMPLEMENT SYSTEM
• I: Two Positive Numbers. E. g. +9 and +4.

• Note that
1. the sign bits of the augend and the addend are both 0 and the sign bit of
the sum is 0, indicating that the sum is positive.
2. the augend and the addend are made to have the same number of bits.
• II: Positive Number and Smaller Negative Number. E, g, +9 and -4,

• In this case, the sign bit of the addend is 1. Note that the sign bits also
participate in the addition process.
• III: Positive Number and Larger Negative Number.
•

• The sum here has a sign bit of 1, indicating a negative number. Because the
sum is negative, it is in 2’s-complement form, so that the last four bits, 1011,
actually represent the 2’s complement of the sum.
• To find the true magnitude of the sum, you must negate (2’s-complement)
11011, the result is 00101 = +5.
• IV: Two Negative Numbers. -9 and -4,

• This final result is again negative and in 2’s-complement form with a sign bit
of 1.
• V: Equal and Opposite Numbers, +9 and -9,
 SUBTRACTION IN THE 2’s-COMPLEMENT SYSTEM
• When subtracting one binary number (the subtrahend) from another binary
number (the minuend),
1. Negate the subtrahend. This will change the subtrahend to its equivalent
value of opposite sign.
2. Add this to the minuend. The result of this addition will represent the
difference between the subtrahend and the minuend. E. g subtract +4 from +9,

Then,
• When the subtrahend is changed to its 2’s complement, it actually becomes
-4, so that you are adding -4 and +9 which is the same as subtracting +4 from
+9.
• Any subtraction operation, actually becomes one of addition when the 2’s-
complement system is used.
• This feature of the 2’s-complement system has made it the most widely used
of the methods available because it allows addition and subtraction to be
performed by the same circuitry.
• another example showing +9 subtracted from -4,

• Negate the subtrahend (+9 ) to produce 10111 (-9 ) and add this to the
minuend (-4 ).
 Arithmetic Overflow
• In the previous examples the magnitude of the answer was small enough to
fit into four bits. However consider, the addition of +9 and +8.

• The answer has a negative sign bit, which is obviously incorrect because you
are adding two positive numbers. The answer should be +17, but the
magnitude 17 requires more than four bits and therefore overflows into the
sign-bit position.
• This overflow condition can occur only when two positive or two negative
numbers are being added, and it always produces an incorrect result.
• Overflow can be detected by checking to see that the sign bit of the result is
the same as the sign bits of the numbers being added.

• Subtraction in the 2’s-complement system is performed by negating the

minuend and adding it to the subtrahend, so overflow can occur only when
the minuend and subtrahend have different signs.

• A computer will have a special circuit to detect any overflow condition when
two numbers are added or subtracted.
• This detection circuit will signal the computer’s control unit that overflow
has occurred and the result is incorrect.
 MULTIPLICATION OF BINARY NUMBERS
• The multiplication of binary numbers is done in the same manner as the
multiplication of decimal numbers. The following example illustrates for
unsigned binary numbers:
 Multiplication in the 2’s-Complement System
• If the two numbers to be multiplied are positive, they are already in true
binary form and are multiplied as they are. The resulting product is, of
course, positive and is given a sign bit of 0.
• When the two numbers are negative, they will be in 2’s-complement form.
The 2’s complement of each is taken to convert it to a positive number, and
then the two numbers are multiplied. The product is kept as a positive
number and is given a sign bit of 0.
• When one of the numbers is positive and the other is negative, the negative
number is first converted to a positive magnitude by taking its 2’s
complement. The product will be in true-magnitude form. However, the
product must be negative because the original numbers are of opposite sign.
Thus, the product is then changed to 2’s-complement form and is given a
sign bit of 1.
 BINARY DIVISION
• consider the following simple division examples:
•

• (a) (b)
• In (a), we have 10012 Divided by 112 which is equivalent to 9 divide by 3. in
decimal. The resulting quotient is 00112 = 310, in (b), 10102 is divided by 1002
(10 divided by 4) in decimal, the result is 0010.12 = 2.510
 BCD ADDITION
• What is BCD? You should be familiar with BCD from CSC 101.
• The addition of decimal numbers that are in BCD form can be best
understood by considering the two cases that can occur when two decimal
digits are added,
1. Sum Equals 9 or Less. E. g. adding 5 and 4 using BCD to represent each digit:

• The addition is carried out as in normal binary addition, and the sum is 1001,
which is the BCD code for 9.
• another example, take 45 added to 33:

• In the examples above, none of the sums of the pairs of decimal digits
exceeded 9; therefore, no decimal carries were produced.
• For these cases, the BCD addition process is straightforward and is actually
the same as binary addition.
2. Sum Greater than 9, e. g. addition of 6 and 7 in BCD:

• The sum 1101 does not exist in the BCD code; it is one of the six forbidden or invalid
four-bit code groups. This has occurred because the sum of the two digits exceeds 9.
• Whenever this occurs, the sum must be corrected by the addition of six (0110) to take
into account the skipping of the six invalid code groups:

• This addition must be performed whenever the sum of the two decimal digits is
greater than 9.
• another example, take 47 plus 35 in BCD:

• The addition of the four-bit codes for the 7 and 5 digits results in an invalid
sum and is corrected by adding 0110.
• Consider the addition of 59 and 38 in BCD:

• The addition of the least significant digits (LSDs) produces a sum of 17 =

10001. This generates a carry into the next digit position to be added to the
codes for 5 and 3.
• Since 17 > 9, a correction factor of 6 must be added to the LSD sum.
• Addition of this correction does not generate a carry; the carry was already
generated in the original addition.
• BCD addition procedure:
1. Using ordinary binary addition, add the BCD code groups for each digit
position.
2. For those positions where the sum is 9 or less, no correction is needed. The
sum is in proper BCD form.
3. When the sum of two digits is greater than 9, a correction of 0110 should be
added to that sum to get the proper BCD result. This case always produces a
carry into the next digit position, either from the original addition (step 1) or
from the correction addition.
 HEXADECIMAL ARITHMETIC
• Hex numbers are used extensively in machine-language computer
programming and in conjunction with computer memories (i.e., addresses).
• Hex Addition
• Addition of hexadecimal numbers is done in much the same way as decimal
addition, as long as you remember that the largest hex digit is F instead of 9.
The following procedure is suggested,
1. Add the two hex digits in decimal, mentally inserting the decimal equivalent
for those digits larger than 9.
2. If the sum is 15 or less, it can be directly expressed as a hex digit.
3. If the sum is greater than or equal to 16, subtract 16 and carry a 1 to the next
digit position.
• Add the hex numbers 58 and 24.
• 58
• +24
• 7C
• Adding the LSDs (8 and 4) produces 12, which is C in hex.
• There is no carry into the next digit position. Adding 5 and 2 produces 7.

• Add the hex numbers 58 and 4B.

• 58
• +48
• A3
• Hex Subtraction
• we can subtract hex numbers using the same method we used for binary
numbers.
• The 2’s complement of the hex subtrahend will be taken and then added to
the minuend, and any carry out of the MSD position will be disregarded.
• How do we find the 2’s complement of a hex number?
• One way is to convert it to binary, take the 2’s complement of the binary
equivalent, and then convert it back to hex. As shown below.
•
• a quicker procedure: subtract each hex digit from F; then add 1.

• Hex Representation of Signed Numbers

• The data stored in a microcomputer’s internal working memory or on a hard
disk or CD ROM are typically stored in bytes (groups of eight bits).
• In most modern digital machines, the subtractions that are part of the
division operation are usually carried out using 2’s-complement subtraction,
that is, taking the 2’s complement of the subtrahend and then adding.
• The division of signed numbers is handled in the same way as multiplication.
Negative numbers are made positive by complementing, and the division is
then carried out.
• If the dividend and the divisor are of opposite sign, the resulting quotient is
changed to a negative number by taking its 2’s-complement and is given a
sign bit of 1.
• If the dividend and the divisor are of the same sign, the quotient is left as a
positive number and is given a sign bit of 0.
CPE 203: INTRODUCTION TO
DIGITAL COMPUTER SYSTEMS
Basic Logic Circuits
Ninan O. D.
Department of Computer Science & Engineering
Obafemi Awolowo University
 Basic Logic Gates
• Boolean algebra is a means for expressing the relationship between a logic
circuit’s inputs and outputs.
• there are three basic logic operations: OR, AND, and NOT.
• Each logic operation can be implemented electronically with transistors,
resulting in a circuit element called a logic gate.
• A logic gate has one or more inputs and one output that is a function of its
inputs .
• A larger circuit isimplemented by a network of gates.
 OR OPERATION WITH OR GATES

• an OR gate is a circuit that has two or more inputs and whose output is equal
to the OR combination of the inputs.
• the sign (+) does not stand for ordinary addition; it stands for the OR
operation.
• the OR gate operates so that its output is HIGH (logic 1) if either input A or B or
both are at a logic 1 level.
• The OR gate output will be LOW (logic 0) only if all its inputs are at logic 0.
• This same can be extended to more than two inputs.

• the output will be 1 for every case where one or more inputs are 1.
• This general principle is the same for OR gates with any number of inputs.
1. The OR operation produces a result (output) of 1 whenever any input is a 1.
Otherwise the output is 0.
2. An OR gate performs an OR operation on the circuit’s inputs.
3. The expression x = A + B is read as “x equals A OR B.”
• The input signals applied to the circuit can be presented in graphical form,
known as a timing diagram
• Example, Determine the OR gate output. The OR gate inputs A and B are
varying according to the timing diagrams shown. For example, A starts out
LOW at time t0, goes HIGH at t1, back to LOW at t3, and so on.
• The OR gate output will be HIGH whenever any input is HIGH.
• Between time t0 and t1 , both inputs are LOW, so OUTPUT = LOW.
• At t1, input A goes HIGH while B remains LOW. This causes OUTPUT to go HIGH
at t1 and stay HIGH until t4 because, during this interval, one or both inputs
are HIGH.
• At t4 , input B goes from 1 to 0 so that now both inputs are LOW, and this
drives OUTPUT back to LOW.
• At t5 , A goes HIGH, sending OUTPUT back HIGH, where it stays for the rest of
the shown time span.
• AND OPERATION WITH AND GATES

• an AND gate is a circuit that has two or more inputs and whose output is equal
to the AND combination of the inputs.
• The expression x = A .B = AB, is read as “x equals A AND B,” which means that x
will be 1 only when A and B are both 1.
• three-input AND gate and its accompanying truth table are shown
1. The AND operation is performed the same as ordinary multiplication of 1s and
0s.
2. An AND gate is a logic circuit that performs the AND operation on the circuit’s
inputs.
3. An AND gate output will be 1 only for the case when all inputs are 1; for all
other cases, the output will be 0.
4. The expression x = AB is read as “x equals A AND B.”
Example, Determine the output waveform for the AND gate shown

The output x will be at 1 only when A and B are both HIGH at the same time.
• the x waveform is 0 whenever B is 0, regardless of the signal at A. Also notice
that whenever B is 1, the x waveform is the same as A.
• B input can be a control input whose logic level determines whether or not the
A waveform gets through to the x output. In this situation, the AND gate is used
as an inhibit circuit.
• B = 0 is the inhibit condition producing a 0 output.
• Conversely, B = 1 is the enable condition, which enables A to reach the output.
NOT OPERATION
The NOT operation is also referred to as inversion or complementation,

• Presence of small circle always denotes inversion

• more commonly called an INVERTER.
• This circuit always has only a single input, and its output logic level is always
opposite to the logic level of the input.
• It inverts (complements) the input signal at all points on the waveform so that
whenever the input = 0, output = 1, and vice versa.
 CPE 203: INTRODUCTION TO
DIGITAL COMPUTER SYSTEMS
Logic Circuits and Boolean Algebra
Ninan O. D.
Department of Computer Science & Engineering
Obafemi Awolowo University

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 Boolean Expression
• Any logic circuit can be described using the three basic Boolean operations
• The OR gate, AND gate, and NOT circuit are the basic building blocks of digital
systems.
•

• The outputs of these circuits are (i) X = A.B + C and (ii) X = (A+B).C
• Note that (A+B). C is not the same as A+B.C as this may mean A+(B.C).
• When an INVERTER/NOT is present in a logic-circuit diagram, its output
expression is the input expression with a bar/prime over it,

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• The outputs of the circuits can also be expressed as (i) A’+B and (ii) (A+B)’
• A truth table specifies the values of a Boolean expression for every possible
combination of values of the variables. For example,

• The truth table specifies the output of the circuit for all possible combinations
of values of the inputs
• The circuit output logic level for any set of input levels can be obtain from the
Boolean expression as well as the truth table.

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Circuit Implementation
• A logic-circuit diagram can be drawn directly from its Boolean expression. E. g,
• X = A.B.C only needs one three input AND gate, X = A + B’ needs a two-input
OR gate with an INVERTER on one of the inputs.
• The same can be extended to more complex circuits. E. g.,
• The circuit diagram to implement the expression X = (A+B)(B’+C) is,

• the terms A + B and B’ + C are inputs to an AND gate.

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• NOR GATE

• The NOR symbol Equivalent circuit Truth table

• the NOR gate output is the exact inverse of the OR gate output for all possible
input conditions.
• An OR gate output goes HIGH when any input is HIGH;
• The NOR gate output goes LOW when any input is HIGH.
• This same operation can be extended to NOR gates with more than two
inputs.
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• NAND GATE

• NAND symbol Equivalent circuit Truth table

• the NAND gate output is the exact inverse of the AND gate for all possible input
conditions.
• The AND output goes HIGH only when all inputs are HIGH,
• the NAND output goes LOW only when all inputs are HIGH.
• This same characteristic is true of NAND gates having more than two inputs.

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• Boolean Theorems
• There are various Boolean theorems (rules) that can help simplify logic
expressions and logic circuits. Theorems 1 – 8 are,

• x is a logic variable that can be either a 0 or a 1.,

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• Multivariable theorems
• (9) x+y = y+x
• (10) x.y = y.x

• Theorems (9) and (10) are called the commutative laws.

• These laws indicate that the order in which we OR or AND two variables is
unimportant; the result is the same.
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• Theorems (11) and (12) are the associative laws, which state that we can
group the variables in an AND expression or OR expression any way we want.
• Theorem (13) is the distributive law, which states that an expression can be
expanded by multiplying term by term just the same as in ordinary algebra.
• Theorems (9) to (13) are easy to remember and use because they are identical
to those of ordinary algebra.
• Theorems (14) and (15) do not have any counterparts in ordinary algebra.
• Each can be proved by trying all possible cases for x and y. E. g., for x + xy, using
truth table.
• Value of x + xy is same as x.

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• It can also be proved by factoring and using theorems (6) and (2),
• x + xy = x(1+y) = x.1 = x.
• Boolean theorems can be useful in simplifying a logic expression that is, in
reducing the number of terms in the expression.
• When this is done, the reduced expression will produce a circuit that is less
complex than the one that the original expression would have produced.
• For eg, Simplify the expression, y = AB’D + AB’D’
• y = AB’(D + D’) ------factoring the expression
• = AB’(1) ------- using theorem 2
• = AB’.

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• Simplify z =(A’+ B)(A + B).
• = A’A + A’B + BA + BB ------Expanding
• = 0 + A’B + BA + B -------- using theorem 3 and 4 A’A = 0, BB = B.
• = B(A’+ A + 1) --------- using theorem 13
• = B. -------- using theorem 2 and 6.

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• DeMorgan’s theorems

• Theorem (16) says when the OR sum of two variables is inverted, it is the same
as inverting each variable individually and then ANDing these inverted
variables.
• Theorem (17) says that when the AND product of two variables is inverted, it is
is the same as inverting each variable individually and then ORing them.

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• When using De Morgan’s theorems to reduce an expression, we may break an
inverter sign at any point in the expression and change the operator sign at
that point in the expression to its opposite ( + is changed to ·, and vice versa).
• This procedure is continued until the expression is reduced to one in which
only single variables are inverted. Examples,

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• De Morgan’s theorems are easily extended to more than two variables.

• the large inverter sign is broken at two points in the expression and the
operator sign is changed to its opposite.
• This can be extended to any number of variables.
• The variables can themselves be expressions rather than single variables

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• Universality of NAND gate
• Any expression can be implemented using combinations of OR gates, AND
gates, and INVERTERs.
• It is possible, however, to implement any logic expression using only NAND
gates and no other type of gate.

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• Similarly, NOR gates can be arranged to implement any of the Boolean
operations.

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• It is common to find circuit diagrams that use alternate logic symbols in
addition to the standard symbols.
• These are the alternate symbols for each gate and their equivalence to the
standard symbols.
• The alternate symbol for each gate is obtained from the standard symbol by,
1. Invert each input and output of the standard symbol. This is done by adding
bubbles (small circles) on input and output lines that do not have bubbles and
by removing bubbles that are already there.
2. Change the operation symbol from AND to OR, or from OR to AND. (In the
special case of the INVERTER, the operation symbol is not changed.)

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• Standard and alternate logic symbols .

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CPE 203: INTRODUCTION TO
DIGITAL COMPUTER SYSTEMS
Combinational Logic Circuits
Ninan O. D.
Department of Computer Science & Engineering
Obafemi Awolowo University
 Logic-circuit simplification and design
• combinational logic circuits - at any time, the logic level at the output
depends on the combination of logic levels present at the inputs.
• A combinational circuit has no memory characteristic, so its output depends
only on the current value of its inputs.
• Two methods of simplification of logic circuits - Boolean algebra theorems;
and mapping technique.

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• Sum-of-products (SOP)

• consists of two or more AND terms (products) that are ORed together.
• Each AND term consists of one or more variables individually appearing in
either complemented or uncomplemented form.
• in a sum-of-products expression, one inversion sign cannot cover more than
one variable in a term e. g., we cannot have

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• Product – of – sums (POS)
• consists of two or more OR terms (sums) that are ANDed together.
• Each OR term contains one or more variables in complemented or
uncomplemented form. Examples,

• can always be realized directly by one or more OR gates feeding a single AND
gate at the circuit output

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• Simplifying logic circuits
• Logic circuit expression can be reduced to a simpler form.
• The new expression can be used to implement a circuit that is equivalent to the
original circuit but that contains fewer gates and connections. E.g.,
• The circuit

• can be reduced to the following

• Both circuits perform the same logic, but the simpler circuit contains fewer gates and
will be smaller and cheaper than the original.
• The circuit reliability will improve because there are fewer interconnections which
can be potential circuit faults.

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There are two methods of simplifying logic circuits.
1. Using the Boolean algebra theorems
2. Using Karnaugh mapping.
Using Boolean Algebra.
• Boolean algebra theorems have been discussed in the last lecture.
• Note that it is not always obvious which theorems should be applied to produce the simplest
result.
• Algebraic simplification often becomes a process of trial and error.
• Two essential steps, the Boolean theorems can be applied to simplify an expression :
1. The original expression is put into SOP form by repeated application of DeMorgan’s
theorems and multiplication of terms.

2. Once the original expression is in SOP form, the product terms are checked for common
factors, and factoring is performed wherever possible. The factoring should result in the
elimination of one or more terms.

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• Example, Simplify the following logic circuit,

• determine the expression for the output

• break down all large inverter signs using DeMorgan’s theorems and then
multiply out all terms.
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• Once the expression is determined, break down all large inverter signs using
DeMorgan’s theorems and then multiply out all terms.

• With the expression now in SOP form, look for common variables

• factor out A.
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• The result can be simplified no further. Its circuit implementation is,

• The simplification process may produce an equivalent, but not simpler circuit,
that both circuits contain the same number of gates and connections.
• Also, you may not be able to simplify some expressions any further.

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 Designing Combinational logic circuits
• When the desired output level of a logic circuit is given for all possible input
conditions, the results can be conveniently displayed in a truth table.
• The Boolean expression for the required circuit can then be derived from the
truth table.
• For example, Consider the circuit whose output x is to be 1 for A = 0, B = 1 and
A = 1, B = 0.

• an AND term is generated for each case in the table where the output x is to
be a 1.
• The AND gate outputs are then ORed together to produce the total output x,

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• Complete Design Procedure
• Any logic problem can be solved using the following step-by-step procedure.
1. Interpret the problem and set up a truth table to describe its operation.
2. Write the AND (product) term for each case where the output is 1.
3. Write the sum-of-products (SOP) expression for the output.
4. Simplify the output expression if possible.
5. Implement the circuit for the final, simplified expression.

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 Karnaugh map method
• The Karnaugh map (K map) is a graphical tool used to simplify a logic
equation or to convert a truth table to its corresponding logic circuit in a
simple, orderly process.
• Although a K map can be used for problems involving any number of input
variables, its practical usefulness is limited to five or six variables.

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CPE 203: INTRODUCTION TO DIGITAL COMPUTER SYSTEMS I (2 UNITS [2-0-
0])

Performance Characteristics and Parameters for Logic Circuit

Several things define the performance of a logic circuit. These performance characteristics are
the switching speed measured in terms of the propagation delay time, the power dissipation,
the fan-out or drive capability, the speed-power product, the dc supply voltage, and the
input/output logic levels.

Timing Diagram
Shows the logic values of signals in a circuit versus time Waveform: the shape of a signal
over a period of time Example: timing diagram of an AND gate (with zero delay)

Propagation Delay

A change in the inputs of a gate causes a change in its outputs. However, the change in the
output signal is not instantaneous. There is a small delay between an input signal change
and an output signal change, called propagation delay.

Propagation delay can be defined as the time it takes for a system to produce the appropriate
output after it receives an input. Think about a typical ATM machine. You do not receive the
money immediately; it takes a little time for the pmoney to come out of the ATM machine.
This is propagation delay. A biologic example can be found in our reflexes. From the time you
see brake lights on the car in front of you until you get your foot on the brakes, there is a
measurable delay or reaction time.

1
When the IN signal goes HIGH, it causes the OUT signal to go HIGH a short time later.
Likewise, when the IN signal goes LOW, it causes the OUT signal to go LOW a short time
later.

Figure 1 - Measuring propagation delay in a logic gate.

Two things are important to note from the timing diagram in Figure 1(b):

1. Transitions are not truly vertical (instantaneous) so we measure from the 50% point on
the input to the 50% point on the output.
2. The time it takes to make the output go HIGH is not necessarily the same as the time to
make the output go LOW.

The speed of a logic circuit is related to this characteristic of propagation delay. Whatever part
is chosen to implement the logic circuit will have a data sheet that states the value of
propagation delay. This information is used to assure that the circuit can operate fast enough
for the application.

Propagation delay time, tP, of a logic gate is the time interval between the transition of an
input pulse and the occurrence of the resulting transition of the output pulse. There are two
different measurements of propagation delay time associated with a logic gate that apply to all
the types of basic gates:

•tPHL: The time between a specified reference point on the input pulse and a corresponding
reference point on the resulting output pulse, with the output changing from the HIGH level to

2
the LOW level (HL). Simply put, tPHL = Propagation delay when the OUTPUT switches from
HIGH to LOW

•tPLH: The time between a specified reference point on the input pulse and a corre- sponding
reference point on the resulting output pulse, with the output changing from the LOW level to
the HIGH level (LH). tPLH = Propagation delay when the OUTPUT switches from LOW to
HIGH

Propagation delay time (tP) = ½ (tPHL + tPLH)

• The propagation delay of a gate limits the frequency at which it can be operated. How?
• The greater the propagation delay, the lower the maximum frequency (tp is inversely
proportional to frequency).
• Thus, Faster circuits are characterized by smaller propagation delays.
• Higher performance systems require higher speeds (smaller propagation delays).

Note

For the HCT family CMOS, the propagation delay is 7 ns, for the AC family it is 5 ns, and for
the ALVC family it is 3 ns. For standard-family bipolar (TTL) gates, the typical propagation
delay is 11 ns and for F family gates it is 3.3 ns. All specified values are dependent on certain
operating conditions as stated on a data sheet.

Worked Example
1. Find the Propagation delay (tP) of a gate with tPLH of 7 ns and tPHL of 5 ns.
2. Show the propagation delay times of an inverter.

Solution

1. Propagation delay time (tP) = ½ (tPHL + tPLH) = ½ (7+5)ns = 6ns

2. An input/output pulse of an inverter is shown below, and the propagation delay times,
tPHL and tPLH, are indicated. In this case, the delays are measured between the 50%
points of the corresponding edges of the input and output pulses. The values of tPHL and
tPLH are not necessarily equal but in many cases they are the same.

Class work
1. One type of logic gate has a specified maximum tPLH and tPHL of 10 ns. For another
type of gate the value is 4 ns. Which gate can operate at the highest frequency and
which operates at lowest frequency. Explain your answers.

3
Propagation Delay in a Circuit
In a given circuit, each gate has a delay. The circuit has a propagation delay between inputs
and outputs. The propagation delay is computed along the critical path

To compute the propagation delay in a circuit, start at the inputs:

1. Delay at each gate output = Maximum input delay + Gate delay

2. Propagation delay of a circuit = maximum delay at any output

Computing the Maximum Circuit Delay

Consider the following circuit with 8 inputs and 2 outputs. Delay of a 2-input AND gate = 2
ns, Delay of a 3-input AND gate = 3 ns, Delay of a 2-input OR gate = 2 ns, Delay of a 3-
input OR gate = 3 ns

Power Dissipation
Generally, as propagation delays decrease (increased speed), the power consumption and
related heat generation increase. That is tp is inversely proportional to power consumption and
related heat generation.

A logic gate draws current from the DC Supply voltage source. When the gate is in the HIGH
output state, an amount of current designated by ICCH is drawn. In the LOW output state, a
different amount of current, ICCL is drawn.

When a gate is pulsed, its output switches back and forth between HIGH and LOW and the
amount of supply current varies between ICCH and ICCL. The average power dissipation depends
on the duty cycle and is usually specified for a duty cycle of 50%

When the duty cycle is 50%, the output is HIGH half the time and LOW the other half. The
average supply current, ICC, is therefore:

ICC = ½ (ICCH + ICCL)

To determine the Average Power Dissipation PD of a gate the following equation is used:

PD = VCC X ICC = VCC × ½ (ICCH + ICCL)

4
 Power Dissipation in a TTL circuit is essentially constant over its range of operating
frequencies. Power Dissipation in CMOS, however, is frequency dependent. It is extremely
low under (dc) conditions and increases as the frequency increases

Worked Example
A certain gate draws 2 mA when its output is HIGH and 3.6 mA when its output is LOW.
What is its average power dissipation if VCC is 5 V and the gate is operated on a 50% duty
cycle

Solution
ICC = ½ (ICCH + ICCL)
ICC = ½ (2 mA + 3.6 mA) = 2.8 mA

PD = VCC X ICC = 5 V X 2.8 mA = 14 mW

Fan-In
The fan-in is the number of inputs to a gate. A 3-input AND gate has a Fan-in of 3. Logic gates
with a large fan-in tend to be slow. Increasing the Fan-in of a gate increases the gate delay. For
example, a 3-input AND gate has a higher delay than a 2-input AND gate made with the same
technology. Using logic gates with higher fan-in is useful when reducing the depth (number of
levels) of a logic circuit

Fan in Limitations
The fan-in of a gate is the number of inputs of this gate. Thus, a 4-input AND gate is said to
have a fanin of 4. A physical gate cannot have a large number of inputs (fanin). For CMOS
technology, the more inputs a gate has the slower it is (larger propagation delay). For example,

Fan-in
a 4-input AND gate is slower than a 2- input one. In CMOS technology, no more than 4-input
gates are typically built since more than 4 inputs makes the devices too slow. TTL gates can
have more inputs (e.g, 8 input NAND 7430).

◼ Number of input signals to a gate

Fan-in characteristics
i. Number of input signals to a gate
◼ Not an electrical property
ii. Not an electrical property
iii. Function of the manufacturing process
◼ Function of the manufacturing process
What’s the Fan-in of the gate below?

NAND gate with a

Fan-in of 8

Fan-Out
In digital circuits, it is common for the output of one gate (called driver gate) to be connect to
25
the inputs of several load gates. The fan-out of a gate is the number of gate inputs it can feed.
There is a limit on the maximum fan-out of a gate. The output of a driver gate can supply a

5
 limited amount of current. Each input of a load gate consumes a certain amount of current.
Therefore, the driver gate can only feed a limited number of load gates. Fan-Out is a measure
of the ability of the output of one gate to drive the input(s) of subsequent gates.

Fan-Out
◼ A measure of the ability of the output of one gate to drive the
input(s) of subsequent gates
Loading and Fan-Out
◼ Usually specified
When the output of a as
logic standard
gate is connectedloads within
to one or more athesingle
inputs of family
other gates, a load on
the driving gate is created. As more load gates are connected to the driving gate, the loading
◼ e.g., An
on the input
driving to an There
gate increases. inverter intothe
is a limit sameof family
the number load gate inputs that a given
gate can drive.
◼ For TTL devices, the number of standard loads is limited by the
amount of input current each load requires as compared to the
Usually specified as standard loads within a single family e.g., An input to an inverter in the
same family. For TTL devices, the number of standard loads is limited by the amount of input
current that
current each the driving
load requires gatetocan
as compared deliver.
the current It isgategenerally
that the driving can deliver. It is
generally considered to be the smaller of the following two items:
considered to be the smaller of the following two items:

◼ MayFan-Out
have
Note
to compute
(Cont.) based on current drive requirements
when mixing families
i. May have to compute based on current drive requirements when mixing families.
ii. Although mixing families is not usually recommended
◼ Although
◼
mixing
An illustration of fan-out
iii. An illustration
currents
families
and theisassociated
not usually
and the associated
of fan-out
source and recommended
sink
source and sink currents.

27

28
6
Worked Example
How many 74ALS00 NAND gate inputs can be driven by a 74ALS00 NAND gate output?
The parameters of 74ALS00 NAND gate from the datasheet are the maximum values of
IOH = 0.4 mA, IOL = 8 mA, IIH = 20 µA, and IIL = 0.1 mA,

Solution
Hence, Fan-out (high) = IOH(max) / IIH (max)
= 0.4 mA/20 µA
= 400 µA/20 µ A = 20

Fan-out (low) = IOL(max) / IIL(max) = 8 mA/0.1 mA = 80. The overall fan-out = fan-out
(high) or fan-out (low) whichever is lower. Hence, overall fan-out = 20

Note: If the fan-out has a fractional part, it should be dropped. In other words, you should
always round down when calculating fan-out

Another Example
A unit load for some particular logic family is as follows:
1 UL = 50 µA HIGH state
= 1 mA LOW state
Determine the fan-in and fan-out for a gate in this family that
has the following parameters:
IOH = 400 µA
IOL = 10mA
IIH = 150 µA
IIL = 4 mA

Solution: Fan-in = IIH /1 UL = 150/50 = 3 UL

Therefore fan-in = 3 or 3 UL

Fan-out (High) = IOH / IIH

= 400/150
= 2.67
=2

Fan-out (Low) = IOL / IIL

= 10/4
= 2.5
=2

Q. What is meant by the DRIVE of a gate?

A. It is the “CURRENT” driving-ability of a gate. In other words, it is the amount of current
the gate can deliver to its load devices. A gate with high-drive is capable of driving more load
gates than another with low-drive.

How can one drive a number of load gates that is larger than the fanout of the driver gate?
There are two methods one can use to achieve this:

7
1. Use high drive buffers
2. Use multiple drivers.

Increasing the Fan-Out with a Buffer Gate

Buffer Gate

Output ƒ = Input

Buffer gate is another logic gate that has one input and its output follow the same logic state
as the input. The buffer is used as a delay element in digital electronics. It is also a current-
boost-up element, which is used to increase the capability of the output of one gate to drive a
number of other gates. Note that the symbol of the buffer resembles the inverter symbol
except that it does not have the inverting circle that the inverter symbol has.

Buffer provides drive capability

o Used to amplify an input signal

o High current output
o Increases the Fan-Out
o increases the propagation delay of a circuit

The figure shows how the buffer is used to drive the large load.

Use of Multiple Drivers

The Figure shows the case of 2 identical drivers driving the load gates.

8
In general, the large number of load gates is divided among more than one driver such that
each of the identical drivers is driving now more than the fanout.

The multiple driver gates (D1, D2) are of identical type and should be connected to the same
input signals

Parity Method for Error Detection

Whenever information is transmitted from one device (the transmitter) to another device (the
receiver), there is a possibility that errors can occur such that the receiver does not receive the
identical information that was sent by the transmitter. The major cause of any transmission
errors is electrical noise, which consists of spurious fluctuations in voltage or current that are
present in all electronic systems to varying degrees. Figure 1 is a simple illustration of a type
of transmission error.

Figure 1 - Example of noise causing an error in the transmission of digital data.

The transmitter sends a relatively noise-free serial digital signal over a signal line to a receiver.
However, by the time the signal reaches the receiver, it contains a certain degree of noise
superimposed on the original signal. Occasionally, the noise is large enough in amplitude that
it will alter the logic level of the signal, as it does at point x. When this occurs, the receiver
may incorrectly interpret that bit as a logic 1, which is not what the transmitter has sent.

Most modern digital equipment is designed to be relatively error-free, and the probability of
errors such as the one shown in Figure 1 is very low. However, we must realize that digital
systems often transmit thousands, even millions, of bits per second, so that even a very low
rate of occurrence of errors can produce an occasional error that might prove to be bothersome,
if not disastrous. For this reason, many digital systems employ some method for detection (and

9
sometimes correction) of errors. One of the simplest and most widely used schemes for error
detection is the parity method.

Parity bit

A parity bit tells if the number of 1s is odd or even.

Many systems use a parity bit as a means for bit error detection. Any group of bits contain
either an even or an odd number of 1s. A parity bit is attached to a group of bits to make the
total number of 1s in a group always even or always odd. An even parity bit makes the total
number of 1s even, and an odd parity bit makes the total odd.

A given system operates with even or odd parity, but not both. For instance, if a system
operates with even parity, a check is made on each group of bits received to make sure the total
number of 1s in that group is even. If there is an odd number of 1s, an error has occurred.

As an illustration of how parity bits are attached to a code, the table below lists the parity bits
for each BCD number for both even and odd parity. The parity bit for each BCD number is in
the P column.

The parity bit can be attached to the code at either the beginning or the end, depending on
system design. Notice that the total number of 1s, including the parity bit, is always even for
even parity and always odd for odd parity.

Detecting an Error

A parity bit provides for the detection of a single bit error (or any odd number of errors, which
is very unlikely) but cannot check for two errors in one group. For instance, let’s assume that
we wish to transmit the BCD code 0101. (Parity can be used with any number of bits; we are
using four for illustration.) The total code transmitted, including the even parity bit, is

10
Now let’s assume that an error occurs in the third bit from the left (the 1 becomes a 0).

When this code is received, the parity check circuitry determines that there is only a single 1
(odd number), when there should be an even number of 1s. Because an even number of 1s does
not appear in the code when it is received, an error is indicated.

An odd parity bit also provides in a similar manner for the detection of a single error in a given
group of bits.

Classwork
1. Assign the proper even parity bit to the following code groups:
(a) 1010 (b) 111000 (c) 101101
(d) 1000111001001 (e) 101101011111

Solution
Make the parity bit either 1 or 0 as necessary to make the total number of 1s even. The parity
bit will be the left-most bit (color).
(a) 01010 (b) 1111000 (c) 0101101 (d) 0100011100101
(e) 1101101011111

2. An odd parity system receives the following code groups: 10110, 11010, 110011,
110101110100, and 1100010101010. Determine which groups, if any, are in error.

Solution
Since odd parity is required, any group with an even number of 1s is incorrect. The following
groups are in error: 110011 and 1100010101010.

Related Problem
1. The following ASCII character is received by an odd parity system: 00110111. Is it
correct?
2. What actual bit strings would a computer transmit to send the message HELLO, using
ASCII with even parity?

Solution
First, look up the ASCII codes for each character in the message. Then for each code, count
the number of 1s. If it is an even number, attach a 0 as the MSB. If it is an odd number, attach
a 1. Thus, the resulting eight-bit codes (bytes) will all have an even number of 1s (including
parity).

Ascii code for H – 72, E – 69, L – 76 & O - 79

11
Assignment
1. Attach an odd-parity bit to the ASCII code for the $ symbol, and express the result in
hexadecimal.
2. Attach an even-parity bit to the BCD code for decimal 69.
3. Attach an odd-parity bit to the BCD code for decimal 92.
4. Why can’t the parity method detect a double error in transmitted data?

Error Correction
Error detection is beneficial because the system that receives a datum containing an error
knows it has received “damaged goods.” Wouldn’t it be great if somehow the receiver could
also know which bit was wrong? If a binary bit is wrong, then the correct value is simply its
complement. Several methods have been developed to accomplish this. In each case, it requires
that several bits of “error detection/correction codes” be applied to each transmitted packet of
information. As the packet is received, a digital cir- cuit can detect if errors have occurred (even
multiple errors) and correct them. This technology is used for massive transfer of high speed
data in such applications as magnetic disk drives, flash drives, CD, DVD, Blu-ray Disc, digital
television, and broadband Internet networks.

Method for Error Detection and Correction

The parity method of error detection, the cyclic redundancy check and the Hamming code for
error detection and correction is presented.

Parity Generator and Checker for Error Correction

We have discussed how a transmitter can attach a parity bit to a set of data bits before
transmitting the data bits to a receiver. We also saw how this allows the receiver to detect any
single-bit errors that may have occurred during the transmission. Figure below shows an
example of one type of logic circuitry that is used for parity generation and parity checking.
This particular example uses a group of four bits as the data to be transmitted, and it uses an
even-parity bit. It can be readily adapted to use odd parity and any number of bits.

In Figure below, the set of data to be transmitted is applied to the parity-generator circuit, which
produces the even-parity bit, P, at its output. This parity bit is transmitted to the receiver along
with the original data bits, making a total of five bits. In Figure (b), these five bits 1data + parity
enter the receiver’s parity-checker circuit, which produces an error output, E, that indicates
whether or not a single-bit error has occurred.

It should not be too surprising that both of these circuits employ XOR gates when we consider
that a single XOR gate operates so that it produces a 1 output if an odd number of its inputs are
1, and a 0 output if an even number of its inputs are 1.

12
XOR gates used to implement (a) the parity generator and (b) the parity checker for an even-parity system.

Classwork
1. Determine the parity generator’s output for each of the following sets of input data,
D3D2D1D0: (a) 0111; (b) 1001; (c) 0000; (d) 0100. Refer to Figure (a).

Solution
For each case, apply the data levels to the parity-generator inputs and trace them through each
gate to the P output. The results are: (a) 1; (b) 0; (c) 0; and (d) 1. Note that P is a 1 only when
the original data contain an odd num ber of 1s. Thus, the total number of 1s sent to the receiver
(data + parity) will be even.

2. Determine the parity checker’s output [see Figure (b)] for each of the following sets of
data from the transmitter:

Solution
For each case, apply these levels to the parity-checker inputs and trace them through to the E
output. The results are: (a) 0; (b) 0; (c) 1; (d) 1. Note that a 1 is produced at E only when an
odd number of 1s appears in the inputs to the parity checker. This indicates that an error has
occurred because even parity is being used.

Cyclic Redundancy Check

The cyclic redundancy check (CRC) is a widely used code used for detecting one- and two-
bit transmission errors when digital data are transferred on a communication link. The
communication link can be between two computers that are connected to a network or between
a digital storage device (such as a CD, DVD, or a hard drive) and a PC. If it is properly

13
designed, the CRC can also detect multiple errors for a number of bits in sequence (burst
errors). In CRC, a certain number of check bits, sometimes called a checksum, are appended to
the data bits (added to end) that are being transmitted. The transmitted data are tested by the
receiver for errors using the CRC. Not every possible error can be identified, but the CRC is
much more efficient than just a simple parity check.
CRC is often described mathematically as the division of two polynomials to generate a
remainder. A polynomial is a mathematical expression that is a sum of terms with positive
exponents. When the coefficients are limited to 1s and 0s, it is called a univariate polynomial.
An example of a univariate polynomial is 1x3 + 0x2 + 1x1 + 1x0 or simply x3 + x1 + x0, which
can be fully described by the 4-bit binary number 1011. Most cyclic redundancy checks use a
16-bit or larger polynomial, but for simplicity the process is illustrated here with four bits.

Modulo-2 Operations
Simply put, CRC is based on the division of two binary numbers; and, as you know, division
is just a series of subtractions and shifts. To do subtraction, a method called modulo-2 addi-
tion can be used. Modulo-2 addition (or subtraction) is the same as binary addition with the
carries discarded, as shown in the truth table in the table below. Truth tables are widely used
to describe the operation of logic circuits. With two bits, there is a total of four possible
combinations, as shown in the table. This particular table describes the modulo-2 operation
also known as exclusive-OR and can be implemented with a logic gate. A simple rule for
modulo-2 is that the output is 1 if the inputs are different; otherwise, it is 0.

CRC Process
The process is as follows:
1. Select a fixed generator code; it can have fewer bits than the data bits to be checked.
This code is understood in advance by both the sending and receiving devices and must
be the same for both.
2. Append a number of 0s equal to the number of bits in the generator code to the data
bits.
3. Divide the data bits including the appended bits by the generator code bits using
modulo-2.
4. If the remainder is 0, the data and appended bits are sent as is.
5. If the remainder is not 0, the appended bits are made equal to the remainder bits in order
to get a 0 remainder before data are sent.
6. At the receiving end, the receiver divides the incoming appended data bit code by the
same generator code as used by the sender.
7. If the remainder is 0,there is no error detected (it is possible in rare cases for multiple
errors to cancel). If the remainder is not 0, an error has been detected in the trans-
mission and a retransmission is requested by the receiver.

The figure below illustrates the CRC process.

14
The CRC process.

Classwork
Determine the transmitted CRC for the following byte of data (D) and generator code (G).
Verify that the remainder is 0. D:11010011 G:1010

Solution
Since the generator code has four data bits, add four 0s (blue) to the data byte. The appended
data (D’) is D’ = 110100110000. Divide the appended data by the generator code (red) using
the modulo-2 operation until all bits have been used.

15
Remainder = 0100. Since the remainder is not 0, append the data with the four remainder bits
(blue). Then divide by the generator code (red). The transmitted CRC is 110100110100.

Remainder = 0

Related Problem
Change the generator code to 1100 and verify that a 0 remainder results when the CRC process
is applied to the data byte (11010011).

Hamming Code
The Hamming code is used to detect and correct a single-bit error in a transmitted code. To
accomplish this, four redundancy bits are introduced in a 7-bit group of data bits. These
redundancy bits are interspersed at bit positions 2n (n = 0, 1, 2, 3) within the original data bits.
At the end of the transmission, the redundancy bits have to be removed from the data bits. A
recent version of the Hamming code places all the redundancy bits at the end of the data bits,
making their removal easier than that of the interspersed bits. A coverage of the classic
Hamming code is available on the website.

16