EC232: ANALOG INTEGRATED CIRCUITS LAB

1. FAMILIARISATION OF OPERATIONAL AMPLIFIERS

AIM:
1. To familiarize with op-amp IC 741
2. To design and set up the following basic operational amplifier circuits.
a) Inverting amplifier
b) Non-inverting amplifier
c) Adder
d) Integrator
e) Comparators

COMPONENTS AND EQUIPMENTS REQUIRED:

 Op-Amp (IC741)
 Resistors
 Capacitors
 Power supplies
 DSO and bread board

THEORY:
An operational amplifier or op-amp is a linear integrated circuit that has a very high
voltage gain, high input impedance and low output impedance. Op-amp is basically a differential
amplifier whose basic function is to amplify the difference between two input signals. Op-amp has
five basic terminals, that is, two input terminals, one output terminal and two power supply
terminals

Definition of 741-pin functions:

Pin 1 (Offset Null): Since the op-amp is the differential type, input offset voltage must be
controlled so as to minimize offset. Offset voltage is nulled by application of a voltage of opposite
polarity to the offset. An offset null-adjustment potentiometer may be used to compensate for offset
voltage. The null-offset potentiometer also compensates for irregularities in the operational
amplifier manufacturing process which may cause an offset. Consequently, the null potentiometer
is recommended for critical applications.

Pin 2 (Inverted Input): Pin2 is called the inverting input terminal and it gives opposite polarity at
the output if a signal is applied to it. It produces a phase shift of 180o between input and output.

Pin 3 (Non-Inverted Input): Pin3 is called the non-inverting terminal that amplifies the input
signal without inversion, i.e., there is no phase shift or input is in phase with output. The op-amp
usually amplifies the difference between the voltages applied to its two input terminals. All
input signals at this pin will be processed normally without inversion.

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Pin 4 (-V): This pin (also referred to as Vee) is the negative supply voltage terminal. Supply-
voltage operating range for the 741 is -4.5 volts (minimum) to -18 volts (max), and it is specified
for operation between -5 and -15 Vdc. The device will operate essentially the same over this range
of voltages without change in timing period. Sensitivity of time interval to supply voltage change
is low, typically 0.1% per volt.

Pin 5 (Offset Null): Since the op-amp is the differential type, input offset voltage must be
controlled so as to minimize offset. Offset voltage is nulled by application of a voltage of opposite
polarity to the offset. An offset null-adjustment potentiometer may be used to compensate for offset
voltage. The null-offset potentiometer also compensates for irregularities in the operational
amplifier manufacturing process which may cause an offset. Consequently, the null potentiometer
is recommended for critical applications.

Pin 6 (Output): Output signal's polarity will be the opposite of the input's when this signal is
applied to the op-amp's inverting input. For example, a sine-wave at the inverting input will
output a square-wave in the case of an inverting comparator circuit.

Pin 7 (V+): The V+ pin (also referred to as Vcc) is the positive supply voltage terminal of the 741
Op-Amp IC. Supply-voltage operating range for the 741 is +4.5 volts (minimum) to +18 volts
(maximum), and it is specified for operation between +5 and +15 Vdc. The device will operate
essentially the same over this range of voltages without change in timing period. Actually, the most
significant operational difference is the output drive capability, which increases for both current
and voltage range as the supply voltage is increased. Sensitivity of time interval to supply voltage
change is low, typically 0.1% per volt.

Pin 8 (N/C): The 'N/C' stands for 'Not Connected'. There is no other explanation. There is nothing
connected to this pin, it is just there to make it a standard 8-pin package

Block diagram:
The block diagram of op-amp shows two difference amplifiers, a buffer for less loading, a
level translator for adjusting operating point to original level and o/p stage. An ideal op-amp should
have the following characteristics:

1. Infinite bandwidth

2. Infinite input resistance

3. Infinite open loop gain

4. Zero output resistance

5. Zero offset.

Op-amps have two operating configurations; open loop and closed loop. In open loop
configuration, it can operate as a switch but gain is uncontrolled. In closed loop configuration, gain
can controlled by feedback resistance Rf and input resistance Rin.
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PIN OUT OF OP-AMP LOGIC SYMBOL OF OP-AMP

BLOCK SCHEMATIC OF OP-AMP

Op-Amp circuits:

a)Inverting Amplifier:
The polarity of the input voltage gets inverted at the output. If a sine wave is fed to the input of
the amplifier, the output will be an amplified sine wave with180 phase shift. The gain of the
inverting amplifier is given by the expression A=-Rf/Ri where Rf is the feedback resistance and Ri
is the input resistance. Inverting amplifier can be used as a scalar because the amplitude of the
output can be varied by varying either of the resistors Rf or Ri.

b) Non inverting amplifier:

This circuit provides a gain to the input signal without any change in polarity. The gain of the
non inverting amplifier is given by the expression A=1 + Rf/Ri where Rf is the feedback resistance
and Ri is the input resistance.
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c) Adder (Summing amplifier):

This circuit gives the sum of two input voltages. Here an input voltage Vi and dc voltage Vref
are given as inputs to the adder. This is an inverting summing amplifier because the output is sum
of inputs with a sign change. The minus sign in the expression for the output can be avoided if
necessary by inverting the input once again using a unity gain inverting amplifier. Output can be
scaled by selecting the gain Rf/Ri. If the ratio is greater than 1 the circuit will function as a
summing amplifier because it produces gain also.

d) Integrator:
Integrator is used to integrate the input waveform. i.e; Vo = ∫Vin dt. Here in the inverting
amplifier configuration, the feedback resistor Rf is replaced by capacitor Cf . Integrators are
commonly used in wave shaping, signal generators etc. For proper wave integration, T >> RC. Gain
and linearity of the output are two advantages of op-amp integrators. Linearity is due to linear
charging of capacitor. Its limitation is for Vin=0 and for low frequencies, XCf =∞ or the capacitor
Cf acts as an open circuit. Therefore the op-amp integrator works as an open loop amplifier and the
gain becomes infinity or very high.

e) Comparator:
A comparator is a circuit which compares a signal voltage applied at one of the input
terminals with the reference voltage at other terminal. If the signal is applied at the inverting
terminal of the op-amp it is called inverting comparator and if the signal is applied to non-inverting
terminal of the op-amp it is called non-inverting comparator. In an inverting comparator if input
signal is less than reference voltage, output will be +Vsat. When input signal voltage is greater than
reference voltage output will be –Vsat. The vice-versa takes place in non-inverting comparator.

PROCEDURE:

a) Inverting Amplifier:
1. Connect the circuit as shown in figure
2. Feed a 2 Vpp, 1KHz sine wave at the inverting terminal and observe the input and output
simultaneously on DSO.
3. Verify whether the output is 20Vpp sine wave with 180 out of phase with input.
4. Vary the input signal frequency from 0 to a few MHz to and measure the output voltage
corresponding to each frequency.
5. Calculate the gain in dB using the formula 20 log (Vo/Vin)
6. Plot the frequency response curve logf Vs gain (dB).

b) Non-Inverting Amplifier:
1. Connect the circuit as shown in figure
2. Feed a 2Vpp sine wave at the non-inverting terminal and observe the input and output
simultaneously on DSO.
3. Verify whether the output is 20Vpp sine wave which is in phase with input.
4. Vary the input signal frequency from 0 Hz to a few MHz and measure the output voltage
corresponding to each frequency.
5. Calculate the gain in dB using the formula 20 log (Vo/Vin)
6. Plot the frequency response curve logf Vs gain (dB).
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c) Adder (Summing Amplifier):

1. Connect the circuit as shown in figure
2. Connect battery for voltage V1, and fed a 2Vpp sine wave as V2
3. Measure and note the output voltage and plot the waveform.
Vo = - (R f / Ri) (V1+V2)
d) Integrator
1. Connections are made as per the diagram.
2. Apply an i/p voltage of 1-2Vpp with 1kHz frequency and check the waveform on the DSO.
3. Measure the value of VO by varying the frequency of the input signal.
4. Calculate gain using the formulae 20 log (VO /VIN).

e) Comparator:
6. Connect the circuit as shown in the figure
7. Connect an alternating waveform to the non-inverting input of the op-amp
8. Connect a reference voltage source to inverting input of the op-amp
9. Plot the input and output waveform.

CIRCUIT DIAGRAM:

a)Inverting Amplifier b)Non inverting amplifier

c)Adder

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d) Integrator e) comparator:

DESIGN:

a)Inverting Amplifier
Gain of an inverting amplifier A=-Rf/Rin
Then Rf/Ri = 10;
Take Ri=1K,
Then Rf=10K

b)Non inverting amplifier

Gain of non inverting amplifier A=1+Rf/Ri
Let the gain be 11
Then Rf/Ri = 10;
Take Ri=1K, Then Rf=10K
c)Adder
Vo=-Rf/Ri(Vi+Vref),
Take Rf=Ri=10k for unit gain
d) Integrator
Let input frequency be 1khz
We have f = .

Let C=0.01µF.Then R= = .
∗ ∗ . ∗

=15.9k Use 15k std.

Select Rf=10R
=150k
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OBSERVATION:
Frequecy response for Inverting amplifier:
Input voltage vin=________

Frequency(Hz) Vo(volts) logf Gain=Vo/Vin Gain in dB

=20log(Vo/Vin)

Frequecy response for Non-Inverting amplifier:

Input voltage vin=________

Frequency(Hz) Vo(volts) logf Gain=Vo/Vin Gain in dB

=20log(Vo/Vin)

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EXPECTED WAVEFORMS:

a)Inverting amplifier b)Non inverting amplifier

c)Adder d) Integrator

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e) Comparator:

RESULT: Familiarized with basic operational amplifier circuits.

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2. MEASUREMENT OF OP-AMP PARAMETERS

AIM:

To measure the following parameters of an op-amp

1. Input bias current

2. Input offset current
3. Input offset voltage
4. CMRR
5. Slew rate

COMPONENTS AND EQUIPMENTS REQUIRED:

 Power supplies
 DSO
 Function generator
 IC 741
 Resistors
 Capacitors

THEORY:

1. Input Bias Current (IB)

This is the average of the currents entering into the inverting and non-inverting terminals
of an op-amp.
( )
IB =
For an ideal op-amp, input bias current is zero and for IC741, it is about 80nA.

2. Input Offset Current (Ios)

This is the algebraic difference between the currents into the inverting and non inverting
terminals of op-amp.
IOS = | − |

3. Input Offset Voltage (Vio)

This is the voltage that must be applied between the input terminals of an op-amp to give a
zero output voltage. For an ideal op-amp, output offset voltage is zero and for IC 741, it is
approximately 2mV.

4. Common-Mode Rejection Ratio (CMRR)

A measure of the ability of the op-amp to reject signals that is simultaneously present at
both inputs. CMRR is usually expressed in dB. For an ideal op-amp, CMRR is infinite and
for IC 741, it is about 90dB.
CMRR (in dB) =20log (Ad/Ac)
Where,

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Ad= Differential mode gain and Ac=Common mode gain

5. Slew Rate (SR)

It is the maximum rate of rise of output voltage. It is the measure of fastness of the op-amp.
It is expressed in V/µs.
SR = 2fVo(max)
Ideally Slew rate is infinite and for IC741, it is 0.5V/µs

PROCEDURE:

1. To find the Offset voltage, set up the circuit and measure the output voltage. Input offset
voltage can be measured using the expression
Vio =( )
Where Vo=output voltage and Vio= input offset voltage

2. Set up the circuits for measuring input bias current and input offset current. Measure the
output voltage. Using the expression Vo=IB1R and Vo=IB2R, IB1 and IB2 can be calculated.
Use the following expression for finding input bias and offset currents.
( )
Input bias current, IB =
Input offset current, IOS = | − |
∆
3. Feed a square wave to input and calculate slew rate using the expression SR= , Where
ΔVo is the voltage swing and t is the time taken to change voltage levels.
4. Set up the circuit for finding CMRR. Apply a sine wave at the input and measure Vo.
Calculate CMRR using the expression;

( )
CMRR = .
Express CMRR in dB using the expression 20log (CMRR).

CIRCUIT DIAGRAM

1. To measure offset voltage (Vos)

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2. To measure input bias current (IB)

(a) For measuring IB1: (b) For measuring IB2:

3) To measure CMRR

5) To measure SLEW RATE

RESULT: Measured op-amp parameters and compared with theoretical values.

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 EC232: ANALOG INTEGRATED CIRCUITS LAB

3. SCHMITT TRIGGER
AIM:

To design and set up a Schmitt Trigger circuit using op-amp for various LTP and UTP.

COMPONENTS AND EQUIPMENTS REQUIRED:

 Op-amp (IC 741)

 Resistors
 Diodes
 Function generator
 Bread board
 Power Supply
 DSO

THEORY:

A circuit which converts a irregular shaped waveform to a square wave or pulse is called a
Schmitt trigger or squaring circuit. The input voltage Vin triggers the output Vo every time it
exceeds certain voltage levels called upper threshold voltage VUTP and lower threshold voltage
VLTP. The threshold voltages are obtained by using the voltage divider. Suppose the output voltage
∗
is +Vsat. Now the voltage across R2 is VUTP= ( )
. When the input voltage exceeds the
voltage across resistor R2, output goes to -Vsat. Now the voltage across R2 is VLTP
∗
=( )
.when the input voltage goes lower than this voltage, output goes to +Vsat.
A comparator with positive feedback is said to exhibit hysteresis, a dead band condition.
The hysteresis voltage is the difference between VUTP & VLTP. There are two types of Schmitt
trigger based on where the irregular wave is given. They are, Inverting & non-inverting Schmitt
trigger. Schmitt trigger finds application in wave shaping circuits. The other name given to Schmitt
trigger is regenerative comparator.

PROCEDURE
1. Calculate the value of components using the design procedure given.
2. Connect the circuit as per as the circuit diagram.
3. Apply the negative trigger voltage to the non-inverting terminal.
4. Note down the reading for output voltage Vo & ON & OFF time period.
6. Plot the reading in the graph and compare it with model graph.

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CIRCUIT DIAGRAM:
(a) Schmitt Trigger For LTP=-3V And UTP=+3V (b)Schmitt trigger for LTP=-2V and UTP=+3V

DESIGN

Vcc=15 V then Vsat=13 V

(a) Schmitt Trigger For LTP=-3V And UTP=+3V
∗
LTP= = -3V

∗
UTP= = 3V

Take R2=3.3k
∗ . ∗
Then 3= . ∗
, Then R1= 11k (use 10k std)

(b)Schmitt trigger for LTP=-2V and UTP=+3V

∗
LTP= = -2V

∗
UTP= = 3V

Take R2=3.3k
∗ . ∗
Then 3= . ∗
, Then Rf2= 11k (use 10k std)

∗ . ∗
-2 = . ∗
, Then Rf1= 18.5k (use 15k std)

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EXPECTED GRAPH

RESULT
Designed and set up Schmitt trigger circuit for various LTP and UTP levels

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4. RC PHASE SHIFT OSCILLATOR

AIM:
To design and setup an RC Phase Shift Oscillator using op-amp for a frequency of 1 KHz.

COMPONENTS AND EQUIPMENTS REQUIRED:

 DC source
 DSO
 Bread board
 Op-amp
 Potentiometer
 Capacitors
 Resistors

THEORY:
RC Phase shift oscillator consists an op-amp as the amplifying stage and three RC cascade
networks as the feedback network. The feedback network provides a fraction of the output voltage
back to the input of the amplifier. The op-amp is functioning in the inverting mode. Therefore any
signal which appears at the inverting terminal is shifted by 180 ͦ at the output. An additional 180 ͦ
phase shift required for oscillation as per Barkhausen criteria is provided by the cascade RC
network. Thus the total phase shift around the loop becomes 0 ͦ.

The frequency of oscillation is given by, 1⁄(√6 2 )The gain of the inverting op-amp
should be at least 29 at this frequency because the attenuation provided by the feedback network is
1/29. The gain is kept slightly greater than 29 to ensure that the variations in circuit parameters will
not make the loop gain less than unity, and thus oscillations die out. For lower frequencies (<1
MHz), op-amp 741 may be used, however for high frequencies, LM318 or LF351 should be used.

PROCEDURE:
1. Verify whether the op-amp is in good condition and set up the circuit as shown in the circuit
diagram.
2. Note down the amplitude and frequency of output waveform.

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CIRCUIT DIAGRAM:

DESIGN:

The required frequency, 1⁄(√6 2 )=1 KHz

Take C=0.1μF .Then R=650Ω.Use 680Ω.

Gain ⁄ =29.

Take =1.2 k and =34.8 k

Use Rf =47k (pot)

EXPECTED GRAPH

RESULT:
Designed and setup the oscillator circuit and obtained the output waveform.

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5. PRECISION RECTIFIER USING OP-AMP

AIM:
To setup and study half wave and full wave rectifiers using op-amp.

COMPONENTS AND EQUIPMENTS REQUIRED:

 Op-amp(IC 741)
 Diode (1N4001)
 Resistors
 DC source,
 DSO
 Bread board

THEORY:
Half Wave Rectifier
An inverting voltage follower can be converted into an ideal half wave rectifier by adding 2
diodes. When is positive, become negative and the diode D1 gets forward biased. At this
moment diode D2 is reverse biased. When becomes –ve becomes +ve and D2 gets forward
biased. If a sinusoidal wave is applied at ,+ve going ripples appear at output point V2 and –ve
going ripples appears at output pointV1.
Op-amp rectifier is also called precision rectifier because it is able to rectify very low
amplitude signals. Ordinary diode rectifiers need minimum input voltage of the order of cut in
voltage of the diode .Op-amp rectifiers also provides gain.

Full Wave Rectifier

A full wave rectifier is also called absolute value circuit. Amplifier A1 works as an
inverting amplifier always and A2 works in 2 modes depending upon the polarity of input voltage;
one in inverting mode and other in non-inverting mode.
When is +ve, D1 conducts and D2 does not conduct.Both amplifiers are functioning in
inverting mode. When becomes –ve D1 does not conduct and D2 conduct.The equivalent circuit
diagram will show that A1 works as inverting amplifier and A2 works as non-inverting
amplifier.So irrespective of the polarity of the input voltage output turns to be +ve always.The
limitation of the circuit is that it does not have high input impidence.

PROCEDURE
1. Verify whether the op-amp is in good condition and set up the circuit as shown in the circuit
diagram.
2. Feed 100 mVpp sine wave at input.
3. Observe and plot the output waveform.

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CIRCUIT DIAGRAM:
HALF WAVE RECTIFIER

FULL WAVE RECTIFIER

DESIGN:
Here, gain is assumed to be 1.
Then R=R1=1K and diode used is IN4001.

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WAVE FORMS:

RESULT:
Designed and setup the circuit and obtained the output waveforms

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6. TRIANGULAR AND SAWTOOTH WAVE GENERATORS

USING OP-AMPS
AIM:
(1)To generate triangular wave using Op-Amp for a frequency of 1 kHz.
(2)To generate saw tooth wave using Op-Amp for a frequency of 1 kHz.

COMPONENTS AND EQUIPMENTS REQUIRED:

 Op-amp
 Resistors
 Capacitors
 Power supplies
 DSO and bread board.

THEORY:
1. Triangular Wave Generator:
We know that the integrator output waveform will be triangular if the input to it is square
wave. It means that a triangular-wave generator can be formed by simply cascading an integrator
and a square-wave generator. A triangular wave generator consists of a comparator and an
integrator. The comparator compares the voltage continuously with an inverting input that is at 0V
and produces a square wave The input of integrator is a square wave and its output is a triangular
waveform, the output of integrator will be triangular wave only when R3C> T/ 2 where T is the
period of square wave.
Suppose that the output of the first op-amp is at +Vsat. Since this voltage is the input of the
integrator, the output of second op-amp will be a negative going ramp. Thus one end of voltage
divider R1 and R2 is at +Vsat and other at negative going ramp. When negative going ramp attains
-Vramp, the effective voltage at non inverting terminal of first op-amp become slightly less than
zero volt. this switches output of first op-amp from +Vsat to -Vsat. Then output of the second op-
amp will be a positive going ramp. When the voltage at non inverting terminal of first op-amp is
just above zero volt, the output switches to +Vsat. The cycles repeat and generate a triangular
waveform. The frequency of triangular waveform is given by, = .

The peak to peak amplitude of triangular waveform or ramp voltage is Vramp (p-p) =
2. Saw tooth Wave Generator:
The saw tooth wave generators have wide application in time-base generators and pulse width
modulation circuits. The difference between the triangular wave and saw tooth waveform is that the
rise time of triangular wave is always equal to its fall of time while in saw tooth generator; rise time
may be much higher than its fall of time, vice versa. By using diodes and pot the duty cycle can be
varied.
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PROCEDURE:
TRIANGULAR WAVE GENERATION

1. Connections are made as per the circuit diagram

2. Give the biasing voltage as power to the IC
3. Observe the square wave output at 1st op-amp sixth pin and triangular wave output
at 2nd op-amp sixth pin.
4. Calculate the frequency and amplitude of the square and triangular wave observed
from the DSO.
5. Compare the practical values obtained with the theoretical values
SAWTOOTH WAVE GENERATION

1. Connections are made as per the circuit diagram

2. Give the biasing voltage as power to the IC
3. Observe the output at 1st op-amp sixth pin and output at 2nd op-amp sixth pin.
4. Move the wiper of the potentiometer in both directions and observe the changes
taking place in the waveforms.
5. Calculate the frequency and amplitude of the saw tooth wave observed from the
DSO.
6. Compare the practical values obtained with the theoretical values

CIRCUIT DIAGRAM:
(a) TRIANGULAR WAVE GENERATION

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(b)SAWTOOTH WAVE GENERATION

DESIGN:
(1)TRIANGULAR WAVE GENERATION

Frequency = , f=1 kHz

Peak to peak output of ramp, =2
Let be 10 V and =13 V
Assume =1k .
Then 10= 2 ∗ 13
= 384.6  (Use 330  )
Also, take C=0.1 μF =
Substituting these values, we get = 6.5 . (Use 22 k pot std)

(2) SAWTOOTH WAVE GENERATION

Frequency = , f=1 kHz

Peak to peak output of ramp, =2
Let be 10 V and =13 V
Assume =1k . Then = 330  .Also, take C=0.1 μF
Substituting these values, we get = 6.5 . (Use 22 k pot).
Select = 47 pot.

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EXPECTED GRAPH
TRIANGULAR WAVE GENERATION SAWTOOTH WAVE GENERATION

RESULT:
Designed and set up triangular and sweep wave generators using op-amp and obtained the
output waveforms.

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 6. WIEN BRIDGE OSCILLATOR
AIM:
To design and setup a wien bridge Oscillator using op-amp for a frequency of 1 kHz with
and without amplitude stabilization.
COMPONENTS AND EQUIPMENTS REQUIRED:

 DC source,
 DSO and bread board
 Op-amp
 Potentiometer
 Capacitor
 Resistors
THEORY:
This is an audio frequency oscillator of high stability and simplicity. The feedback signal
in this circuit is connected to the non-inverting input terminal so that the op-amp is working as a
non-inverting amplifier. Therefore, the feedback network need not provide any phase shift. This
circuit can be viewed as a wein bridge with a series RC network in one arm and parallel RC
network in the adjoining arm. Resistors and are connected in the remaining 2 arms.The
condition of zero phase shift around the circuit is achieved by balancing the bridge. The
frequency of oscillation is the resonant frequency of the balanced bridge and is given by the
expression 1 ⁄2 .From the analysis of the circuit, it can be seen that the feedback factor
β=1/3 at the frequency of oscillation .Therefore, for the sustained oscillation, the amplifier must
have a gain of 3.
PROCEDURE:
1. Verify whether the op-amp is in good condition and set up the circuit as shown in the
circuit diagram.
2. Note down the amplitude and frequency of output waveform.

CIRCUIT DIAGRAM:

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DESIGN:
1⁄( 2 )= 1 kHz
Take C=0.1μF .Then R=1.6kΩ.
Use 1.5kΩ.

Gain 1+ ⁄ =3.

Take =1 k and =2.2 k use 4.7 kpot.

OUTPUT WAVEFORM:

RESULT:
Designed and set up wein bridge oscillator using op-amp and obtained the output
waveforms

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 8. ASTABLE AND MONOSTABLE MULTIVIBRATOR USING
OP-AMP

AIM:

(1)To design and set up an astable multivibrator using op-amp for frequency of oscillation 1 kHz.
(2) To design and set up a monostable multivibrator using op-amp for pulse width of 1ms.

COMPONENTS AND EQUIPMENTS REQUIRED:

 Power supply
 DSO
 Op-amp(IC 741)
 Resistors
 Capacitors
 Bread board.

THEORY:

Astable multivibrator:
Astable multivibrator is capable of producing square wave for given frequency,
amplitude and duty cycle. The output of the op-amp is forced to swing repetitively between
positive saturation +Vsat and negative saturation –Vsat resulting in a square wave output. This
circuit is also called free running multivibrator or square wave generator. The output of the op-
amp will be in positive saturation if differential input voltage is negative and vice versa. The
differential voltage Vd=Vo−βVsat, where β is the feedback factor and βVsat is the potential at
non-inverting terminal of the op-amp.
Consider the instant at which the Vo=+Vsat. Now the capacitor charges exponentially
towards +Vsat through R, automatically Vd increases and crosses zero. This happens when
Vc=+βVsat. The moment Vd becomes positive due to further charging of the capacitor, output
charges to –Vsat. Now capacitor starts discharging to zero and recharges towards –Vsat. Now Vd
decreases and crosses zero. this happens when Vc=-βVsat. The moment Vd becomes negative
again, output changes to +Vsat. Thus completes one full cycle.
The time period T of the square wave is T = 2RC ln , where β = . If β is made ½ ,
T= 2.2RC.Astable multivibrator is particularly useful for the generation of frequency in the audio
frequency range. Higher frequencies are limited by the delay time and slew rate of the op-amp.

Monostable Multivibrator:
A monostable multivibrator (MMV) is also called one shot. It has a stable state and a
quasi-stable state. The circuit remains in stable state until triggering signal causes a transition to
quasi-stable state. After a time interval, it returns to the stable state. a single output pulse is
generated when a trigger is applied.

Consider the instant at which the output Vo=+Vsat. Now the diode D1 clamps the capacitor

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voltage Vc at 0.7V. Feedback voltage available at the non-inverting terminal is +βVsat. When the
negative going trigger is applied such that the potential at non-inverting terminal becomes less
than 0.7V, the output switches to –Vsat. Now the capacitor charges Through R towards –Vsat,
because the diode becomes reverse biased. When the capacitor voltage becomes more negative
than –βVsat, the comparator switches to +Vsat and capacitor C starts charging to +Vsat through R
until Vc reaches 0.7V and C becomes clamped to 0.7V. The pulse width is given by T=RC ln
approximately. If β= 0.5, T=0.69RC. The time period of the trigger must be larger than the
output pulse width T. The circuit does not respond to a trigger that appears before the specified
output pulse width and hence it is called non- retriggerable monoshot.

PROCEDURE:

1. Verify whether the op-amp is in good condition wiring it as ZCD or voltage follower.
2. Set up the astable multivibrator observe the waveforms at pin nos.6 and 2 of the op-amp
using CRO and note down their amplitudes and frequencies.
3. Set up the monostable multivibrator and feed 6Vpp, 200Hz square wave at the trigger
input.
4. Observe the waveforms at pin nos.6 and 2 of the op-amp using CRO and note down
their amplitudes and frequencies.

CIRCUIT DIAGRAM:

(1)Astable Multivibrator (2) Monostable Multivibrator

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DESIGN:
(1)Astable multivibrator
Time Period, = 2 ln( )
Where, β =
Let β=0.5, Then R1=R2, Take R1=R2=10k
Given fO = 1kHz ,i.e., T=1 ms
When β=0.5, T=2.2RC
∗
Take C = 0.1 F Then, R = . ∗ = . ∗ . ∗
= 4.545k
Take R= 4.7k (std.)
(2)Monostable multivibrator

We have T= RC ln( )

Let β= 0.5, then T=0.69RC.

Given, pulse width, T=1ms
∗
Let C=0.1 then R = =
. . ∗ . ∗

R=14.5 K, use 15K (std).

Since β= , R1=R2=10K.
( )

For differentiating circuit RdCd<< 0.0016 Tt.

Trigger time should be greater than output pulse width of the multivibrator. Take trigger time
period Tt=0.5ms and Cd=0.01uF then Rd=8.2K.
EXPECTED GRAPH:
(1)Astable multivibrator: (2) Monostable Multivibrator:

RESULT: Designed and set up astable and monostable multivibrator using op amp and obtained
the output waveform.

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 9. ACTIVE SECOND ORDER LPF, HPF, BPF
AIM:
Design and set up
(i) A Second order low pass butterworth filter for a higher cut off frequency of 1 kHz
(ii) A Second order high pass butterworth filter for a lower cut off frequency of 1 kHz
(iii) A band pass filter having fo=1 kHz, Q=3 and gain Af=10
COMPONENTS AND EQUIPMENTS REQUIRED:

 Op-amp
 Resistors,
 Capacitors,
 DC source
 signal generator,
 bread board and CRO

THEORY:
Filters are frequency selective circuits. It is used to attenuate signals in certain frequency
ranges according to the requirement. There are active and passive filters. Passive filters are
simply RC network which passes a certain range of frequencies and attenuates other. Active
filters, in addition consists of some active components which provide gain. The roll off of a first
order filter is 20 dB/decade and that of the second order filter is 40 dB/ decade. A first order low
pass filter can be converted into a second order type simply by using an additional RC network.

Low Pass Filter:

An active Low Pass Filter attenuates high frequencies and passes low frequency signals. It
consists simply of a passive filter section followed by a non-inverting operational amplifier. The
frequency response of the circuit is the same as that of the passive filter, except that the
amplitude of the signal is increased by the gain of the amplifier and for a non-inverting amplifier
the value of the pass band voltage gain is given as 1 + Rf/R1, the same as for the low pass filter
circuit.
Consider the circuit diagram; at low frequencies, the capacitors appears open (since capacitive
reactance will be high at low frequencies) and voltage gain will be maximum. As the frequency increases,
the gain eventually starts to decrease.

The higher cut off frequency of the filter is given by the expression,
1
=
2
High Pass Filter:
An active high Pass Filter attenuates low frequencies and passes high frequency
signals. It consists simply of a passive filter section followed by a non-inverting operational
amplifier. The frequency response of the circuit is the same as that of the passive filter, except
that the amplitude of the signal is increased by the gain of the amplifier and for a non-inverting

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amplifier the value of the pass band voltage gain is given as 1 + Rf/R1, the same as for the low
pass filter circuit.
Consider the circuit diagram at low frequencies, the capacitors appears open (since
capacitive reactance will be high at low frequencies) and voltage gain approaches to zero. At
higher frequencies the capacitors appears short circuited and circuit becomes a non-inverting
amplifier. The cut off frequency of the filter is given by the expression,
1
=
2
Band Pass Filter:
The range of frequencies that a band pass filter passes is known as the ‘pass band’,
which is bound by a lower cut-off frequency fL and a higher cut-off frequency fH.

Procedure:

1. Set up the circuit and feed 2Vpp sine wave from the signal generator.
2. Vary the frequency of sine wave in steps and note down the corresponding output
voltage. Plot the frequency response on graph sheet.
3. Calculate the higher cutoff frequency from graph sheet.

CIRCUIT DIAGRAM:
Low Pass Filter:

High Pass Filter:

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Design:

Required cut off frequency =1 kHz

We have = , = =C and = =R
√

Therefore = =1 kHz

Let C=0.1μf. Then R=1.59 k, use 1.5k std.

For R2=R3=1.5k and C2=C3=0.1μf,

The pass band gain =1+ must be 1.58

Let R1=1k, 1+ = 1.586 ,Therefore Rf=586Ω, use 560Ω std.

Tabular column and waveform:

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 Frequency response of LPF Frequency response of HPF

RESULT:
Designed and set up active second order low pass, high pass and band pass filters using op-amp.

Obtained cut off frequency for LPF, fH= ……….

Obtained cut off frequency for HPF, fL= ……….

BPF, fo= ---------

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 10. ACTIVE BAND REJECTION (NOTCH) FILTER
AIM:
To design a notch filter to eliminate frequency of 1kHz.

COMPONENTS AND EQUIPMENTS REQUIRED:

 Op-amp (IC 741)

 Resistors
 Capacitors
 Signal generator
 Power supply
 DSO and bread board.

THEORY:

A Band-Stop Filter is a circuit that allows most frequencies to pass, but block or
attenuates a certain range or band of frequencies. It is also known as a ‘band-elimination filter or
a ‘band-rejection filter’. The band-stop filter is the opposite of the band-pass filter.

The range of frequencies that a band-stop filter blocks is known as the ‘stop band’, which
is bound by a lower cut-off frequency fL and a higher cut-off frequency fH. An ideal band-stop
filter is one whose stop band is completely rejected by it, while allowing all other frequencies to
pass unchanged. The narrow band reject filters which attenuate a certain frequency only, and
passes all other frequencies are called notch filters. The notch frequency is given by; =

PROCEDURE:
1. Set up the circuit and feed a 2 Vpp sine wave from a signal generator.
2. Vary the input frequency in steps and note down the corresponding output voltage.
3. Plot the frequency response and find the notch frequency from the graph.

Circuit Diagram:

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DESIGN:
Required frequency = =1 kHZ

Take C=0.01µF , then

1 ∗ 10 = ∗ . ∗

Then R=1.59k , take R=1.5k std.

Then, 2C=0.22µF and R/2=8.2K

TABULAR COLUMN and EXPECTED GRAPH:

frequency Out put voltage, Vo log f 20 log Vo/ Vin

in Volts

RESULT:
Designed and setup notch filter and plotted the frequency response, Obtained notch frequency, fN=……

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 11. TIMER IC-NE 555
AIM:

1) To design and set up an astable multivibrator using 555 timer

2) To design a monostable multivibrator using 555 timer for a 1ms pulse width

COMPONENTS AND EQUIPMENTS REQUIRED:

 555 Timer IC
 Capacitors
 Resistors
 DC Source
 DSO and Breadboard

THEORY:
555 timer is an analog IC used for generating accurate time delay or oscillation. This will
provide time delay ranging from microsecond to hours. Maximum operating frequency is in excess of 500
kHz. Output is TTL compatible. The 555 timer can be used with supply voltage in the range from +5 V to
+18 V and can drive load up to 200 mA.
Functional diagram of 555: The 5k internal resistor act as a voltage divider network, providing (2/3)Vcc
at the inverting terminal of upper comparator (UC) and (1/3)Vcc at the non inverting terminal of lower
comparator (LC). In the stable state, the Q output of the control flip flop is high. This makes the output
low because of the buffer which basically is an inverter.
Pin 1: Ground terminal
Pin 2 (Trigger): This pin is used to feed the trigger input when the chip is set up as a monostable
multivibrator. When a trigger of amplitude greater than (1/3)Vcc is applied to this terminal, circuit
switches to quasi stable stage.
Pin 4 (Reset): This terminal is used to reset the output of the circuit irrespective of the input. A logic low
input will reset the output. For normal operation this pin is connected to Vcc.
Pin 5 (Control): Voltage applied to this terminal will control the instant at which the comparator
switches and hence the pulse width of the output. When this pin is not used it is bypassed to ground using
a 0.01 µF capacitor.
Pin 6 (Threshold): If the voltage applied to the threshold terminal is greater than (2/3) Vcc, upper
comparator switches to +Vsat and flip flop output gets reset.

Pin diagram of 555 Functional Diagram of 555

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Astable multivibrator

555 timer IC can be made to function as an astable multivibrator.Initiaily capacitor C starts

charging through RA and RB towards Vcc with a time constant (RA + RB)C. During this time,. R = 0, S=1,
=0 and output (pin 3) is high (equal to Vcc). When capacitor voltage equals 2/3 Vcc, the upper
comparator triggers the control flip flop so that =1. This makes transistor Q1 ON and capacitor C starts
discharging towards ground through RB and transistor Q1 with a time constant RBC. During the discharge
of the timing capacitor C, as it reaches Vcc/3 the lower comparator is triggered and at this stage S =1, R=
0, which turns =0. This makes transistor Q1 OFF and again capacitor C starts to charge. Thus the
capacitor periodically charges and discharges between (2/3) Vcc and (1/3) Vcc. Output amplitude of the
square wave swings between 0.3 V to applied Vcc.
The charging period of the capacitor tc =0.69(RA + RB) C. The discharging period of the capacitor
td=0.69RBC. If tc = td, the duty cycle of the output waveform will be 1/2. In order to make tc and td equal
to each other, a diode is connected in parallel with RB such that capacitor charges through RA and diode,
and discharges through RB. Another method is using a resistor of same value of RA and RB between the
pin number 7 and the junction formed by RA and RB.

Monostable multivibrators

Monostable multivibrators are used to generate pulse waveforms of specified pulse width.
Consider the circuit and internal diagram of 555. In the stable state Q is low and in turn, Q1 turns on and
output goes low. When the negative going trigger goes lower than Vcc/3, the Flip Flop gets set and hence
Q becomes 1. This makes transistor Q1 off. The capacitor starts charging towards Vcc, which was earlier
clamped to zero. After a time period, the capacitor voltage becomes greater than (2/3) Vcc and upper
comparator resets the Flip Flop,that is, R=1,S=0. This makes =1.In turn, transistor Q1 turns ON and
thereby discharging the capacitor c rapidly to ground potential. The output returns to the stable state. The
time duration, of quasi-stable state is given by the equation, T=1.1RC seconds. Though it is possible to
apply the trigger purse directly to pin 2, trigger shown in figure is better because it makes narrow trigger
pulses applied to trigger terminal. Also it prevents the possibility of mistriggering the monostable
multivibrator on positive pulse edges.

PROCEDURE:
1) Connections are made as per the circuit diagram.

2) Switch on the D.C power supply and set the voltage to 10V.

3) Observe the o/p waveform at pin 3 using DSO & also observe the waveform across Capacitor (pin 6).
4) Measure the frequency of oscillations from the observed o/p and compare it with theoretical value.
5) Measure the Duty Cycle D= ( )
) from the observed o/p and compare it with theoretical value.
6) Sketch the waveforms on graph sheet.

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CIRCUIT DIAGRAM:
Astable Multivibrator using 555: Monostable Multivibrator using 555:

DESIGN:
Astable Multivibrator using 555

Take Vcc=10V and tc=1ms, td=0.5ms

We have td=0.69RBC

Take C=0.1 µF

0.5m=0.69*RB*0.1µ, then RB= 7.25k (use 7.2k std.)

1m=0.69*(RA+7.2k)*0.1µ, then RA =

.Choose C1= 0.01µF

Monostable Multivibrator using 555

Take Vcc=10V .We have T=1.1RC, Take C=0.1µF.

1m= 1.1*R*0.1µ, then R=

Designing trigger circuit:

We have R1C1≤ 0.016T, there T1 is the time period of trigger.

Let T1 be 3mS.Take R1=5.6K then C1=0.01µF.

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EXPECTED GRAPH:
Astable Multivibrator using 555

Monostable Multivibrator using 555

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