1.

Draw the cross-sectional view of NMOS with all terminals including

body.

2. Draw the 3-D diagram of a NMOS and mark Width and length.

3. Explain the working of MOS in accumulation, depletion and inversion

regions of operation with voltage conditions
● As Vg (Gate Voltage) is negative, the positive carrier in p-substrate (for
nmos) is accumulated beneath the gate, forming Accumulation region.
● As a small voltage is applied at the gate terminal, the positive charge
beneath the gate gets repelled, leaving behind negative ions, forming
Depletion region.
● Increasing the voltage at the gate, the positive charge gets repelled
further and negative charge carriers are formed beneath the gate. The
conducting layer of electrons in p-substrate is called the inversion
region.
Fig 3 - Accumulation region of nmos

Fig 4 - Depletion region of nmos

Fig 5 - Inversion region of nmos

4. Define threshold voltage of a MOSFET. What is the mathematical
expression for Vt
The gate voltage at which strong inversion occurs is known as threshold
voltage of MOSFET. Strong Inversion means the concentration of electrons at
the inversion region is approximately equal to the concentration of holes in
p-substrate or concentration of holes accumulated in accumulation region.

where,

γ = body-effect coefficient φF = Fermi potential

Vt0 = threshold voltage without Qbo = Charge density of depletion

body bias region per unit area

φs = Surface potential at threshold Qox = Charge density of oxide

Vsb = Source-Body voltage region per unit area

Φms = Work function difference Cox = Oxide capacitance per unit

area

5. What is body bias? Write the threshold voltage equation with body bias
The voltage applied at the body of the MOSFET that prevents the conduction
of the parasitic diodes formed between Source-Body and Drain-Body is known as
Body Bias. This is one of the parameters that affects the threshold voltage of
MOSFET.
6. What will happen if the substrate voltage in an NMOS is a) +ve b) -ve -
give reason
There will be formation of parasitic diode between S-B and D-B
● If the substrate voltage of nmos is positive then the parasitic diode
becomes forward bias, so a large amount of current flows in the diode.
As a result of this high heat gets dissipated. Another effect is that the
electrons get attracted to the substrate regions, holes left behind. Then
the depletion region beneath the gate becomes narrower, Vth required
decreases.

● If the substrate voltage of nmos is negative, then the parasitic diode

becomes reverse biased, This results in a wider depletion region and it
becomes more difficult for the inversion region to be formed. Thus it
increases Vth.

.
7. What will happen to Threshold voltage of an NMOS if a) substrate doping
is increased b) source doping is increased
a. As the substrate doping in nmos is increased, the concentration of
electrons decreases. So the voltage required to form an inversion layer
increases, that is Vth increases.
b. As the source doping in nmos is increased, there will be a large
concentration of electrons. So the voltage required to form an inversion
layer decreases, that is Vth decreases.
8. What will happen to Vt if Tox is increased?
As the tox i.e The thickness of the oxide increases, the Vg required for
the formation of the inversion region increases, this increases the Vth.

9. What is the meaning of strong inversion?

The term strong Inversion means the concentration of electrons at the inversion
region is approximately equal to the concentration of holes in p-substrate or
concentration of holes accumulated in the accumulation region. At this region
the semiconductor surface inverters from p to n type.
10. Derivation
11. What is roughly the Vt in 28nm technology?
The Vt in 28nm technology is 0.2 to 0.3 V.
12. What is the meaning of pinch-off?
Pinch-off means the channel near the drain at which there is no charge
density, that is the channel is no longer inverted near the drain.
13. Why do we have a tapered channel? Explain with equations.
The charge density of the channel is directly proportional to (Vgs-Vth-V(x)).
When Vds = Vgs-Vth, then the channel charge density drops to zero. The
channel charge density at source is maximum and it is minimum at drain. This
causes the tapered effect in the channel.

14. Why is the width of the depletion region at drain larger as compared to
source?
The width of the depletion region at drain and source is based on the voltage
applied at the drain and source terminal. As the drain voltage
(Vds≥Vgs-Vth) is larger than source voltage (source voltage is zero), the width
of the depletion region at drain is larger as compared to source.
15. Why does a negative body potential increase the depletion region for
NMOS? What is its effect on Vt?
When Vbs is applied with negative potential, then parasitic diodes (S-B, D-B)
become reverse biased, more holes get attracted to the substrate terminal,
leaving a larger negative charge behind, this increases the depletion region of
the nmos. Since the depletion width is increased and Vt is proportional to Vsb,
Vt is increased by this effect.
16. Draw the cross-sectional view with both NMOS and PMOS on a single
silicon with the body terminals
 17. What will happen to Vt if temperature is increased?( we will discuss this)
If temperature is increased, there will be a shift in fermi level and band gap
energy. As a result of this, the Vt decreases.
18. Write down the voltage conditions for Linear and Saturation regions of
operation for PMOS transistor.

Cutoff Vgs > Vth

(or)
Vsg < |Vth|

Linear Vgs ≤ Vth,

Vds > Vgs-Vth
(or)
Vsg ≥ |Vth|,
Vsd < Vsg-|Vth|

Saturation Vgs ≤ Vth,

Vds ≤ Vgs-Vth
(or)
Vsg ≥ |Vth|,
Vsd ≥ Vsg-|Vth|

19. What is leakage current? Write down 3 major components of leakage.

Show the current flow direction of these components with a diagram.
Leakage current : Even when the transistor is OFF, they leak a small amount
of current. It doesn't act like a perfect/pure switch. This current is called
leakage current.
Major components of leakage current :
1. Subthreshold leakage
Theoretically, we assumed that current flows in nmos only if Vgs > Vt.
But in reality, current doesn’t drop abruptly to 0 for Vgs ≤ Vt, rather it decays
exponentially. This effect is called subthreshold or weak inversion conduction
and this current is called subthreshold leakage. This is caused by the diffusion
current in the minority carrier of mos. The Id for this region is

By equation, we can understand that subthreshold leakage increases

significantly as Vds increases. To depict this, the below image shows
subthreshold leakage at Vds = 1.05v and 0.5v.

To limit the subthreshold leakage, we will use the slope factor S,

The current flow direction of subthreshold current is given below.

2. Gate leakage
As transistors are getting scaled down, the thickness of the gate-oxide
layer reduces, this causes the carriers crossing the gate-oxide and results in
leakage current through the gate. This type of leakage is called Gate Leakage.

3. Junction leakage
There are parasitic diodes formed between Source-Body and Dain-Body.
The body is tied to GND to avoid body-effect. However, reversed biased diodes
still conduct a small amount of current. This effect is called Junction Leakage.
The reverse biased current for the parasitic diode is given as
20. Identify the region of operation for the transistors

21. Draw the ID vs VDS (for VGS1, VGS2 and VGS2>VGS1) and ID vs VGS (for
VDS1,VDS2 and VDS2>VDS1)
22, 23 From simulation - tabulate Idsat(max saturation current) Ioff for an
NMOS transistor under the following PVT condition

TEMPERATURE VARIATION

PVT CORNER Id(sat) Id(off)

TT_-40c_1.0v 41.3876μA 1.6772nA

TT_25c_1.0v 38.4451μA 9.1947nA

TT_125c_1.0v 33.6911μA 48.040nA

VOLTAGE VARIATION

TT_25c_0.9v 31.6558μA 5.8269nA

TT_25c_1.0v 38.4451μA 9.1947nA

TT_25c_1.1v 45.1579μA 14.3715nA

PROCESS VARIATION

SS_25c_1v 29.0022μA 0.3898nA

TT_25c_1.0v 38.4451μA 9.1947nA

FF_25c_1.0v 50.6466μA 320.8221nA

24. Plot simulation waveform for id (i(vss) vs vgs) for -40c and 125c @TT,1.0v
25. For Q 22 a), b) and c) – explain with logic/equations the trend of Ion current
values
26. For Q 23 a), b) and c) – explain with logic/equations the trend of Ioff current
values with complete subthreshold leakage current equation.
a) Temperature variation
Increasing temperature has two effects
1. Increasing temperature decreases mobility
As temperature increases, thermal vibration in the lattice
increases, giving rise to scattering of electrons. So electrons collide with
each other and hence contributing less streamline flow needed for the
flow of electric current. Hence the mobility decreases. The relationship
is given in below equation

Hence mobility decreases in increasing temperature.

2. Increasing temperature decreases Vth
The equation for Vth is given below.

At high temperature Φf decreases due to the shift of Fermi Level. The

fermi level shift with increase in temperature for n-type and p-type
semiconductor is shown below.
 Hence Vth decreases in increasing temperature

From the equation,

i) Temperature increases, mobility reduces, Id reduces
ii) Temperature increases, Vth reduces, Id increases.
Both are opposing effect, which effect dominates is depended upon the
voltages
At high Vgs, the difference between Vgs and Vt is so high, so the
overdrive voltage doesn’t dominate, the mobility dominates. Hence
Ion reduces as temperature increases.
At low Vgs, both the Vgs and Vt are so close, slight change in Vt
will have more impact in overdrive voltage. So (Vgs-Vt)2 dominates.
Hence Ion increases as temperature increases.

The subthreshold leakage current depends only on Vth. As the

temperature increases, Vth reduces due to the shift of fermi level, the Vgs - Vth
increases, I(leakage) increases.
b) Voltage Variation
From the equation

We can understand that as voltage increases (Vgs or Vds), the Ion increases.

The above subthreshold leakage equation also shows that increasing voltage,
the Ioff or I(leakage) also increases.
c) Process Variation
The process variation impacts impurity concentration densities, oxide
thicknesses, diffusion depths and so on. The change in these parameters reduces the
Vth from SS, TT and FF. So that the Ion current increases from SS, TT and FF.
Similarly the I(leakage) current also increases.
27. What is GIDL. Explain with id vs vgs graph.
GIDL stands for Gate Induced Drain Leakage. It occurs where the gate
partially overlaps the drain. This effect is high when the drain is at high potential and
the gate is at low potential. Due to this strong electric field, electron-hole pair
generation occurs, the electrons go to the drain region and holes to the substrate,
causing the net flow of current from drain to body. Instead of the current Id going to 0,
the current increases in negative potential of Vgs. This effect is called as GIDL.
28. What is the subthreshold slope? What are the typical values? How is it used
to define Vt of a transistor?
Subthreshold slope determines how much Vgs have to be reduced for the drain
current to drop by a factor of 10. The equation is given as

It is expressed as mV/decade. If n=1, and (KT/q)ln(10) evaluates to

60mV/decade. it means that Id drops down by the factor of 10 for every 60mV
reduction of gate-to-source voltage.
The typical value of subthreshold slope is 60 to 90mV/decade.
We want a good ratio of Ion:Ioff for a mosfet to behave as a good switch. This
can be determined with the help of the Subthreshold slope.

So if the Vgs is reduced by 360mV, the subthreshold current reduces by the factor of
104. By this we can determine Vth, so that there is a good ratio between Ion and Ioff.
29. How does mobility and Vt vary with temperature?
i) Temperature increases, mobility reduces, Id reduces
ii) Temperature increases, Vth reduces, Id increases.
30. Plot Id vs Vds for n105_hvt, n105, n105_lvt models (25c, 1.05v)

Ion Ioff

n105_hvt 199.2uA 7.055pA

n105 41.813uA 1.417pA

n105_lvt 281.581uA 1.588pA

31. Plot I(vss) vs Vgs for

a) SS_-45c_0.9v, SS_125c_0.9v
 b) TT_-45c_1.0v,TT_125c_1.0v

c) FF_-45c_1.0v,FF_125c_1.1v

31. What is temperature inversion? Explain with logic and equation.

The change in temperature in mos can increase or decrease the drain current
based on the voltage (Vgs) applied. For low Vgs, the drain current increases with
temperature i.e., it exhibits positive temperature coefficient for lower values of Vgs.
For High Vgs, the drain current decreases with temperature i.e., it exhibits negative
temperature coefficient for higher values of Vgs. This phenomenon is called
temperature inversion.
Explanation-
Increasing temperature has two effects
1. Increasing temperature decreases mobility
As temperature increases, thermal vibration in the lattice
increases, giving rise to scattering of electrons. So electrons collide with
each other and hence contributing less streamline flow needed for the
flow of electric current. Hence the mobility decreases. The relationship
is given in below equation

Hence mobility decreases in increasing temperature.

2. Increasing temperature decreases Vth
The equation for Vth is given below.

At high temperature Φf decreases due to the shift of Fermi Level. The

fermi level shift with increase
in temperature for n-type and
p-type semiconductor is shown
below.
Hence Vth decreases in increasing temperature

From the equation,

i) Temperature increases, mobility reduces, Id reduces
ii) Temperature increases, Vth reduces, Id increases.
Both are opposing effect, which effect dominates is depended upon the
voltages
At high Vgs, the difference between Vgs and Vt is so high, so the
overdrive voltage effect doesn’t dominate, the mobility effect
dominates. Hence Ion reduces as temperature increases.
At low Vgs, both the Vgs and Vt are so close, slight change in Vt
will have more impact in overdrive voltage. So (Vgs-Vt)2 effect
dominates. Hence Ion increases as temperature increases.
In the below example of TT_1.0v, at -40c and 125c, the
simulation results show that till the crossover point (0.53v,13.05uA) i.e.,
at low Vgs, the overdrive voltage effect dominates as a result of that the
drain current increases with temperature. After the crossover point i.e.,
at higher Vgs where the difference between Vgs and Vt is quite large,
the mobility effect dominates as a result the drain current decreases with
increase in temperature.
32. Plot id vs vgs for
a) ss/0.9v/m40 & ss/0.9v/125c

b) tt/1.0v/m40 & tt/1.0v/125c

c) ff/1.1v/m40 & ff/1.1v/125c

and tabulate the crossover point for the 3 cases.

 Crossover point

1. SS_0.9v_-40c (0.7v,12.803uA)

SS_0.9v_125c

2. TT_1.0v_-40c (0.53v,13.05uA)

TT_1.0v_125c

3. FF_1.1v_-40c (0.33v, 13.086uA)

FF_1.1v_125c

33. Tabulate the Ion and Ioff values for n105, n105_hvt and n105_rvt at
SS/0.9v/125, SS/0.9v/m40c, TT/1.0v/25c, FF/1.1/m40c, FF/1.1v/125c

n105 n105_hvt n105_lvt

Ion Ioff Ion Ioff Ion Ioff

SS_0.9_-40c 23.62uA 19.91pA 178.83uA 20.37pA 178.83uA 193.073nA

SS_0.9_125c 21.01uA 3.171nA 69.00uA 18.34nA 164.2uA 1.374uA

TT_1.0_-40c 41.39uA 1.677nA 283.6uA 35.33pA 216.8uA 416.9nA

TT_1.0_125c 33.69uA 48.04nA 119.6uA 22.58nA 198.5uA 2.174uA

FF_1.1_-40c 64.18uA 268.9nA 361.8uA 24.36pA 417.7uA 66.04uA

FF_1.1_125c 49.15uA 952.6nA 232.3uA 3.028nA 357.2uA 44.91uA

34. What are the different capacitances of a MOS transistor? Write down the
formula based on physical parameters of the device(no derivation reqd) Draw
the RC model of a transistor.
1. Oxide related capacitance
a. Cgs - Gate-Source capacitance
b. Cgd - Gate-Drain capacitance
c. Cgb - Gate-Body capacitance
d. Overlap capacitance
i. Cgso - Gate-Source overlap
capacitance
 ii. Cgdo - Gate-Drain overlap capacitance
2. Junction Capacitance
a. Cgs(diff) - Gate-Source diffusion capacitance
b. Cds(diff) - Gate-Drain diffusion capacitance
The formulas for these capacitance are

The parallel plate capacitance of MOS is given as

where Cper micron is considered as a technology parameter. By varying Width of the

transistor we can change the capacitance.
35. How to configure the transistor as a diode? What is the conduction condition?
When the Gate and Drain terminal of MOS are shorted, then it acts as a diode
connected transistor.
In this configuration Vds will always be greater than
Vgs-Vth, so it will be either in cutoff or saturation not in
linear mode of operation. Based on voltage applied
between drain and source, it can be forward or reverse
biased.
36. How to use the transistor as a capacitor? How will you change the value of
this capacitor?
When the Drain and Source terminal of MOS
are shorted, then it acts like a capacitor, in which
SiO2 will behave as an insulator.
Keeping the voltage and length of the device
constant, we can change the value by changing the
width of the MOS.
37. Draw the detailed layout views of inverter, nand2 and nor2 gate with
diffusion, poly, contact, metal layers
Inverter
Nand

Nor
38. Draw the parasitic model RC of M1,M2 & M3 layers where M1 is bottom,
M2 middle and M3 is the top layer.

39. Explain latch up with a diagram. How to prevent latchup?

Latch-up occurs when the parasitic diode formed by the
substrate-well-diffusion turns on.
● NPN - N-diffusion of NMOS, P-type substrate,
N-well
● PNP - P-diffusion of PMOS, N-type substrate,
P-well
● Rsub,Rwell - Resistance to substrate or well to
the nearest substrate or well.
Latch-up can be triggered when current flows
through the substrate. If current flows, Vsub raises,
turning ON NPN. This pulls current through Rwell, bringing down Vwell, turning ON
PNP. This raises Vsub, forming a positive feedback loop between Vdd and Vss. This
continues until power is turned off or melting the wires.
To prevent latches
1. Minimizing Rsub and Rwell.
2. Using n+ and p+ guard ring in NMOS and PMOS tied to power rails
3. NMOS should to clustered together near Vss and PMOS to Vdd
40. What is DRC and LVS. What are tools to verify DRC, LVS?
DRC stands for Design Rule Check, it checks whether the layout is drawn
according to the design rules (minimum width, minimum spacing and minimum
overlap) and it can be manufacturable.
LVS stands for Layout vs Schematics. It checks whether the layout is drawn
according to schematics. It verifies by comparing the netlist of the layout and
schematics.
Few tools to verify DRC and LVS are
1. Calibre (Cadence)
2. IC Validator (Synopsys)
3. Hercules (Silicon Creations)
41.Why do we use diffusion sharing in nand/nor layout?

We use shared diffusion and merged diffusion to

1. Reduce overall area of layout
2. Reduces parasitic capacitances
3. Simplifies the manufacturing process.
42. Explain what is
a. CLM (with id-vds graph and equation)
Ideally, Ids is independent of Vds in saturation. But, when Vds≥Vgs-Vth, the
depletion region between the drain-body increases, thus the effective length of the
channel reduces. Due to this, Ids gradually increase with Vds at saturation. This
phenomenon is known as Channel Length Modulation.

b. Velocity saturation (show it in id-vds

graph)
When Vds is increased, the electric field
along the channel reaches a critical value (Ec)
and the carrier saturates at maximum velocity
vsat. Thus the device enters into saturation
before Vds reaches Vgs-Vth. This effect is
known as Velocity Saturation.
c. DIBL (with diagram and its effect)
Ideally, it is assumed that the depletion region is solely formed due to the gate
voltage and the depletion charge beneath the gate are from MOS field effects. But a
part beneath the gate is already depleted from Source-Body and Drain Body junctions
and the Drain-Body depletion width increases by increasing Vds. This reduces the
amount of Vgs to form strong inversion. Thus Vt reduces. This effect is called DIBL
(Drain Induced Barrier Lowering). It increases the subthreshold leakage at high Vds.
d. Punch through (with diagram)
When higher than normal Vds is applied, the depletion regions of Source/drain
get overlap. Thus source - drain region gets shorted together causing abnormal flow of
high current and ultimately self-destroying the device.
This effect can be reduced by setting an upper Vds limit or by halo doping.

e. Hot electron effect (with diagram).

The increase in electric field increases the velocity of carriers and they get
injected to gate oxide and become trapped there. It can damage the atomic structure of
Drain due to impact ionisation. Thus altering the electric behaviour of Oxide and
Drain.
 This effect can be reduced by introducing LDD (Lightly Doped Drain) in
MOS during fabrication. It reduces the electric field at Drain junction, thus increasing
the immunity of the device to hot electron damage.

43. Draw the transfer curve of the inverter and show the NMOS, PMOS region of
operation in 5 important transition points of the curve.

Points nmos pmos

A Cutoff Linear

B Saturation Linear

C Saturation Saturation

D Linear Saturation

E Linear Cutoff
44. Draw the cross-sectional view of an inverter with all electrical connections.

45. 45. Plot the DC transfer curve of an inverter with .dc analysis.

46. Derive the trip point equation and find out the conditions for vdd/2 trip point.
Trip point is the point at which both the transistors are in the saturation region.
For Vin = Vdd/2 the conditions are
1. Vtn = -Vtp
2. βn = βp
a. Ln = Lp
b. μn = 2μp
c. Wn = 2Wp
47. Simulate the DC transfer curve for wn=wp, wn=2wp, wn=1/2 wp and note
down the trip points.

Width of the device Trip Points Wn, Wp

Wn = Wp 0.4v 100n, 100n

Wn = 2Wp 0.3v 100n,200n

Wn = ½ Wp 0.5v 100n,50n
48. Run a .tran simulation and observe the delay of an inverter.
 For Wn = 200n, Wp = 100n. The propagation delay are
Tpdf = V1 - V2 = 1.63n - 2.95n = 0.86ns
Tpdr = V4 - V3 = 18.37n - 17.5n = 0.87ns
49. Explain why the trip point shifts in Q46.
1. From the equation of Vinv, as the Wn increases, the βn increases. So the trip
point shifts towards the left.

2. As the width of the nmos increases, the nmos becomes stronger and output trips
at low Vin. As a result of this, the trip point shifts towards the left.

50. For a transistor, explain which of the following corners will have ( & why)
1. Max leakage : FF_1.1v_125c
● The FF process has low Vt compared to other processes.
● For high Vds = 1.1v, the DIBL increases.
● For high temperature(125c), the threshold voltage decreases.
Ultimately, the low Vt causes the subthreshold leakage to increase and is
maximum compared to other PVT corners.
2. Min leakage : SS_0.9v_-40c
● The SS process has high Vt compared to TT, FF process.
● For Low Vds = 0.9v, the DIBL is low.
● For low temperature (-40c), the threshold voltage increases.
 Ultimately, the high Vt causes the subthreshold leakage to decrease and
is maximum compared to other PVT corners.

3. Max Idsat : FF_1.1v_-40c

● The FF process has low Vt compared to other processes.
● For high Vgs = 1.1v, the overdrive voltage becomes high.
● After the crossover point, the effect of mobility is high in (-40c)
compared to (125c).
For low threshold, high Vgs and lower temperature, The FF_1.1v_-40c
will have maximum drain current.
4. Min Idsat : SS_0.9v_125c
● The SS process has high Vt compared to TT, FF process.
● For Low Vgs = 0.9v, the overdrive voltage decreases.
● For high temperature (125c), the threshold voltage is reduced.
For higher threshold, low Vgs and higher temperature, The
SS_0.9v_125c will have minimum drain current.

51. Tabulate the delay of the inverter TPLH and TPHL for the following
a) Load variation - CL – 1f, 10f,20f for 200n/100n at TT,1v,25c
b) Size variation - 200n/100, 400n/200n, 800n,400n for CL=10f at
TT,1v,25c
c) Vt/process variation – CL=10f, 200n/100n, SS,TT,FF @ 1v, 25c
d) Supply variation CL=10f, 200n/100n, supply – 0.9v , 1v, 1.1v @TT,25c
 TT_1v_25c, Wp/Wn=200n/100n

CL Tpdf Tpdr

1f 25.18ps 31.87ps

10f 150.8ps 132.3ps

20f 287.6ps 242.4ps

CL= 10f, TT_1v_25c

Wp/Wn Tpdf Tpdr

200n/100n 150.8ps 132.3ps

400n/200n 90.9ps 85.8ps

800n/400n 55.6ps 53.8ps

CL = 10f, 1v_25c,Wp/Wn=200n/100n

Process Tpdf Tpdr

ss 219.1ps 205.8ps

ff 119.7ps 112.5ps

tt 150.8ps 132.3ps

CL = 10f, TT_25c,Wp/Wn=200n/100n

Supply Tpdf Tpdr

0.9v 180.4ps 188.1ps

1v 163.0ps 154.4ps

1.1v 150.8ps 132.3ps

51. Write relationship of gate delay w.r.t transistor size, load capacitor, vt and
supply voltage ( directly proportional or inversely proportional).
● Delay is inversely proportional to transistor size.
● Delay is directly proportional to load capacitor.
● Delay is directly proportional to vt.
● Delay is inversely proportional to process.
● Delay is inversely proportional to supply voltage.
52. Write the propagation delay of an inverter in terms of RC time constant.
Tpdf = 0.69RnCL
Tpdr = 0.69RpCL
where,Rp, Rn = Effective resistance of pmos and nmos
CL = Load capacitance = Sum of diffusion capacitance of first stage inverter,
gate capacitance of next stage inverter and wire load capacitance.
53. Write capacitor charge/discharge equation.
Charging equation : I = CL*(dv/dt)
Discharging equation : I = -CL*(dv/dt)
54. With help of above two equations- explain the trend of delays in Q50 a), b), c)
and d)
1. Capacitance variation
As the load capacitance increases, the time required to charge or
discharge the capacitance increases. Hence the delay of the circuit increases.
● From the equation, the capacitance is directly proportional to delay. So
increasing capacitance increases the delay.
Tpdf = 0.69RnCL
Tpdr = 0.69RpCL
● From the equation, the capacitance increases then dv/dt (the rate of
change of the output voltage w.r.t time) decreases, hence the delay
increases.
Charging equation : I = CL*(dv/dt) Discharging equation : I = -CL*(dv/dt)
2. Transistor size variation
As the transistor size increases, the current increases, the time required
to charge or discharge the capacitance decreases. Hence the delay of the circuit
decreases.
● As the transistor size increases, the drain current increases, this reduces
the Rp or Rn. Since Rp or Rn is directly proportional to the delay,
decreasing effective resistance decreases delay.
● As the transistor size increases, the drain current increases, the dv/dt
increases. Hence the delay decreases.
3. Process variation
As the process varies from SS to FF, the current increases, the time
required to charge or discharge the capacitance decreases. Hence the delay of
the circuit decreases.
● As the process varies (from SS to FF), the drain current increases, this
reduces the Rp or Rn. Since Rp or Rn is directly proportional to the
delay, decreasing effective resistance decreases delay.
● As the process varies (from SS to FF), the drain current increases, the
dv/dt increases. Hence the delay decreases.
4. Supply voltage variation
As the supply voltage increases, the current increases, the time required
to charge or discharge the capacitance decreases. Hence the delay of the circuit
decreases.
● As the voltage increases, the Id current increases and Rp or Rn reduces.
Since Rp or Rn is directly proportional to the delay, decreasing effective
resistance decreases delay.
● As the voltage increases,the drain current increases, the dv/dt increases.
Hence the delay decreases.
54.Which of the corners will have min and max delay assuming constant load
cap and transistor size and why
SS,0.9v,m40c ; SS,0.9v,125c; FF,1.1v,125c; FF,1.1v,m40c
1. Minimum delay - FF_1.1v_-40c
2. Maximum delay - SS_0.9v_125c
SS_0.9v_-40c
● For the SS process, the Vt is high, the Id current decreases. As the
current decreases, the time taken to charge or discharge the load
increases. Hence delay increases.
● For a low voltage of 0.9v, the drain current decreases, the delay
increases.
● For a low temperature of -40c, the mobility increases, as a result the
current increases. The time taken to charge or discharge the load
decreases. Hence the delay decreases.
SS_0.9v_125c
● For the SS process, the Vt is high, the Id current decreases. As the
current decreases, the time taken to charge or discharge the load
increases. Hence delay increases.
● For a low voltage of 0.9v, the drain current decreases, the delay
increases.
● For a high temperature of 125c, the mobility decreases, as a result the
current decreases. Hence the delay increases.
FF_1.1v_125c
● For the FF process, the Vt is low, the Id current increases. As the current
increases, the time taken to charge or discharge the load decreases.
Hence delay decreases.
● For a high voltage of 1.1v, the drain current increases, the delay
decreases.
● For a high temperature of 125c, the mobility decreases, as a result the
current decreases. Hence the delay increases.
 FF_1.1v_-40c
● For the FF process, the Vt is low, the Id current increases. As the current
increases, the time taken to charge or discharge the load decreases.
Hence delay decreases.
● For a high voltage of 1.1v, the drain current increases, the delay
decreases.
● For a low temperature of -40c, the mobility increases, the current
increases. Hence the delay decreases.
FF_1.1v_-40c < FF_1.1v_125c < SS_0.9v_-40c < SS_0.9v_125c
55. Measure the delay from input to output of 4 inverters connected in series.

TT_1.1_25c

Tpdf 24.41ps

Tpdr 15.88ps
56. Simulate the circuit and measure the delay from A to X, B to Y, C to Z

A -> X Tpdf 24.39ps

B -> Y Tpdf 295.5ps

C -> Z Tpdr 24.39ps

57. For Q 55, simulate at a) SS/0.9/125, SS/0.9v/m40 and b)SS/0.6v/125 ,
SS/0.6v/m40c

PVT CORNERS Tpdf Tpdr

a. SS/0.9/125 44.93ps 40.89ps

SS/0.9/-40 55.38ps 46.86ps

b. SS/0.6/125 124.3ps 118.5ps

SS/0.6/-40 304.7ps 236.9ps

58. Identify the ckts

a. Latch
b. Ring Oscillator
59. From Q 55 – determine the stage delay of one inverter.

TT_1.1_25c

Tpdf 24.41ps

Tpdr 15.88ps
𝑛 𝑠𝑡𝑎𝑔𝑒 𝑑𝑒𝑙𝑎𝑦
Single stage delay = 𝑛
60. Simulate a 11 stage ring oscillator and measure one period from the
waveform. Write the formula for one period in terms of stage delay of an
inverter. You can run the simulation at SS/0.9v/125c

One cycle period = 208.05ps

For 11-stage inverter, the delay is 22Tp = 208.05ps
208.05
For one inverter, the gate delay, Tp = 22
= 9.45ps

Formula for one period in terms of stage delay of an inverter is

T = 2N * (Delay of single stage inverter)
61.How will you predict the approx. value of o/p with logic ( w/o simulation)

From 0.3(Vt) < 0.4 < 0.5 (Vdd/2) , the region of nmos and pmos is
NMOS saturation = PMOS linear
Ids(sat) = Isd(linear)
β𝑛 2 𝑉𝑠𝑑
2
(𝑉𝑔𝑠 − 𝑉𝑡𝑛) = β𝑝 (𝑉𝑠𝑔 − 𝑉𝑡𝑝 − 2
)𝑉𝑠𝑑

Since Wp = 2Wn, the β𝑝 = β𝑛

2 (1−𝑉𝑜𝑢𝑡)
(0. 4 − 0. 3) = 2 * (0. 6 − 0. 3 − 2
)(1 − 𝑉𝑜𝑢𝑡)
 (1−𝑉𝑜𝑢𝑡)
(0. 05) = (0. 3 − 2
)(1 − 𝑉𝑜𝑢𝑡)
0.6−1+𝑉𝑜𝑢𝑡
(0. 05) = ( 2
)(1 − 𝑉𝑜𝑢𝑡)
𝑉𝑜𝑢𝑡−0.4
(0. 05) = ( 2
)(1 − 𝑉𝑜𝑢𝑡)

(0. 1) = (𝑉𝑜𝑢𝑡 − 0. 4) − 𝑉𝑜𝑢𝑡(𝑉𝑜𝑢𝑡 − 0. 4)

2
(0. 1) = (𝑉𝑜𝑢𝑡 − 0. 4) − 𝑉𝑜𝑢𝑡 + 0. 4𝑉𝑜𝑢𝑡
2
𝑉𝑜𝑢𝑡 − 1. 4𝑉𝑜𝑢𝑡 + 0. 5 = 0
Solving the above equation, we will get Vout = 0.7
62. What will be the o/p the ckt. (only analysis no simulation)

1. in = Vdd
a. For the nmos, 𝑉𝑔𝑠 = 𝑉𝑖𝑛 − 𝑉𝑜𝑢𝑡 > 𝑉𝑡𝑛. When
𝑉𝑜𝑢𝑡 = 𝑉𝑑𝑑 − 𝑉𝑡𝑛 it reaches the minimum voltage required
to turn nmos ON. So the maximum voltage level output
charged to is 𝑉𝑑𝑑 − 𝑉𝑡𝑛.
2. in = 0
a. For the pmos, 𝑉𝑠𝑔 = 𝑉𝑜𝑢𝑡 − 𝑉𝑖𝑛 > |𝑉𝑡𝑝|. When
𝑉𝑜𝑢𝑡 = |𝑉𝑡𝑝| it reaches the minimum voltage required to
turn pmos ON. So the maximum voltage output discharged to
is |𝑉𝑡𝑝|.
In this configuration, NMOS passes weak 1 and PMOS passes weak 0.
63. What are the two criteria that designers use for determining P:N ratio of an
inverter based on Tplh,Tphl ?
1. P:N ratio at which there is approximately equal rise and fall delay occurs.
2. P:N ratio at which there is minimum delay occurs.

64. How do we size a chain of inverters for optimum delay – write down the 3
criteria.
1. Each stage delay must be equal.
2. The size of one inverter is the geometric mean of the adjacent inverters.
3. For optimum delay, the ratio of each inverter can be 4.
65. Measure the delay between point A to B in the three circuits (three different
simulations with different sizes of the inverter chain) . If the transistor size is
>1000n , you can use micron(u) as a unit e.g. 1000n=1u. Corner SS/0.9v/125c
 Tph Tpl Tp

a. 49.71ps 49.53ps 49.62ps

b. 68.90ps 66.71ps 67.81ps

c. 52.89ps 52.89ps 52.89ps

66. In Q56, explain the waveform at Node Y. Which is the victim and aggressor
node in this ckt. How can we reduce cross talk?
As the width of I1 and I3(800/400) is large compared to the width of
I2(200/100). The nodes X and Z have high signal capacity. As the node X and Z
switches(from Vdd to 0), it pulls the node Y down to 0 before it can reach Vdd, thus
increasing the switching delay of node Y due to capacitive coupling.
The signal capacity is weaker. Victim - Y
The signal capacity is stronger. Aggressor - X and Z
To reduce the cross talk by
1. Reducing the signal strength of the aggressor by reducing the width of the
aggressor.
2. Increasing the driving capacity of the victim node by increasing the width.
3. By reducing the coupling capacitance.

Before After

A -> X 24.39ps 70.33ps

B -> Y 295.5ps 22.80ps

C -> Z 24.39ps 70.33ps

67. What are the two components of dynamic power? Derive the equation for
switching power of an inverter with load cap.
The two components of dynamic power
1. Switching power
2. Short-circuit power
𝑃(𝑑𝑦𝑛𝑎𝑚𝑖𝑐) = 𝑆𝑤𝑖𝑡𝑐ℎ𝑖𝑛𝑔 𝑝𝑜𝑤𝑒𝑟 + 𝑆ℎ𝑜𝑟𝑡 𝐶𝑖𝑟𝑐𝑢𝑖𝑡 𝑝𝑜𝑤𝑒𝑟
The energy consumption from the supply is given as
𝐸 = 𝑉𝑣𝑑𝑑 𝐼(𝑡)𝑑𝑡
𝑑𝑉𝑜𝑢𝑡
𝐼(𝑡) = 𝐶𝐿 𝑑𝑡
𝑑𝑉𝑜𝑢𝑡
𝐸 = 𝑉𝑣𝑑𝑑 𝐶𝐿 𝑑𝑡
𝑑𝑡
𝐸 = 𝑉𝑣𝑑𝑑 𝐶𝐿𝑑𝑉𝑜𝑢𝑡
𝑉𝑑𝑑

𝐸 = 𝑉𝑣𝑑𝑑 𝐶𝐿 ∫ 𝑑𝑉𝑜𝑢𝑡
0
𝐸 = 𝑉𝑣𝑑𝑑 𝐶𝐿[𝑉𝑑𝑑]

2
𝐸 = 𝐶𝐿𝑉𝑣𝑑𝑑
2
𝐶𝐿𝑉𝑣𝑑𝑑
2
𝑃= 𝑇
𝑜𝑟 𝐶𝐿𝑉𝑣𝑑𝑑 𝑓

The energy stored in the capacitor is given as

𝐸 = 𝑉𝑜𝑢𝑡𝐼(𝑡)𝑑𝑡
𝑑𝑉𝑜𝑢𝑡
𝐼(𝑡) = 𝐶𝐿 𝑑𝑡
𝑑𝑉𝑜𝑢𝑡
𝐸 = 𝑉𝑜𝑢𝑡𝐶𝐿 𝑑𝑡
𝑑𝑡
𝐸 = 𝑉𝑜𝑢𝑡𝐶𝐿𝑑𝑉𝑜𝑢𝑡
𝑉𝑑𝑑

𝐸 = 𝐶𝐿 ∫ 𝑉𝑜𝑢𝑡𝑑𝑉𝑜𝑢𝑡
0
2
𝑉𝑜𝑢𝑡
𝐸 = 𝐶𝐿[ 2
]

In summary, each switching cycle takes fixed amount of energy equal to

2
2 𝑉𝑜𝑢𝑡
𝐶𝐿𝑉𝑣𝑑𝑑 from the supply. During charging, 𝐶𝐿[ 2
] is stored in the capacitor and

2
𝑉𝑜𝑢𝑡
𝐶𝐿[ 2
] dissipated from the pmos.
68. What is short circuit current? Draw the SC current waveform w.r.t input
transition and DC transfer curve.
Write the formula for SC current.
In the transfer curve, from Vtn to Vdd-Vtp, both pmos and nmos will be
ON, the current flows from Vdd to Vss and it will be maximum at Vdd/2. This
current is called a Short-circuit current.

Formula for SC power-

𝑃𝑆𝐶 = (𝑉𝐷𝐷 − 2𝑉𝑇) * 𝐼𝑆𝐶 * 𝑓 * 𝑡𝑟(𝑓)

69. Measure & tabulate dynamic I(vvdd) for an inverter for the following
a) For CL – 1f, 5f, 10f ( load variation) @TT/1v/25c , 200n/100n
b) For VDD – 0.9v, 1v, 1.1v ( voltage variation) for CL=5f, 200n/100n, at
TT,25c
c) For Wp/wn – 200n/100n , 400n/200n , 800n/400n ( width variation) for
CL=5f, 200n/100n, @TT/1v/25c
d) For SS/1v/25c, TT/1v/25c, FF/1v/25c for constant CL=5f ( process
variation) , 200n/100n
e) FF/1v/-40c, FF/1v/25c, FF/1v/125c for constant CL=5f ( temp variation) ,
200n/100n
70. Measure & tabulate static I(vvdd), I(vvss) for an inverter for Q 68 by
choosing a proper timing window.
 Load Variation [TT/1v/25c , 200n/100n]

CL Dynamic power Static power

I(vvss) I(vvdd) Static ‘0’ Static ‘1’

1f 583.7nA 578.70nA 9.192nA 4.482nA

5f 2.576uA 2.574uA 9.192nA 4.790nA

10f 5.070uA 5.072uA 9.192nA 4.465nA

1. Dynamic power
2
𝑃𝑑𝑦𝑛𝑎𝑚𝑖𝑐 = 𝐶𝐿𝑉𝑣𝑑𝑑 𝑓 + 𝑉𝑣𝑑𝑑𝐼𝑠𝑐 𝑡𝑟(𝑓)𝑓

From the above equation, as CL increases, the switching power increases, then
the dynamic power also increases.
2. Static power
𝑃𝑠𝑡𝑎𝑡𝑖𝑐 = 𝑉𝑣𝑑𝑑𝐼𝑠𝑢𝑏
𝑉𝑔𝑠−𝑉𝑡+η𝑉𝑑𝑠−𝑘𝑉𝑠𝑏 −𝑉𝑑𝑠
𝑛𝑣𝑇 𝑣𝑇
𝐼𝑠𝑢𝑏 = 𝐼𝑜𝑓𝑓𝑒 [1 − 𝑒 ]

As the subthreshold current doesn’t depend on the load variation, increasing

load doesn’t affect the static power. We are measuring the static power when
the capacitor is completely charged or discharged.

Voltage Variation [CL=5f, 200n/100n, at TT,25c]

VVDD Dynamic power Static power

I(vvss) I(vvdd) Static ‘0’ Static ‘1’

0.9v 2.313uA 2.313uA 5.825nA 3.115nA

1v 2.576uA 2.574uA 9.192nA 4.790nA

1.1v 2.841uA 2.838uA 14.370nA 6.388nA

1. Dynamic power
2
𝑃𝑑𝑦𝑛𝑎𝑚𝑖𝑐 = 𝐶𝐿𝑉𝑣𝑑𝑑 𝑓 + 𝑉𝑣𝑑𝑑𝐼𝑠𝑐 𝑡𝑟(𝑓)𝑓
 From the above equation, 𝑃𝑑𝑦𝑛𝑎𝑚𝑖𝑐 is proportional to the Vvdd, increasing the

supply voltage increases both switching power as well as short-circuit power,

thus the dynamic power increases.
2. Static power
𝑃𝑠𝑡𝑎𝑡𝑖𝑐 = 𝑉𝑣𝑑𝑑𝐼𝑠𝑢𝑏
𝑉𝑔𝑠−𝑉𝑡+η𝑉𝑑𝑠−𝑘𝑉𝑠𝑏 −𝑉𝑑𝑠
𝑛𝑣𝑇 𝑣𝑇
𝐼𝑠𝑢𝑏 = 𝐼𝑜𝑓𝑓𝑒 [1 − 𝑒 ]
−𝑉𝑑𝑠
𝑣𝑇
As the supply voltage varies, the Vds increases, increasing the [1 − 𝑒 ] and
DIBL factor, the subthreshold current increases and 𝑃𝑠𝑡𝑎𝑡𝑖𝑐 is also proportional

to Vvdd, the static power increases.

Width Variation [CL=5f, 200n/100n, @TT/1v/25c]

WP/WN Dynamic power Static power

I(vvss) I(vvdd) Static ‘0’ Static ‘1’

200n/100n 2.576uA 2.574uA 9.192nA 4.790nA

400n/200n 2.70uA 2.696uA 85.56nA 27.79nA

800n/400n 2.994uA 2.986uA 257.9nA 94.97nA

1. Dynamic power
2
𝑃𝑑𝑦𝑛𝑎𝑚𝑖𝑐 = 𝐶𝐿𝑉𝑣𝑑𝑑 𝑓 + 𝑉𝑣𝑑𝑑𝐼𝑠𝑐 𝑡𝑟(𝑓)𝑓

As the width of the transistor increases, the Ids through the device increases,
increasing the short-circuit power. Hence the dynamic power also increases.
2. Static power
𝑃𝑠𝑡𝑎𝑡𝑖𝑐 = 𝑉𝑣𝑑𝑑𝐼𝑠𝑢𝑏
𝑉𝑔𝑠−𝑉𝑡+η𝑉𝑑𝑠−𝑘𝑉𝑠𝑏 −𝑉𝑑𝑠
𝑛𝑣𝑇 𝑣𝑇
𝐼𝑠𝑢𝑏 = 𝐼𝑜𝑓𝑓𝑒 [1 − 𝑒 ]

As the 𝐼𝑜𝑓𝑓∝ 𝑊, the 𝐼𝑠𝑢𝑏 increases, ultimately increasing the static power.
 Process Variation [CL=5f, 200n/100n]

Process Dynamic power Static power

I(vvss) I(vvdd) Static ‘0’ Static ‘1’

SS/1v/25c 2.562uA 2.563uA 389.1pA 553.2pA

TT/1v/25c 2.576uA 2.574uA 9.192nA 4.790nA

FF/1v/25c 2.798uA 2.763uA 318.5nA 63.86nA

1. Dynamic power
2
𝑃𝑑𝑦𝑛𝑎𝑚𝑖𝑐 = 𝐶𝐿𝑉𝑣𝑑𝑑 𝑓 + 𝑉𝑣𝑑𝑑𝐼𝑠𝑐 𝑡𝑟(𝑓)𝑓

As the process varies from ss to ff, the Ids through the device increases,
increasing the short-circuit power. Hence the dynamic power also increases.
2. Static power
𝑃𝑠𝑡𝑎𝑡𝑖𝑐 = 𝑉𝑣𝑑𝑑𝐼𝑠𝑢𝑏
𝑉𝑔𝑠−𝑉𝑡+η𝑉𝑑𝑠−𝑘𝑉𝑠𝑏 −𝑉𝑑𝑠
𝑛𝑣𝑇 𝑣𝑇
𝐼𝑠𝑢𝑏 = 𝐼𝑜𝑓𝑓𝑒 [1 − 𝑒 ]

As the process varies, the Vt reduces, the 𝐼𝑠𝑢𝑏 increases, the static power also

increases.

Temperature Variation [CL=5f, 200n/100n]

Temp Dynamic + Static power Static power

I(vvss) I(vvdd) Static ‘0’ Static ‘1’

FF/1v/-40c 2.681uA 2.658uA 152.1nA 9.327nA

FF/1v/25c 2.798uA 2.763uA 318.5nA 63.86nA

FF/1v/125c 3.118uA 3.082uA 677.1nA 385.3nA

1. Dynamic power
2
𝑃𝑑𝑦𝑛𝑎𝑚𝑖𝑐 = 𝐶𝐿𝑉𝑣𝑑𝑑 𝑓 + 𝑉𝑣𝑑𝑑𝐼𝑠𝑐 𝑡𝑟(𝑓)𝑓
 As the temperature increases, the Ids through the device decreases (due to the
mobility effect), decreasing the short-circuit power. Hence the dynamic power
also decreases.
2. Static power
𝑃𝑠𝑡𝑎𝑡𝑖𝑐 = 𝑉𝑣𝑑𝑑𝐼𝑠𝑢𝑏
𝑉𝑔𝑠−𝑉𝑡+η𝑉𝑑𝑠−𝑘𝑉𝑠𝑏 −𝑉𝑑𝑠
𝑛𝑣𝑇 𝑣𝑇
𝐼𝑠𝑢𝑏 = 𝐼𝑜𝑓𝑓𝑒 [1 − 𝑒 ]

As the temperature increases, the Vt reduces, Isub increases. Hence the static
power also increases.
71. Take the buffer chain of Q 65 (1) and measure static and dynamic current
at SS/0.9v/125, SS/0.9v/m40c, TT/1.0v/25c, FF/1.1/m40c, FF/1.1v/125c
72. For Q71, create a column for (Dynamic- static) for true dynamic current.

PVT Dynamic+Static Static power Dynamic power

power

I(vvss) I(vvdd) I(vvss) I(vvdd) I(vvss) I(vvdd)

SS/0.9v/125c 6.166uA 6.086uA 4.869uA 1.432uA 1.297uA 4.654uA

SS/0.9v/m40c 2.523uA 2.839uA 87.72nA 25.45nA 1.645uA 2.584uA

TT/1.0v/25c 10.93uA 10.48uA 11.15uA 2.567uA - -

FF/1.1v/m40c 107.2uA 96.67uA 151.7uA 38.88uA - -

FF/1.1v/125c 334.3uA 307.2uA 459.9uA 167.2uA - -

1. SS/0.9v/125c
● For the SS process, the dynamic power and static power is less
compared to TT and FF.
● For 0.9v, the dynamic power and static power is less compared to 1.0v
and 1.1v
● For 125c, the static power increases and dynamic power reduces.
2. SS/0.9v/m40c
● For the SS process, the dynamic power and static power is less
 compared to TT and FF.
● For 0.9v, the dynamic power and static power is less compared to 1.0v
and 1.1v
● For m40c, static power is reduced and dynamic power is increased.
3. TT/1.0v/25c
● For the TT process, the dynamic power and static power is high
compared to SS and low compared to FF.
● For 1.0v, the dynamic power and static power is high compared to 0.9v
and low to 1.1v.
● For 25c, the static power is high compared to m40c and less compared
to 125c. The dynamic power is low compared to m40c and high
compared to 125c.
4. FF/1.1v/m40c
● For FF processes, the static and dynamic power is very high.
● For 1.1v, the static and dynamic power is high.
● For m40c, static power is low and dynamic power is increased.
5. FF/1.1v/125c
● For FF processes, the static and dynamic power is very high.
● For 1.1v, the static and dynamic power is high.
● For 125c, static power increases and dynamic power reduces.
Static power
𝑆𝑆/0. 9𝑣/𝑚40𝑐 < 𝑆𝑆/0. 9𝑣/125𝑐 < 𝑇𝑇/1. 0𝑣/25𝑐 < 𝐹𝐹/1. 1𝑣/𝑚40𝑐 < 𝐹𝐹/1. 1𝑣/12
Dynamic power
𝑆𝑆/0. 9𝑣/125𝑐 < 𝑆𝑆/0. 9𝑣/𝑚40𝑐 < 𝑇𝑇/1. 0𝑣/25𝑐 < 𝐹𝐹/1. 1𝑣/125𝑐 < 𝐹𝐹/1. 1𝑣/𝑚40
73. Design a 2:4 decoder with inverter and nand gates and measure
a) delay b) dynamic c) static d) true dynamic current at
SS/0.9v/125, SS/0.9v/m40c, TT/1.0v/25c, FF/1.1/m40c, FF/1.1v/125c

PVT Delay Dynamic + Static Static True dynamic

(s) current current current
(A) (A) (A)

Tp I(vvdd) I(vvss) I(vvdd) I(vvss)

SS/0.9/125c 72.596p 411.952n 463.644n 62.565n 349.387n 401.078n

SS/0.9/-40c 80.308p 347.082n 397.690n 2.5571n 344.524n 395.133n

TT/1.0/25c 41.603p 487.617n 547.928n 54.969n 432.649n 492.959n

FF/1.1/-40c 24.351p 1.7031u 1.7718u 847.745n 855.966n 924.131n

FF/1.1/125c 28.205p 7.4238u 7.4913u 6.3553u 1.0685u 1.1360u

Delay : FF/1.1/-40c < FF/1.1/125c < TT/1/25c < SS/0.9/-40c < SS/0.9/125c
Static current : SS/0.9/-40c < SS/0.9/125c < TT/1/25c < FF/0.9/-40 < FF/0.9/125c
Dynamic current:SS/0.9/125c < SS/0.9/-40c < TT/1/25c < FF/0.9/125c < FF/0.9/-40c

PVT Delay Dynamic + Static Static True dynamic

(s) current current current
(A) (A) (A)

Tp I(vvdd) I(vvss) I(vvdd) I(vvss)

SS/0.9/125c 71.907ps 632.23n 733.31n 32.166n 600.06n 701.14n

SS/0.9/-40c 78.069ps 587.16n 689.82n 39.252p 587.20n 689.86n

TT/1.0/25c 42.883ps 761.23n 880.22n 36.332n 724.90n 843.89n

FF/1.1/-40c 25.570ps 1.859u 1.995u 659.30n 1.1990u 1.3360u

FF/1.1/125c 29.087ps 5.124u 5.259u 3.7850u 1.3380u 1.4737u

74. Derive the P:N ratio for nand2, nor2, nand3, nor3, nand4, nor4 using a 2:1
inverter as reference. Compare the total width of transistors ( P and N combined)
between a) nand2 & nor2 , b) nand3 & nor3, c) nand4 & nor4.
Reference inverter
1. nand2

a1 a0 y

0 0 1 PMOS best case

0 1 1 PMOS worst
case
1 0 1

1 1 0 NMOS

𝑃: 𝑁 𝑟𝑎𝑡𝑖𝑜 𝑓𝑜𝑟 𝑁𝐴𝑁𝐷2 𝑖𝑠 2 : 2 𝑜𝑟 1 : 1

2. nor2

a1 a0 y

0 0 1 PMOS

0 1 0 NMOS Worst
case
1 0 0

1 1 0 NMOS Best
case

𝑃: 𝑁 𝑟𝑎𝑡𝑖𝑜 𝑓𝑜𝑟 𝑁𝑂𝑅2 𝑖𝑠 4 : 1

3. nand3

a2 a1 a0 y

0 0 0 1 PMOS best
case
 0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1 PMOS
worst case

1 1 1 0 NMOS
𝑃: 𝑁 𝑟𝑎𝑡𝑖𝑜 𝑓𝑜𝑟 𝑁𝐴𝑁𝐷3 𝑖𝑠 2 : 3
4. nor3

𝑃: 𝑁 𝑟𝑎𝑡𝑖𝑜 𝑓𝑜𝑟 𝑁𝑂𝑅3 𝑖𝑠 6 : 1

5. nand4

𝑃: 𝑁 𝑟𝑎𝑡𝑖𝑜 𝑓𝑜𝑟 𝑁𝐴𝑁𝐷4 𝑖𝑠 2 : 4 𝑜𝑟 1 : 2

6. nor4

𝑃: 𝑁 𝑟𝑎𝑡𝑖𝑜 𝑓𝑜𝑟 𝑁𝑂𝑅4 𝑖𝑠 8 : 1

Width

a. NAND2 8u

NOR2 10u

b. NAND3 15u

NOR3 21u

c. NAND4 24u

NOR4 36u
75. What is the equation for equivalent width of n transistors connected in a)
parallel b) series – draw the series and parallel diagrams
a. Parallel
𝑊 = 𝑊1 + 𝑊2

b. Series
(𝑊1)(𝑊2)
𝑊 = 𝑊1+𝑊2

76. Why do we have static power

consumption in the gate? Show with the help of an inverter.
In an inverter if Vin=Vss, then pmos turns ON, instead of the nmos completely
turning OFF, the subthreshold leakage current flows in nmos. Similarly if Vin=Vdd,
the nmos turns ON and the subthreshold leakage current flows in PMOS. In
conclusion, during the static input, the subthreshold leakage current flows in the OFF
device, hence there is static power consumption.
77. Design a 4:16 decoder with two 2:4 decoder and inv,nand gates and measure
the delay of the circuit. Use 1:1 ratio for 2 input nand gates.

PVT TPHH TPHL TP

SS/0.9/125c 67.270ps 96.066ps 81.668ps

SS/0.9/-40c 83.871ps 105.52ps 94.695ps

TT/1.0/25c 34.441ps 51.566ps 43.003ps

FF/1.1/125c 19.601ps 38.161ps 28.880ps

FF/1.1/-40c 15.732ps 28.915ps 22.323ps

78. Draw the diagram of a 4:1 mux driven by a 2:4 decoder. Simulate the
circuit and measure delay.
 PVT TPLL1 TPLL2 TPHH1 TPHH2 TP

SS/0.9/125c 19.365ps 19.376ps 20.097ps 20.510ps 19.837ps

SS/0.9/-40c 24.802ps 24.801ps 27.507ps 27.682ps 26.198ps

TT/1.0/25c 7.8916ps 7.8863ps 7.6031ps 7.7261ps 7.772ps

FF/1.1/125c 2.5628ps 2.2304ps 2.6595ps 2.5009ps 2.4884ps

FF/1.1/-40c 2.4011ps 2.3764ps 2.8387ps 2.5707ps 2.5467ps

79.Why do we prefer/advantage of nand gate over nor gate? Show an example.
The optimum width of Nand gate is less than Nor gate. Lesser width implies
lesser area, lesser gate and diffusion capacitance. This reduces the delay and dynamic
power consumption. Due to lesser area, delay and dynamic power consumption, we
prefer Nand gate over Nor gate.

TT/1.1v/125c

Delay True Dynamic

NAND4 1.9516ps 1.2582u

NOR4 16.991ps 4.4891u

80. What happens when we short 2 inverter outputs? Show with simulation what
happens to o/p voltage and current. When is it allowed to short 2 inverter o/ps?
If we are shorting two inverter outputs
1. For the same inputs the capacitor gets fully charged or discharged, so no
problem occurs.
2. For different inputs, the output goes to an undermined state.
a. For equal strength inverters, the output may go to VDD/2.
b. If the strength of I1 is greater than I2, then the output of I1 gets
dominated.
c. If the strength of I2 is greater than I1, then the output of I2 gets
dominated.
3. In case of current, the ON device of each inverter gets shorted and larger ISC
flows through it.

The shorted output of the inverter is allowed only if the inputs are shorted.
81. What is a tristate gate? Draw the ckt of a tristate inverter and simulate. Why
do we need a tristate gate? Show an example.
Tristate gate : Tristate has three states - 0, VDD, High ‘Z’. Tristate controls whether
or not to connect the input to output. When the control is 0, then it doesn’t allow the
input to pass to output and gives High ‘Z’ state. When the control is 1, then the input
gets passed to output.
Circuit diagram of Tristate inverter
The simulated output

Delay_in_r_out_f, 𝑇𝑝 = 2. 7663𝑝𝑠 @𝑇𝑇/1. 05/25𝑐

We need the tristate gate to ensure that the output doesn’t go to the undermined
state while shorting the outputs.
In the below circuit, when device1 needs to
transmit the data, it activates tristate_1 by enabling cntrl
and transfers the in1 to output. At the same time, the
tristate_2 goes to a high impedance state and effectively
disconnects itself from the output. Thereby preventing
the undermined state and reducing the overall short
circuit current.
82. Which circuit configurations can be used when we
have to connect multiple o/ps?
1. We can use the tristate gate when we have to short
multiple outputs.
2. We can use the pass gate when we have to short
multiple outputs.
83. Why should we not have floating input – what can it cause in silicon?
Simulate a floating inverter and observe current and voltage. Compare the
current waveform when switching input voltage is applied.
If there is a floating input,
1. The output will be undefined.
2. There will be a large flow of Short-circuit current over an undefined period of
time. This damages the silicon.
 FF/-40c/1.1v

Delay_in_r_x_f 8.4919ps

Delay_in_r_out_f 12.229ps

Pure dynamic current 1.0134uA

Short circuit current 24.921uA

84. Draw the pass transistor logic implementation for the following (refer chapter
6.19 of the book).
F=AB , F=A+B, F=invert(AB) , F= invert(A+B)
F=A XOR B F=A XNOR B
What is the advantage and disadvantage of these implementation over
gates
1. F = AB

A B F NMOS PTL

0 0 0 When A = 0, F = 0

0 1 0

1 0 0 When A = 1, F = B

1 1 1
2. F = A+B

A B F

0 0 0 When A = 0, F = B

0 1 1

1 0 1 When A = 1, F = 1

1 1 1
3. F = invert(AB)

A B F

0 0 1 When A = 0, F = 1

0 1 1

1 0 1 When A = 1, F =
B’
1 1 0
4. F = invert(A+B)

A B F

0 0 1 When A = 0, F =
B’
0 1 0

1 0 0 When A = 1, F = 0

1 1 0
5. F = A XOR B

A B F

0 0 0 When A = 0, F = B

0 1 1

1 0 1 When A = 1, F =
B’
1 1 0
 6. F = XNOR B

A B F

0 0 1 When A = 0, F = B’

0 1 0

1 0 0 When A = 1, F = B

1 1 1
1. The advantage of this PTL implementation is
that a lesser number of transistors can be used.
2. Disadvantage : Since the NMOS is the weak conductor of ‘Vdd’, the logic
high output is degraded.

85. What will be V1, V2, V3 in the following ckt - analyse with theory

At V1, 𝑉𝑔𝑠 = 1𝑉 − 0. 7𝑉 = 0. 3𝑉 = 𝑉𝑡 At V1, 𝑉𝑠𝑔 = 0. 3𝑉 − 0𝑉 = 0. 3𝑉 = 𝑉𝑡

At V2, 𝑉𝑔𝑠 = 0. 7𝑉 − 0. 4𝑉 = 0. 3𝑉 = 𝑉𝑡 At V2, 𝑉𝑠𝑔 = 0. 3𝑉 − 0𝑉 = 0. 3𝑉 = 𝑉𝑡
At V3, 𝑉𝑔𝑠 = 0. 7𝑉 − 0. 4𝑉 = 0. 3𝑉 = 𝑉𝑡 At V3, 𝑉𝑠𝑔 = 0. 6𝑉 − 0. 3𝑉 = 0. 3𝑉 = 𝑉𝑡
86. Draw a resistive inverter and a nand gate with PMOS load. Why is it called a
ratioed logic? What are the disadvantages?

Resistive inverter Nand gate with PMOS load

● Ratioed logic : The output of the gate depends on the ratio of pull-up and
pull-down network of the device.
● Disadvantages
1. The PMOS will always be ON, so there is a large Short-circuit current
flowing from VDD to GND.
2. There will be logic HIGH and LOW signal degradation.
88. Draw a basic dynamic nand gate with clock and show its timing diagram?
What are the common issues of a basic dynamic gate? How do we overcome the
issues with the help of Domino dynamic gate + PMOS keeper? What is the main
issue with Domino gates?
Basic dynamic nand gate with clock
Timing diagram of dynamic logic nand
Common issues of basic dynamic gate
1. Charge leakage - When the output is pre charged and during evaluation phase,
if the pull-down network is off, ideally the output should remain at VDD. But it
leaks away due to leakage current, This causes degradation at output HIGH
level.
2. Charge Sharing - For the given circuit,if input ‘A’ changes its state from 0 ->
1, the N1 turns on, then the charge originally stored in CL is redistributed over
CL and CA.. Therefore there occurs a drop in output
voltage level.
3. Capacitive coupling - When the output is pre charged
and during evaluation phase, if the pull-down network
is off, then the output will be at a high impedance state.
While cascading the gate will be subjected to cross-talk
effect.
4. Cascading Dynamic gate - There will be a finite
amount of propagation delay for the output capacitance
to discharge the output to GND. When this output is
cascaded to the input of the next dynamic gate, there will be loss of charge at
the next stage output, which can not be recovered.
To solve the above issues, we are using domino logic + PMOS keeper

● The P2 and P4 (Keeper transistor), are always ON during the high impedance
state. This eliminates the charge leakage and capacitive coupling issue in
dynamic logic.
● To ensure all the inputs of the next stage dynamic gate are set to 0 at the end of
pre-charge phase, we are using a static inverter at the output of each stage. This
solves the problem of cascading issues in dynamic logic.
Main issues with domino logic
1. Since we are using a static inverter, only non-inverting logic can be
implemented.
89. Define VOH, VOL, VIL and VIH. Draw the diagram showing the relative
position of the four voltage levels for a system to work properly. Define Noise
margin.
1. VOH - The minimum voltage at which the output is considered to be in a logic
HIGH state.
2. VOL - The maximum voltage at which the output is considered to be in a logic
LOW state.
3. VIL - The maximum voltage for which the input can rise for the system to
recognize as logic LOW.
4. VIH - The minimum voltage for which the input can drop for the system to
recognize as logic HIGH.
Diagram showing the relative position of the four voltage levels for a system to work
properly

Noise Margin - The allowable noise voltage at the input of a gate so the output will
not be corrupted.
Low noise margin, 𝑁𝑀𝐿 = 𝑉𝐼𝐿 − 𝑉𝑂𝐿

High noise margin, 𝑁𝑀𝐻 = 𝑉𝑂𝐻 − 𝑉𝐼𝐻

90. Show how to find VOH, VOL, VIL and VIH for a cmos inverter from the
transfer curve.
91. Create a schematic of a chain of inverters which produces input to output
delay of approx 100ps @tt/1v/25c. Simulate and check how much delay you are
getting.
Schematics

Number of inverters = 16; Delay for per stage inverter = 5.794ps

Simulated waveform

Measured delay
Delay_in_r_out_r, 𝑇𝑃𝐻𝐻 = 88. 126𝑝𝑠
Delay_in_f_out_f, 𝑇𝑃𝐿𝐿 = 97. 281𝑝𝑠
𝑇𝑃 = 92. 704𝑝𝑠
92. Use the above block delay block 5 times and simulate the following circuits
and observe the outputs, this will require 4 separate schematics ( you can apply a
pulse/PWL input)
93. Draw the block diagram ( show the i/ps, outputs of stage 1 and programming
for 2nd stage) for decoding 9 address input with 2 stage decoding.
Three 3:8 decoders on the first stage and 512 3-input NAND and inverter on the
second stage.

Y0 = in1’ in2’ in3’ in4’ in5’ in6’ in7’ in8’ in9’

Y1 = in1’ in2’ in3’ in4’ in5’ in6’ in7’ in8’ in9

Y2 = in1’ in2’ in3’ in4’ in5’ in6’ in7’ in8 in9’

Y3 = in1’ in2’ in3’ in4’ in5’ in6’ in7’ in8 in9

.............

Y510 = in1 in2 in3 in4 in5 in6 in7 in8 in9’

Y511 = in1 in2 in3 in4 in5 in6 in7 in8 in9
94. What is the disadvantage of using nand, nor with large no of inputs?
For a large number of input NAND and NOR, the optimum width of the
transistors is large, this increases the capacitances. Hence the delay and dynamic
power consumption is larger. So it is preferable to use 2,3 or4-input nand or nor gate.
96. Draw the schematic of INVERT( AB+ CD) and INVERT( (A+B)(C+D)) and
derive the PMOS and NMOS sizes for equal rise-fall)
A B C D Y=(AB+CD)’ Y=((A+B)(C+D))’
0 0 0 0 1 1
0 0 0 1 1 1
0 0 1 0 1 1
0 0 1 1 0(Worst case) 1(Worst case)
0 1 0 0 1 1
0 1 0 1 1(Worst case) 0(Worst case)
0 1 1 0 1 0
0 1 1 1 0 0
1 0 0 0 1 1
1 0 0 1 1 0
1 0 1 0 1 0
1 0 1 1 0 0
1 1 0 0 0 1
1 1 0 1 0 0
1 1 1 0 0 0
1 1 1 1 0 0
 a. Y = (AB+CD)’

a. Y = ((A+B)(C+D))’

97. For Q 92, what is the functionality of each circuit?

a. Odd number of inverters with NAND - pulse shifter where posedge is delayed
by 500ps.
b. Odd number of inverters with NOR - pulse shifter where negedge is delayed by
500ps.
c. Even number of inverters with NAND - Posedge triggered Monoshot.
d. Even number of inverters with NOR - Negedge triggered Monoshot.
98. Draw the ckt and Size the transistors
Invert( A(B+C)+DE)

99. Using the transistor as a capacitor load at a few points, simulate your delay
block and note down the delay value with caps and w/o caps

Delay Without capacitor With capacitor

TPHH 531.9ps 536.0ps
TPLL 522.7ps 526.1ps
TP 527.3ps 531.1ps
100. Create the simulation setup for a latch and observe the circuit o/p

101. Create a FF schematic in Master-Slave configuration with 2 latches and

simulate by applying CLK and data input
102. Measure the hold, setup and clock to Q time for the FF
HOLD_CLK_TO_CLK-B 3.4833ps
SETUP_D_TO_X 22.238ps
SETUP_D_TO_Y 13.0902ps
SETUP 22.238ps
103.Draw the o/ps at Q1 and Q2 ( no simulation)

104. Measure the leakage in the following ckt under two different input
conditions shown ( @FF/1.1/125c)

I(vvdd) I(vvss)

1. -394.7nA 394.8nA

2. -1.288nA 1.290nA

1. The intermediate nodes will be at GND, so Vsb =

0. Hence there will be no reduction in leakage.
2. The intermediate nodes Vx and Vx get settled to
VTHln(1+n), so the Vsb will be positive, this
increases the Vt (by eqn1) and Vds(DIBL factor),
Vgs reduces. Ultimately N2,N3,N4 reduces the
leakage.

(1) 𝑉𝑇 = 𝑉𝑇0 + γ( (| − 2θ𝐹 + 𝑉𝑆𝐵|) − | − 2θ𝐹|)

𝑉𝑔𝑠−𝑉𝑡+η𝑉𝑑𝑠−𝑘𝑉𝑠𝑏 −𝑉𝑑𝑠
𝑛𝑣𝑇 𝑣𝑇
(2) 𝐼𝑠𝑢𝑏 = 𝐼𝑜𝑓𝑓𝑒 [1 − 𝑒 ]

In conclusion, stacking more number of OFF transistors lowers the leakage.

105. Does CLK-to-Q depend on either setup/hold? Explain with logic/diagram.
The Clk-to-Q delay is time required for the Q1 to pass to Q2 at clock transition.
It is primarily dependent on the internal delay (Pass-transistor and an inverter) and
clock transition. The setup delay depends on Data and before the clock transition and
the hold delay depends on Data and after the clock transition.

As setup and hold time occurs at different portions of the clock, the
CLK_TO_Q delay doesn’t depend on the setup or hold time.

From the above figure, increasing and decreasing setup-hold time doesn’t affect
the CLK_TO_Q delay.
106. Without simulation, for the diagram below draw the o/ps Q1 and Q2 if
Tclk-q=Ts=Th=Tdelay of the delay block =1ns . What is the max operating
frequency of the design(or minimum clock cycle time). Draw the timing diagrams
for all inputs and outputs. Write the generalised formula for clock period.

Timing diagram

Minimum clock cycle time, 𝑇𝑐𝑦𝑐𝑙𝑒 = 𝑡𝑐𝑙𝑘−>𝑞 + 𝑡𝑑 + 𝑡𝑠𝑒𝑡𝑢𝑝2 = 1𝑛 + 1𝑛 + 1𝑛 = 3𝑛

Generalized formula for clock period, 𝑇𝑐𝑦𝑐𝑙𝑒 = 𝑡𝑐𝑙𝑘−>𝑞(𝑛) + 𝑡𝑑(𝑛) + 𝑡𝑠𝑒𝑡𝑢𝑝(𝑛+1)

107. Draw the o/ps of master and slave of a D-FF for the following i/ps ( no
simulation)
108. For the circuit below draw the timing diagram and
a. Find TD1 to meet the hold time requirement of the 2nd flop
b. Find the min cycle time of the clock.

Timing diagram

a. TD1 = 1n for satisfying hold time requirement of the 2nd flipflop.

b. Minimum cycle time of clock,
𝑇𝑐𝑦𝑐𝑙𝑒 = 𝑡𝑐𝑙𝑘−>𝑞 + 𝑡𝑑 + 𝑡𝑠𝑒𝑡𝑢𝑝2 = 1𝑛 + 1𝑛 + 2𝑛 = 4𝑛
109. for Q106, if we have the 1ns delay block between CLKs of 2 FFs instead of
the data paths, draw the FFs signal waveforms. Does the system meet the hold
time requirement? If we need to fix any hold issue in this design, what will you
do?

The system doesn’t meet the hold time requirement. To fix this issue we can introduce
1n delay block
110. With the FF that you have designed, calculate the
a. cycle time of 2 FF shift register without any combi delay in between
𝑇𝑐𝑦𝑐𝑙𝑒 = 𝑡𝑐𝑙𝑘−>𝑞1 + 𝑡𝑠𝑒𝑡𝑢𝑝2 = 1𝑛 + 1𝑛 = 2𝑛

b. cycle time of 2 FF shift register with combi delay of 1 ns between the FFs (
for diagram -refer to Q106)
𝑇𝑐𝑦𝑐𝑙𝑒 = 𝑡𝑐𝑙𝑘−>𝑞1 + 𝑡𝐷+ 𝑡𝑠𝑒𝑡𝑢𝑝2 = 1𝑛 + 1𝑛 + 1𝑛 = 3𝑛

111. Draw the timing diagram at I/p and o/p of each flop

Timing diagram

a. To meet the hold time requirement

Td1 = THOLD2 - TCLK-Q1 = 2n - 1n = 1n
Td2 = THOLD3 - TCLK-Q2 = 3n - 2n = 1n
b. 𝑇𝑐𝑦𝑐𝑙𝑒 = 𝑡𝑐𝑙𝑘−>𝑞2 + 𝑡𝐷2 + 𝑡𝑠𝑒𝑡𝑢𝑝3 = 2𝑛 + 1𝑛 + 3𝑛 = 6𝑛
108) Explain how do you decide a) PD/PG ratio b) PG/PU ratio in a SRAM
bitcell.
a. PD/PG ratio
Considering the read operation i.e., WL = 1 and bl, blb holds or discharges
depending on q and qbar. Representing it in the form of the
resistor.

𝑉𝐷𝐷𝑅𝑃𝐷𝑁
By Resistor-divider rule, 𝑉𝑋 = 𝑅𝑃𝐺 + 𝑅𝑃𝐷𝑁
will always

be non-zero. If VX is high, it can make q and qbar

lose data(destructive read). So we need to keep VX as
low as possible. To keep VX low, RPDN should be low,
𝑊𝑃𝐷
therefore WPD > WPG. 𝑊𝑃𝐺
= 2 − 2. 5

PD/PG ratio is determined by the read

operation of bitcell.
b. PG/PU ratio
During write operation
Orginally qbar = VDD which is held by the
pmos transistor, now it needs to change to 0 (passing via A2). So 0 should be
stronger than VDD held by pmos. And writing ‘1’ to the bit-cell is not
effective(due to Vt drop), writing ‘0’ is effective. Hence the WPG > WPUN.
𝑊𝑃𝐺
𝑊𝑃𝑈𝑁
= 1. 5 - 2

The access transistor(1.5x2) carries 3 times the more current compared to the
Pull-up pmos transistor.
PG/PU ratio is determined by the write operation of bitcell.
109) Draw the diagram of bitcell, precharge transistor, mux and write driver
and explain

a) Sequence of events in READ operation

1. Precharge is turned OFF.
2. Word-line is fired, turning ON the bit-cell 1 and 2.
3. Required cpg signal is fired with respect to word-line, selecting
one of the bit-line bit-line bar.
4. Write driver is OFF by keeping the wen high.
5. The content in the bit-cell (q and qbar) is passed to selected bl
and bl_b.
6. It is read in Data and Data_b via the pass gate.
Bitcell -> Bitline -> Data
b) Sequence of events WRITE operation
1. Precharge is turned OFF.
2. Word-line is fired, turning ON the bit-cell 1 and 2.
3. Required cpg signal is fired with respect to word-line, selecting
one of the bit-line bit-line bar.
4. Write driver is turned ON by keeping the wen low.
5. The data to be written (Din) is passed to the Data and Data_b via
Write driver.
6. The Data and Data_b are passed to bit-line and bit-line bar via
Mux.
 7. Finally, the bl and bl_b writes into q and qbar of the bitcell by
flipping the initial contents to the written data.
Din -> Data-> Bitline -> Bitcell
110) Explain what you mean by storing '1' and '0' in the SRAM cell.

● Storing ‘0’ means, the nmos in Pull-down is ON and pulls-down the Q/Qbar to
Vss.
● Storing ‘1’ means, the pmos in Pull-up in ON and pulls-up the Q/Qbar to Vdd.
111) Identify the bitline discharge path during a) READ b) WRITE

a. READ discharging path of bitline is via the Pull-down network of bit-cell.

b. WRITE discharging path of bitline is via the Pull-down network of write driver.
112) How does the bitline store charge?
After precharging the bit-line and bit-line bar to Vdd, to store ‘0’, the bitline
discharges to Vss via the nmos pull-down transistor. For the bitline to store ‘1’, the
Pull-up pmos transistor cannot pull to Vdd because the size of pmos is small but it
holds the Vdd from the precharge phase.

113) Draw/Plot the Write and READ timing diagram

a) CLK, WL , WEN pulse, data , write driver o/ps, bitlines, Q/Q_ for Write
b) CLK, WL, Q/Q_, bitlines, sense amp input, sense amp o/p , final Q for READ

114) Why do we need a SA? Explain with waveform.

After there is a sufficient differential
voltage between data and data_bar, the sense
amplifier is turned ON and the differential
voltage is amplified, producing a clear digital
output. We need a sense amplifier to convert
the non-digital read data to digital data.
Without a sense amplifier, the data and data_b
might be too weak to reliably determine the
data. This could lead to errors in reading the
stored information, potentially resulting in incorrect data retrieval.
115) What will happen if multiple wordlines are fired at the same time in one
column? Explain 2 issues.
If multiple word lines are fired at the same
time, then
1. The bitlines and bitline bars are
determined by the PDN transistor
(because the pull-down nmos
transistor is much stronger than the
pmos pull-up), which leads to
incorrect reads.
2. There is a short-circuit path from
vdd to vss, it can disturb the content
of the bit-cell.
116) What will happen if we do not pre-charge the bitlines between successive
READ operation?
Considering the bitcell-1 has Q
and Qbar as 0 and 1, bitcell-2 has Q and
Qbar as 1 and 0. For the first read
operation, after precharging bl is
discharging to vss and bl_b is holding
vdd. For the second read (with no
precharge between the wl), the bl
cannot charge to vdd because the pmos
in PU is weak and there is no precharge.
117. For SRAM_16x8, tabulate the access, setup, hold time and cycle time.

ACCESS TIME

Access time SS/0.9/m40 SS/0.9/125 TT/1.0/25 FF/1.1/m40 FF/1.1/125

CLK_to_Q1 1.3767ns 1.2159ns 692.04ps 380.06ps 446.69ps

CLK_to_Q2 1.3648ns 1.2083ns 691.91ps 380.14ps 445.33ps

CLK_to_WL 241.18ps 195.49ps 132.06ps 60.530ps 62.435ps

WL_to_SE 1.0346ns 946.31ps 530.06ps 304.43ps 363.57ps

SE_to_Q1 100.99ps 74.185ps 29.946ps 15.125ps 20.692ps

SE_to_Q2 89.076ps 66.597ps 29.819ps 15.204ps 19.329ps

ADDRESS SETUP TIME

RA SETUP 24.073ps 37.793ps -0.8110ps 13.337ps 25.286ps

CA_SETUP -6.4570ps 13.861ps -15.993ps 4.7443ps 15.372ps

Clock path 135.46ps 101.19ps 77.267ps 28.681ps 26.377ps

Setup 24.073ps 37.793ps -0.8110ps 13.337ps 25.286ps

ADDRESS HOLD TIME

Clock path 148.52ps 112.18ps 81.928ps 31.059ps 29.818ps

Data path 22.379ps 20.606ps 7.8083ps 2.8486ps 7.4694ps

Hold 126.14ps 91.573ps 74.120ps 28.211ps 22.349ps

DATA SETUP TIME

Data path 84.694ps 75.554ps 38.490ps 20.368ps 26.984ps

Clock path 135.46ps 101.19ps 77.267ps 28.681ps 26.377ps

Setup -56.020ps -30.026ps -41.02ps -9.4342ps -0.6585ps

DATA HOLD TIME

Clock path 148.51ps 112.17ps 81.928ps 31.071ps 29.818ps

Data path 22.379ps 20.606ps 7.8083ps 2.8486ps 7.4694ps

Hold 126.05ps 91.491ps 74.319ps 28.244ps 22.385ps

 WEN SETUP TIME
Data path_1 83.927ps 68.623ps 40.925ps 25.245ps 25.887ps

SETUP_1 -51.536ps -32.574ps -36.352ps -3.4476ps -0.4877ps

Data path_2 86.403ps 70.934ps 42.362ps 26.065ps 26.731ps

SETUP_2 -49.060ps -30.23ps -34.915ps -2.6280ps 0.3563ps

Clock path 135.46ps 101.19ps 77.267ps 28.681ps 26.377ps

Setup -49.060ps -30.263ps -34.915ps -2.6280ps 0.3563ps

WEN HOLD TIME

Clock path 148.37ps 112.13ps 81.844ps 31.041ps 29.805ps

Data path 35.602ps 27.153ps 19.727ps 14.041ps 12.113ps

Hold 112.77ps 84.985ps 36.342ps 17.000ps 17.692ps

CYCLE TIME

Cycle_time_1 2.2934ns 2.0510ns 1.1133ns 648.58ps 780.23ps

(setup+gtp_high)

Cycle_time_2 2.2700ns 2.0208ns 1.1192ns 640.59ps 763.67ps

(wl_to_blb)

Cycle_time_3 2.2814ns 2.0266ns 1.1213ns 641.43ps 764.99ps

(wl_to_datab)

Cycle_time_4 2.2813ns 2.0270ns 1.1213ns 641.92ps 766.72ps

(wl_to_SDb)

Cycle_time 2.2934ns 2.0510ns 1.1213ns 648.58ps 780.23ps

118. For SRAM_16x8, tabulate the power measurement.

 DYNAMIC + STATIC POWER

SS/0.9/m40 SS/0.9/125 TT/1.0/25 FF/1.1/m40 FF/1.1/125

write_vdd -38.525uA -48.996uA -59.520uA -224.62uA -907.94uA

write_vss 38.510uA 48.980uA 59.502uA 224.60uA 907.93uA

read_vdd -37.201uA -47.422uA -58.065uA -223.49uA -905.39uA

read_vss 37.225uA 47.446uA 58.094uA 223.52uA 905.43uA

disable_vdd -2.0840uA -9.4559uA -12.044uA -158.45uA -815.842uA

disable_vss 1.9783uA 9.3499uA 11.918uA 158.30uA 815.690uA

clk_vdd -33.955uA -43.881uA -53.616uA -218.73uA -908.22uA

clk_vss 34.006uA 43.926uA 53.667uA 218.79uA 908.28uA

addr_vdd -767.65nA -8.2576uA -10.830uA -164.20uA -849.53uA

addr_vss 803.82nA 8.2958uA 10.874uA 164.25uA 849.58uA

STATIC POWER

static_vdd

static _vss

TRUE DYNAMIC POWER

write_vdd

write_vss

read_vdd

read_vss

disable_vdd

disable_vss

clk_vdd

clk_vss

addr_vdd

addr_vss
115)Explain with timing diagram and timing window how will you measure

a) READ power
It is the power consumed by the memory during retrieving data. For measuring read
power, the measurement window is taken such that it includes all the inputs switching
(wen to high) upto the nodes (bl/blb, data/datab) precharging.
b) Write power
It is the power consumed by the memory during storing data. For measuring write
power, the measurement window is taken such that it includes all the inputs switching
(wen to low) up to the nodes (bl/blb, data/datab, SD/SDb) precharging.
c) deselect power
Deselecting or disabling the memory involves deactivating the chip enable (CEN).
This state leads to a decrease in power consumption. For measuring deselect power,
the measurement window includes CEN switches to logic high, while rest signals are
toggling (clk to logic high, rest signals can be toggled to high or low).
d) clock pin power
The clock pin power is the power consumed by the memory when the clock pin
toggles. The measurement window includes only the clock pin toggling and rest pins
are not toggling (cen = 0).
e) add pin power
For measuring the address pin power, the measurement window includes single bit
address toggling and rest pins are static. The total address pin power is calculated as
‘n’ number of address pin times the single address bit power.
f) static power in memory
Static power consumption in memory refers to power dissipation when there are no
switching activities.
116) With diagrams explain what will happen if both the write driver and pre-
charge are on ?
If both the write driver and precharge are on, then
1. There will be a short circuit path
from vdd (of precharge) to vss
(of write driver).
2. The precharge circuit tries to
pull up the bl/blb to vdd, while
the write driver pull-down
network tries to pull down the
bl/blb to vss.
3. Since the PDN of the write
driver is stronger and there is a
fight between precharge and
write driver, bl/blb takes longer
time to discharge.
117) Explain with a diagram what will happen if both WL and pre-charge are
ON?
If both WL and precharge are ON, then
1. There will be a short circuit path
from vdd (of precharge) to vss (of
PD transistor of bitcell).
2. The precharge circuit tries to pull up
the bl/blb to vdd, while the bitcell
pull-down transistor tries to pull
down the bl/blb to vss.
3. Since there is a fight between
precharge and PD transistor of
bitcell, the bitlines take longer time to discharge.
118) what is characterization? How do you determine the PVT conditions for
char?
Characterization : The process of gathering and validating the PPA data for working
PVTs.
The PVT conditions of characterization is determined by
i) Process

For performance we will consider SS, FF and TT, where SF, FS are within the process
boundary.
ii) Voltage: The voltage regulator in SOC fluctuates voltage, there is no guarantee that
voltage is 1v (nominal voltage). So given the tolerance of ±10% , there can be three
voltage variations: 0.9V, 1V, 1.1V.
iii) Temperature: We will take into account low temperature(-40c), nominal
temperature(25c) and high temperature(125c).
The process characterization PVTs are SS/0.9/-40c, SS/0.9/125c, TT/1.0/25c,
FF/1.1/-40c, FF/1.1/125c. The FF/1.1/125c is mostly included due ro high leakage.
119) Calculate the number of rows and cols for 256 words x 128 bits memory for
mux2, mux4 and mux8 options and draw the relative size of the memory
instances. Calculate how many address bits we need for each instance.
𝑊𝑜𝑟𝑑𝑠
𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑟𝑜𝑤𝑠 = 𝑚𝑢𝑥

𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑐𝑜𝑙𝑢𝑚𝑛𝑠 = 𝑚𝑢𝑥 × 𝑏𝑖𝑡𝑠

256 words x mux2 x 128 Rows 128 7 row address 8

bits address
Columns 256 1 column address

256 words x mux4 x 128 Rows 64 6 row address

bits
Columns 512 2 column address

256 words x mux8 x 128 Rows 32 5 row address

bits
Columns 1024 3 column address
 PVT Read Margin(targ=0.1) Write Margin(targ=1.2)

Meas Margin Wl_high Wl to Q Ratio x/y Margin

diff (V) (V) (x) (y)

SS/0.81/m40 0.6919 0.5919 3.5582ns 640.75ps 5.55316 4.3516

SS/0.81/125 0.6240 0.5240 2.6549ns 442.73ps 5.9967 4.7967

FF/0.81/m40 0.5449 0.4449 1.0155ns 192.43ns 5.27761 4.07761

FF/0.81/125 0.4645 0.3645 1.0471ns 201.49ps 5.1967 3.9967

FF/1.21/m40 0.7802 0.6802 582.32ps 99.695ps 5.8410 4.6410

FF/1.21/125 0.6898 0.5898 717.22ps 123.90ps 5.7885 4.5885

PVT Timing margin SE pulse width margin(targ=2.5)

Clk to wl Clk to Ratio SE SE to Q Ratio Margin

(x) precharge (x/y) hightime (y) (x/y)
(y) (x)

SS/0.81/m40 341.56ps 297.60ps 1.1477 2.0428ns 150.26ps 13.5957 11.0957

SS/0.81/125 243.26ps 215.77ps 1.1273 1.4242ns 97.388ps 14.6242 12.1242

FF/0.81/m40 113.15ps 99.487ps 1.1373 534.12ps 25.759ps 20.7349 18.2349

FF/0.81/125 95.577ps 83.638ps 1.1427 549.47ps 25.489ps 21.5573 19.0573

FF/1.21/m40 50.351ps 45.334ps 1.1106 305.05ps 13.810ps 22.0893 19.5893

FF/1.21/125 53.023ps 47.691ps 1.1110 376.35ps 18.226ps 20.6489 18.1489

PVT PULSE WIDTH

GTP SE

SS/0.81/m40 3.5785ns 2.0428ns

SS/0.81/125 2.6517ns 1.4242ns

FF/0.81/m40 1.0158ns 534.12ps

FF/0.81/125 1.0379ns 549.47ps

FF/1.21/m40 573.08ps 305.05ps

FF/1.21/125 701.02ps 376.35ps

 PVT DC margin

SS/0.81/m40 400mV

SS/0.81/125 350mV

SF/0.81/m40 50mV

SF/0.81/125 100mV

FS/0.81/m40 850mV

FS/0.81/125 820mV

FF/0.81/m40 420mV

FF/0.81/125 450mV

FF/1.21/m40 650mV

FF/1.21/125 710mV
120) Explain the working of clock gen with ckt and timing diagram.

When cen=0, P1 and N3 are

ON, the clk=0 and clk_d=1, the N1 is
OFF and N2 is ON. As soon as the
clk is transitioned to 1, the PDN is
on, pulling the ‘x’ to vss, the gtp goes
to high. Even after the PDN turns off,
the latch holds the data. After the 1ns
delay of gtp, the rst goes low, turning
on the PUN, pulling the ‘x’ to vdd.
During this time gtp goes low. This
state remains until the clk transitions
to ‘1’. The clock period of clk and
gtp are the same. The gtp high period
is equal to 1ns delay block.
When cen=1, only P3 is turned on, pulling ‘x’ to vdd and gtp to ‘0’.
121) Explain the working of SA with ckt, timing diagram and how it amplifies a
small diff voltage.

Working
When SE = 0, the decoupling transistor D1 and D2 are on, the
tristate output Data and Datab passed to SD and SDb. The N3
transistor is OFF, so ‘x’ is not at vss. There will not be a current path
so it doesn’t work as an inverter.
As soon as SE = 1, the N3 will be ON, ‘x’ is connected to vss.
The decoupling transistor gets turned OFF. By the property of latch,
there will not be any metastable state. So ‘supply’ voltage SD/SDb is
going to remain ‘HIGH’ and voltage less than supply is going to
remain ‘LOW’.
Considering SD = 1.0v, SDb = 0.9v, the N1 and N2
will be on. Initially pulling down the SD and SDb to vss.
Assuming Vt = 0.3V for both N1 and N2
(𝑉𝑔𝑠 − 𝑉𝑡)1 = 0. 9𝑉 − 0. 3𝑉 = 0. 6𝑉 is the overdrive voltage of N1
(𝑉𝑔𝑠 − 𝑉𝑡)2 = 1. 0𝑉 − 0. 3𝑉 = 0. 7𝑉 is the overdrive voltage of N2
Since the overdrive voltage of N2 is greater than
N1, the N2 pulls SDb is GND quicker. When the
SDb voltage crosses the threshold of P1, the N1
turns OFF and P1 turns ON, pulling the SD to vdd.
This is true only for ideal conditions.During
manufacturing, there will be variation in electrical
and physical properties of the same transistor, no
transistor will be identical (Local Variation).

122) What is margining? What are the PVT corners for margining for 1v
nominal voltage?
Margining refers to the difference between the actual operating condition of the
design and the minimum amount required for correct operation. The goal of margining
is to ensure the circuit is robust under every possible PVTs.
PVT corners for margining are
1. The manufactured silicon can be any process in the process boundary
box, so we need to test for SS, SF, FS, FF.
2. The voltage is generated via the voltage regulator, it can be subject to
variation. So to guarantee the design is working at 0.9v and 1.1v, we
need to check for ±10% i.e., 0.81v and 1.21v.
3. The temperature is industry standard, there will not be any variation.
Margining can be done for -40c (low temperature) and 125c (high
temperature).

Process Voltage Temp

SS
-40c
SF 0.81
FS
125c
FF
SS
-40c
1.21
SF
FS
125c
FF
123) Define a) READ margin b) Write margin c) WL – Precharge margin d)
SE PW vs Q delay margin with equation ( along with some target) and diagram
wherever necessary.
a. READ margin : Read margin measures the difference between the differential
voltage of tristate outputs when SE=1 and the required differential voltage for
proper operation of sense amp. The read margin should be sufficient so that
there will be proper read operation.
𝑅𝑒𝑎𝑑 𝑚𝑎𝑟𝑔𝑖𝑛 = 𝑚𝑒𝑎𝑠𝑢𝑟𝑒 𝐷𝑎𝑡𝑎, 𝐷𝑎𝑡𝑎𝑏 𝑑𝑖𝑓𝑓 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 − 𝑡𝑎𝑟𝑔𝑒𝑡 𝑑𝑖𝑓𝑓 𝑣𝑜𝑙𝑡𝑎𝑔𝑒(100 𝑚𝑣)
b. WRITE margin : Write margin measures the difference between the ratio of
wl pulse width to wl - q and the target value. For successful write operation, the
ratio should be greater than 1.2 to 1.3, which means the pulse width of wl
should be 20 - 30% more compared to wl to q.
𝑥 = 𝑊𝐿 𝑝𝑢𝑙𝑠𝑒 𝑤𝑖𝑑𝑡ℎ
𝑦 = 𝑊𝐿 ℎ𝑖𝑔ℎ 𝑡𝑜 𝑏𝑖𝑡𝑐𝑒𝑙𝑙 𝑞/𝑞𝑏 ℎ𝑖𝑔ℎ
𝑥
𝑊𝑟𝑖𝑡𝑒 𝑚𝑎𝑟𝑔𝑖𝑛 = 𝑦
− 𝑡𝑎𝑟𝑔𝑒𝑡(1. 2 − 1. 3)
c. WL-precharge margin : The wl-precharge timing margin refers to the ratio of
clk to wl and clk to precharge. For proper synchronisation and operation, this
ratio should be approximately equal to
1.
𝑥 = 𝑐𝑙𝑘 𝑡𝑜 𝑤𝑙
𝑦 = 𝑐𝑙𝑘 𝑡𝑜 𝑝𝑟𝑒𝑐ℎ𝑎𝑟𝑔𝑒
𝑥
𝑇𝑖𝑚𝑖𝑛𝑔 𝑚𝑎𝑟𝑔𝑖𝑛 = 𝑦
≃1
d. SE pulse-width vs Q delay : The SE
delay margin measures the difference
between ratio of SE pulse width to
SE-Q time and the target value. For
successful read operation, delay
margin ensures the Q transitions
before the SE goes low.
𝑥 = 𝑆𝐸 𝑝𝑢𝑙𝑠𝑒 𝑤𝑖𝑑𝑡ℎ
𝑦 = 𝑆𝐸 ℎ𝑖𝑔ℎ 𝑡𝑜 𝑄 ℎ𝑖𝑔ℎ
𝑥
𝐷𝑒𝑙𝑎𝑦 𝑚𝑎𝑟𝑔𝑖𝑛 = 𝑦
− 𝑡𝑎𝑟𝑔𝑒𝑡
(2. 1 𝑡𝑜 3)
124) What is the worst Process (out of SS,TT,FF,FS and SF) for Write and why?

Initially ‘Q’ is at ‘logic high’, which is held by P1.

Now to flip the Q (high -> low), the A1 should be stronger
than the P1. But for the SF process, A1 is slow (higher Vt,
lesser current), P1 is fast (lesser Vt, higher current). So the
‘logic high’ is much stronger. To flip in the SF process Q
we need stronger ‘logic low’ (very close to 0) otherwise the
write fails. Since the write fails at very low voltage for SF
compared to other processes, the SF corner is the worst corner.
125) what is
a) random offset ( what is a typical value? )
Random offset is due to the mismatch of Vt for transistors (local variation).
The typical random offset value for 1σ is 10-15mv.
To measure the random offset,
1. Apply the differential voltage between the tristate outputs.
2. Run the monte carlo for a specific number of times(say for 5000 times).
3. find how many simulations are failing.
4. If 1 failure out of 5000 sample = 2.7σ spread, then vary the differential voltage
to get the specific number of failures. Larger differential voltage, lesser number
of failures.
5. Calculate differential voltage for 1σ.
6. Random offset = n x 1σ (n is the number of sigmas needed)
Lets say, I’m applying a 20mv differential voltage between D and Db, running
monte carlo for 5000 times. Out of 5000, 10 are failing. So, I am increasing the
differential voltage. At 27mv, one out of 5000 samples is failing.
27𝑚𝑣 = 2. 7σ
1σ = 10𝑚𝑣.
If the number of sigmas required is 6, then, 𝑅𝑎𝑛𝑑𝑜𝑚 𝑜𝑓𝑓𝑠𝑒𝑡 = 6 × 10𝑚𝑣 = 60𝑚𝑣
.
b) systematic offset ( what is a typical value? )
During layout, there will be mismatch in SD, SDb capacitors, which can
contribute to the differential voltage. The typical value for systematic offset is around
10-20mv.
Measuring the systematic offset
With the extracted netlist (contains RC information), we vary the differential
voltage. Apply the less differential voltage. Then go on increasing, the differential
voltage at which the sense amplifier works is taken as systematic offset.
c) bitcell current degradation factor
Due to local variation in bitcells, the current flow in the bitcells during read
varies. The differential voltage between bitlines is large for lesser read current.
To measure the bitcell current degradation factor
1. Measure the access transistor current when the bl/blb is discharging.
2. Run the monte carlo simulation.
3. Find the mean, minimum, maximum currents.
4. Calculate the factor which determines how much percentage the minimum
current deviates from the mean. The variation is typically around ±20-30%
and how do you determine each of them (write few points for each)
126) What is the total SA offset formula?
𝑅𝑎𝑛𝑑𝑜𝑚 𝑜𝑓𝑓𝑠𝑒𝑡 + 𝑆𝑦𝑠𝑡𝑒𝑚𝑎𝑡𝑖𝑐 𝑜𝑓𝑓𝑠𝑒𝑡
𝑆𝐴 𝑜𝑓𝑓𝑠𝑒𝑡 = 𝑏𝑖𝑐𝑒𝑙𝑙 𝑟𝑒𝑎𝑑 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑑𝑒𝑔𝑟𝑎𝑑𝑎𝑡𝑖𝑜𝑛 𝑓𝑎𝑐𝑡𝑜𝑟

If Random offset = 60mv, Systematic offset = 20mv, bicell read current degradation
factor = 0.8, then SA offset = 100mv
127) What are the margins that determine WL pulse width in a)READ b)
WRITE
a. READ
During read, the margins that determines the WL pulse width are
1. Sufficient differential voltage of bitlines which can be 10-15% greater
than SA offset.
2. SE pulse width which is sufficient to produce Q signal.
 b. WRITE
During write, the margins that determines the WL pulse width is
𝑊𝐿 𝑝𝑢𝑙𝑠𝑒𝑤𝑖𝑑𝑡ℎ
1. Write margin = 𝑊𝐿 𝑡𝑜 𝑞
− 𝑡𝑎𝑟𝑔𝑒𝑡(1. 2 𝑡𝑜 1. 3). The WL pulse

width should be 20-30% larger than WL to Q.

128) What are the factors that determine the maximum number of rows in a
column?
The factors that determine the maximum number of rows in a column are
1. Bitline loading - As the number of rows increases, the bitline loading
increases. This affects the write by reducing the write margin and read by
reducing SA margin. Reducing the overall access and cycle time. This factor
limits the number of rows in a column.
2. The read current-to-bitline leakage ratio determines the number of rows by
𝐼𝑅𝐸𝐴𝐷
𝐼𝐵𝐼𝑇𝐿𝐼𝑁𝐸 𝐿𝐸𝐴𝐾×(𝑛−1)𝑏𝑖𝑡𝑐𝑒𝑙𝑙𝑠
> 10
129) Simulate the bitline READ and leakage current for the bitcell and calculate
the Read-to-bitline leakage ratio for the design at FF/1.1/125c.
For 256 bitcells
Iread -36.9316uA
Ibitline_leakage 85.3831nA
Read-to-bitline leakage ratio -1.69623
130) Draw the top level architecture diagram of 2k words x 8 bits x mux8 using
butterfly and 2 banks architecture . How many address bits do we need for this
memory?
Memory configuration is 2k words x 8 bits x mux8
𝑊𝑜𝑟𝑑𝑠 2×1024
𝑅𝑜𝑤𝑠 = 𝑚𝑢𝑥 𝑠𝑖𝑧𝑒
= 8
= 256 𝑟𝑜𝑤𝑠 [8 𝑏𝑖𝑡𝑠 𝑟𝑜𝑤 𝑎𝑑𝑑𝑟𝑒𝑠𝑠]

𝐶𝑜𝑙𝑢𝑚𝑛𝑠 = 𝑚𝑢𝑥 × 𝑏𝑖𝑡𝑠 = 8 × 8 = 64 𝑐𝑜𝑙𝑢𝑚𝑛𝑠 [3 𝑏𝑖𝑡𝑠 𝑐𝑜𝑙𝑢𝑚𝑛 𝑎𝑑𝑑𝑟𝑒𝑠𝑠]

Butterfly architecture
2 Bank architecture

Butterfly + Bank architecture

Address bit required

1. For row decoding is 7-bits
2. For column decoding is 3-bits
3. For bank decoding is 1-bit
4. Total address bits required is 11
ACCESS TIME [Minload = 0.01f, Maxload = 10f; Minslew = 0.01n, Maxslew = 0.5n]

SS/0.9/m40 SS/0.9/125 TT/1.0/25 FF/1.1/m40 FF/1.1/125

Minload-Minslew 665.85ps 665.85ps 334.29ps 358.22ps 358.22ps

Minload-Maxslew 761.98ps 761.98ps 379.60ps 294.79ps 294.79ps

Maxload-Minslew 901.08ps 901.08ps 487.06ps 473.76ps 473.76ps

Maxload-Maxslew 1.1351ns 931.69ps 535.07ps 396.26ps 454.80ps

SETUP TIME

cslew - aslew SS/0.9/m40 SS/0.9/125 TT/1.0/25 FF/1.1/m40 FF/1.1/125

0.01n - 0.01n 47.412ps 47.412ps 25.162ps 17.109ps 17.109ps

0.5n - 0.01n 30.103ps 30.103ps -14.754ps -12.877ps -12.877ps

0.01n - 0.5n -13.552ps -13.766ps -22.963ps 55.709ps 105.32ps

0.5n - 0.5n -145.80ps -34.514ps -62.892ps 23.294ps 81.587ps

HOLD TIME

cslew - aslew SS/0.9/m40 SS/0.9/125 TT/1.0/25 FF/1.1/m40 FF/1.1/125

0.01n - 0.01n 91.091ps 91.091ps 45.974ps 25.521ps 25.521ps

0.5n - 0.01n 67.568ps 67.568ps 61.976ps 42.905ps 42.905ps

0.01n - 0.5n 285.70ps 145.59ps 93.834ps -16.148ps -57.485ps

0.5n - 0.5n 257.41ps 121.34ps 109.94ps 6.0001ps -51.334ps

 TRUE DYNAMIC - READ TRUE DYNAMIC - WRITE

SS/0.9/m40 TT/1.0/25 FF/1.1/125 SS/0.9/m40 TT/1.0/25 FF/1.1/125

lvt 46.288uA 49.375uA - 46.209uA 74.372uA -

rvt 34.760uA 44.454uA 51.656uA 33.952uA 42.731uA 51.559uA

hvt 74.193uA 86.643uA 113.50uA 74.573uA 86.983uA 622.02uA

ACCESS TIME CYCLE TIME

lvt 511.20ps 267.96ps - 2.3125ns 1.1412ns -

rvt 1.3767ns 692.04ps 446.69ps 2.2934ns 1.1213ns 780.23ps

hvt 1.4451ns 730.37ps 425.37ps 2.7000ns 1.3721ns 905.42ps

STATIC CURRENT

lvt 42.018uA 509.21uA -

rvt 47.151nA 10.202uA 864.38uA

hvt 253.79nA 6.5637uA 520.59uA

Vdd =Vddc=1v Vdd=0.9v;Vddc= 1v Vdd = 1.1v;Vddc = 1v

Access time 347.82ps 431.66ps 294.73ps

Cycle time 1.1965ns 1.4792ns 1.0190ns

Write power (vdd) 45.579uA 40.156uA 66.929uA

Read power (vdd) 44.057uA 38.836uA 50.082uA

Write power 183.52nA 246.07nA 170.65nA

(vddc)

Read power(vddc) 62.163nA 36.995nA 109.14nA

Leakage current 9.4113uA 5.5159uA 15.921uA

(vdd)

Leakage current 743.50nA 743.45nA 743.57nA

(vddc)
131) Liberty file related question
Which pin/bus section in .lib will have
a) Access time : Q bus under the timing type rising_edge
b) Cycle time : Clk pin under the timing type min_period
132) What are the timing numbers associated with address, data and control
section?
The timing numbers associated with address, data bus and control pins are rise
constraint and fall constraint for setup and hold time, for different clock and input
slew.
133) Where do you find pin power information in .lib?
The pin power information is in the all pins internal_power sections. It includes
the rise power and fall power for vddce and vddpe with different input slew.
134) What is the pipeline option? Draw the timing diagram of the read cycle with
pipeline ON.
The pipelining refers to the specific way of organizing and processing data. In
memory, the pipeline is used to improve the access time. If the pipeline option is on, it
means there will be extra latches at the output.
Timing diagram

135) What is the redundancy option?

Redundancy means the inclusion of extra bit cells (redundant rows or columns)
to replace the defective bit cells. If the redundancy option is on, which means the
design includes this redundancy feature.
136) What does the bit_write_mask option do? Show write partitioning with a
diagram.
Write partitioning is a scheme which allows control of the write enable
independently for each IO or a block of IOs read/write.
If the bit_write_mask option is ON, which means only the local wens are used,
not the global wen.

137)What is the full form for BIST? Why do we need BIST?

The BIST stands for Built-In-Self-Test. It is a testing technique used in SOC.
We use BIST to test all the input signals, memory arrays and detect the manufacturing
defects and other faults.
138) Why do you use the power gating option? Draw a block diagram of PG
implementation and tabulate the current simulation results with power gating
option in active, retention and power down mode.
Power gating is a technique where we can
specifically turn off the peripheral power(retention
mode) or both core and peripheral power (power
down mode) when they are not in use. This helps to
save power during sleep mode.
 Modes I(vvdd) I(vvddc)

Active mode Write power 51.608uA 894.58nA

Read power 50.428uA 768.61nA

Retention mode 1.4251uA 759.53nA

Power down mode 144.20nA 326.35nA

Leakage power 76.448nA 3.0528nA

139) What is the back bias option?

Back bias is the voltage applied at the body terminal of the transistor. This is
one of the power saving techniques which is primarily applied to reduce the leakage
power during power-down mode.
140) What will happen to memory performance if we change the EMA option?
With the required SE offset, we can adjust the firing of SE using EMA. If the
SE offset is less, then we can adjust EMA, so that SE fires earlier, which reduces the
CLK to Q (access time), reducing the cycle time and improving performance.
With the EMA, we can adjust the word-line pulse width, improving the write
margin.
141) What does a memory compiler do? What are the 3 different components of
a memory compiler?
Memory compiler is a program/software that can automate the generation of
different memory instances of different sizes, does curve fitting and generates the
behavioural verilog model.
Components of memory compiler
1. Design DB - contains leaf level schematics and
layout information
2. Simulation DB -contains PPA information.
3. Softwares - for tilting and curve fitting.
142) what are the standard views of a memory instance?
● Netlist(representing info. about schematics)
● GDS2 (representing info. about layout)
● Liberty (containing timing and power information)
● LEF (footprint of design with pin position information)
● Verilog model (representing the behaviour of the design)
143) How is curve fitting used to generate timing/ power for a memory instance
in a compiler?
For example, in case of access time, increasing
row increases access time linearly, similarly
increasing column also increases access time. If I’m
having a memory instance of column ‘n’ and row
between m1 and m2, then from the graph the memory
instance has access time between ‘x’ns and ‘z’ns. In
the same way, for every timing and power parameters
we find the dependencies, then generate a graph for
every parameter. Then we can locate the timing and
power for all the memory instances.
144) what does tiling do in a compiler?
Tiling is software that builds memory of different sizes. It takes the basic leaf
cells as input along with other parameters that are necessary to build the memory. For
example, if i need to build an array, i need to provide the basic leaf cell - bitcell and
number of rows and columns information. Tiling gives the netlist, GDS2, LEF files.
SNM
NMH NML
HOLD 425 mv 220 mv
READ
 TT_1.0_25c

iread_a 847.32nA

iread_b 847.32nA

DC write margin 412mV

Hold NMH 425mV

Hold NML 253mV

Read NMH 50mV

Read NML 44mV

145) Explain with reason which pass transistor is required for a) read b) write
The pass transistor which is required for read operation is pmos. Because
during sen triggering, the one of tristate output is expected to be near vdd with
sufficient differential voltage. The pass transistor which passes a strong vdd is pmos.
The pass transistor which is required for write operation is nmos. We know
that writing ‘0’ to bitcell is effective, so there should not be any drop when the write
driver output is passed to bl/blb. The pass transistor which passes a strong ‘0’ is nmos.
146) Draw 2:1 muxing with SA and Write drivers when we have separate read
and write paths.

133) What are the corner instances for each mux for the following compiler
Words range 128 to 2k
Bits range 2 to 128
Mux option 2,4,8
Mux_2
Min rows 128
= 64 Min columns 2×2=4
2

Max rows 2𝑘
= 1𝑘 Max columns 128 × 2 = 256
2

1 Short and thin 64 rows x 4 columns

2 Tall and thin 1k rows x 4 columns
3 Short and wide 64 rows x 256 columns
4 Tall and wide 1k rows x 256 columns
Mux_4
Min rows 128
= 32 Min columns 2×4=8
4

Max rows 2𝑘
= 512 Max columns 128 × 4 = 512
4

1 Short and thin 32 rows x 8 columns

2 Tall and thin 512 rows x 8 columns
3 Short and wide 32 rows x 512 columns
4 Tall and wide 512 rows x 512 columns
Mux_8
Min rows 128
= 16 Min columns 2 × 8 = 16
8

Max rows 2𝑘
= 256 Max columns 128 × 8 = 1024
8

1 Short and thin 16 rows x 16 columns

2 Tall and thin 256 rows x 16 columns
3 Short and wide 16 rows x 1k columns
4 Tall and wide 256 rows x 1k columns
134) Explain in detail the process of writing in the bitcell.

Assuming the data stored in the bitcell are q=1, qbar=0. If I’m applying bl=0
and blb=1 (via the tristate points), then
1. The N2 turns off and P2 turns ON, charging the node qbar to vdd.
2. The P1 turns off and N1 turns ON, discharging the node q to vss.
Thus flipping the q and qbar from 1,0 to 0,1.
135) Explain the sizing of DP bitcell.
During read, if both access transistors for A
and B are turned ON and the pull-down transistor
N1 is on, then the node ‘x’ will have high noise. To
keep this low, we are decreasing the resistance of
PDT. So the width of PDT is twice that of original
𝑊𝑃𝐷𝑇
width. [ 𝑊𝑃𝑇
= 3 − 4].

During write, any one of the access

transistors is ON, it is similar to single port SRAM.
Writing ‘0’ in a bitcell is effective, so we need to
have a strong ‘0’ compared to ‘vdd’ held by the pmos. So the width of the access
𝑊
transistor > width of pull-up transistor.[ 𝑊 𝑃𝑇 = 1. 5 − 2]
𝑃𝑈𝑇
136) Explain what happens in following contention case a) R-R b) R-W c) W-W
a) R-R
In this scenario both port A and B are in read operation. The access transistors
for port A and B are ON, based on the path, the bl/blb from the port A and B
discharger/charges. Since this doesn’t involve the modification of data. There will not
be any collision.
b) R-W
Let's consider port A is in read operation and port B is in write operation. In
this case, port A may read the original data or the new data written by port B. We
cannot guarantee correct read operation in this case. One way of making sure that
there is no collision is we can prioritise writing and delay the read.
c) W-W
If both the port A and B are writing in the same bitcell, this results in collision
if the data of the both ports are different.