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Laxmi Nandikolmath
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34 views5 pages

Synopsis

Synopsis

Uploaded by

Laxmi Nandikolmath
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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BASAVESHWAR ENGINEERING COLLEGE,BAGALKOT-587103

Department of Electronics and Communication Engineering

MAJOR PROJECT SYNOPSIS

PROJECT TITLE: “DESIGN AND VERIFICATION OF AHB PROTOCOL USING


SYSTEM VERILOG”

Submitted By:

1. Laxmi Nandikolmath 2BA21EC040

2. Rakshita Gajendragad 2BA21EC075

3.Suchitra Hullur 2BA21EC107

4. Umm-ul-khair Sindgi 2BA21EC117

Project Guide Co-ordinators HOD

Dr. Sharanappa P. H. Dr. S. R. Bharamagoudar Dr. Jayashree D. Mallapur

Prof.M.C.Aralimarad
ABSTRACT

AMBA AHB is a high-performance on-chip bus architecture widely used in system-on-chip


(SoC) designs. It provides a standardized interface for intercommunication between various
modules like processors, memories, and I/O peripherals. AHB supports burst transfers,
pipelining, and various transfer modes, making it suitable for high-speed data transfers. The
design and verification of AHB protocols are typically carried out using System Verilog and
simulation tools like QuestaSim. By adhering to AMBA AHB standards, SoC designers can
ensure efficient and reliable communication within their integrated systems.

INTRODUCTION

The Advanced High-performance Bus (AHB) protocol is part of the AMBA (Advanced
Microcontroller Bus Architecture) specification developed by ARM, widely used in modern
System on Chip (SoC) designs. AMBA protocols, including AHB, ASB, and APB, standardize
on-chip communication between integrated components like CPUs, memories, and peripherals.
AHB, designed for high-performance applications, supports features such as burst transfers,
pipelining, and high data throughput, making it ideal for interconnecting high-bandwidth
elements like ARM processors, memory, and DMA controllers.

In SoC designs, where multiple IP cores with different functionality need to be integrated,
efficient communication is essential to ensure system performance and reliability. AHB, with its
shared bus architecture and arbitration mechanism, allows only one master to access the bus at a
time, ensuring organized data transfer. Its pipelined architecture improves efficiency by
overlapping address and data phases.

As SoC complexity increases, verification becomes critical. Over 70% of the development cycle
is often consumed by verification tasks to ensure synchronization and proper communication
between IP cores. System Verilog, a widely used hardware verification language, offers a high
level of abstraction for verifying such protocols. This work focuses on designing and verifying
an AHB protocol with a single master-slave configuration using System Verilog, adhering
to AMBA standards.
LITERATURE SURVEY:

In [1] The design and verification of an AMBA AHB bus architecture using System Verilog. The
AHB implementation features a single master and single slave configuration, supporting various
transfer modes, including burst transfers, pipelining, and sequential/non-sequential transfers. A
comprehensive verification environment is developed in System Verilog, incorporating
testbenches, assertions, and coverage analysis. The design is functionally verified using
QuestaSim, demonstrating its ability to operate at high clock frequencies. Future work will
explore the integration of UVM for enhanced verification capabilities

Key Terms: AHB, AMBA, Master, Slave, SoC, Boundary Address, DUT, System Verilog.

In [2] The design and verification of an AMBA AHB bus system using SystemVerilog. The
AHB implementation features a single master and four slaves, supporting single-beat
transactions. A verification environment is developed using SystemVerilog to randomize address
and control signals and verify read/write transactions. The design is functionally verified, and
future work includes expanding the design to support multi-master configurations and burst
transfers. Additionally, the paper plans to replace the custom verification environment with a
UVM-based VIP for improved reusability and efficiency.

Key Terms: AHB, AMBA-AHB, QuestaSim, ARM.

In [3] This paper proposes an AMBA AHB bus verification environment using SystemVerilog
assertions. It leverages SVA to check protocol compliance for a single master and four slaves
with single-beat transactions. The QuestaSim simulator is used for simulation.

Future work includes expanding the design for multi-master configurations, burst transfers, and
wrapping address boundaries. Additionally, a UVM-based VIP is proposed for improved
reusability and efficiency.The referenced literature includes the AMBA specification, papers on
AHB Lite and AHB verification using SVA, and a review of SoC bus protocols.

Key Terms: AMBA ,AHB , SV, SVA .


OBJECTIVES:

The primary objectives of using blockchain technology to detect and prevent counterfeit products
are as follows:

Objectives for AHB protocol using System Verilog:

1. Comprehensive verification: Ensure AHB design correctness using testbenches,


assertions, and coverage analysis.

2. Reusability: Promote reuse of verification components for future AHB designs.

3. Efficiency: Improve verification efficiency through constrained random test generation


and efficient simulation techniques.

4. Formal verification: Detect errors early using mathematical proofs of correctness.

5. Integration: Seamlessly integrate System Verilog into the AHB design and verification
process.

EXPECTED OUTCOMES:

The expected outcomes of designing and verifying the AHB protocol using SystemVerilog
include ensuring the AHB design's correctness and functionality, identifying and correcting
errors, improving design quality, increasing confidence, ensuring compliance with AMBA
standards, achieving an efficient verification process, and enhancing debugging capabilities.
Ultimately, the goal is to create a high-quality, functional, and reliable AHB implementation that
meets the required specifications and standards.
REFERENCES:

[1] Gurha, Prince, and R. R. Khandelwal, “System Verilog Assertion Based Verification of
AMBA-AHB” , International Conference on Micro-Electronics and Telecommunication
Engineering (ICMETE), 2016.
[2] K. Singh, A. Shrivastava and G. S. Tomar, “Design and Implementation of High
Performance AHB Reconfigurable Arbiter for Onchip Bus Architecture”, International
Conference on Communication Systems and Network Technologies, 2011.
[3] Pockrandt, M. Herber, P and Glesner, S, Model checking a SystemC/TLM design of the
AMBA AHB Protocol Embedded Systems for Real-Time Multimedia (ESTIMedia),
2011 9th IEEE Symposium on 13-14 Oct.2011.

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