290 Unit 10

10.2 VHDL Models for Multiplexers

with two data inna
multiplexer (MUX)
igure 10-5 shows a 2-to-1
A'-I10 + A-I1.The correspondine Vuts and
and oone
nput. The MUX output is
F
DL statemenconta
=

F<= (notA and 10) or (A and 1);

represent the MUX by conditional signal ase
a
Alternatively,
ment, as
we can

shown in 10-5. This

Figure
is 10 when A
statement executes whenaBnmen
=
0, and else it is I1
assignment
never A, 0, state
A,
changes. The MUX output
either be bits or bit-vectors. oT
the conditiona
statement, 10, I1, and F can

FIGURE 10-5
2-to-1 Multiplexer 1-
- conditional signal assignment statement
F= 10 when A = '0' else 11;

The general form of a conditional signal assignment statement is

signal_name<= expression1 when condition1
else expression2 when condition2
lelse expressionN]:
This concurrent statement is executed whenever a change occurs in a sigpals
one of the expressions or conditions. It conditionl is true, signal_name is s
Used in
to the value of cxpressionl, or clse if condition2 is true, signal_name is set eauequal
the value of expression2, cte. The line in square brackets is optional. Figure 106
shows how two cascaded MUXes can be represented by a conditional signal assign.
ment statement. The output MUX selects A when E = "T;or else it selectstheou

put of the first MUX, which is B when D =l', or else it is C.

FIGURE 10-6
Cascaded 2-to-1

D
F <= A when E = '1'
MUXes else B when D = '1'
else C

Figure 10-7 shows a 4-to-1 MUX with four data inputs and two control inpulsA
and B The control inputs select which one of the data inputs is transmited tou

output. The logic equation for the 4-to-1 MUX is

F A'B1, A'BI, ABI, + ABI

Thus one way to modiel the MUX is with the VHDL statement

F<= (notA and not B and 10) or (not A and B and 1) or

(A and not B and 12) or (A and B and 13);
 291
Introduction to VHDL

sel <= A&B;

AGURE
1O2
selected signal
1Mtplerer MUX
with sel select assignment statement
F< 10 when "00",
11 when "01,
2 when "10",
13 when "11;
A B

Anather way to model the 4-to-1 MUX is to use a conditional assignment statement

"00"
F<= 10 when A&B
=

"01
else I1 when A&B
=

else 12 when
A&B =
"10
else 13;
bits A andB
The expression A&B means A concatenated with B, that is, the two the
to form a 2-bit vector. This bit vector is tested, and appro
are merged together
=1' and A&B "10"
B 0',
=

nriate MUX input is selected. For example, if A

could use a more complex
and 12 is selected. Instead of concatenating A and B, we
condition:

F< 10 when A ="0 and B ='0'

else I1 when A ="0 and B 1
else 12 when A ="1' and B '"0*
else 13;
state
the MUX is to use a selected signal assignment
A third way to model statement, soo
shown in Figure 10-7. A&B cannot be used in this type of
ment, as that is
set Sel equal to A&B.
The value of Sel then selects the MUX input
we first
assigned to F
The general form of a selected signal assignment statement is

with expression_s select

choice1,
signal_s= expression1 [after delay-time] when choice2,
when
expression2 [after delay-timej

[expression_n lafter delay-timej when others

of the
statement executes
whenever a signal changes in any
This concurrent
choicel, signal_s is set
is evaluated. If it equals
expressions First. expression_s etc. If
choice2. signal_s is set equal to expression2;
cqual to expressionl: if equals
it
are given, the last
line should be
all possible choices for the value of expression_s is not
is required. When it is present, if expression_s
omitted: otherwise. the last line The
choices. signal_s is set equal to expression_n.
enumerated
cqual to any of the or after A if
the "after delay-
delay-time,
Sugnal_s is updated after the specified
tume is omitted.
292 Unit 10

10.3 vHDL Modules

we declare all
must
lo write a complete
VHDL module, the
declaration, and internal Inp
then specify the into. op nput and
Signals using an entity
declaraton. As an example, Cor

dule. "ider
architecture
module using an

gives the name "twO_gates

to the module
Figure
The port
entity declaration
to the module. A, B,and
d D are 104
specifies the inputs and outputs
bit. and E is an output signal
of type
architecture
archite
bit. The
because
tecture is
it is an int named "g
decata
input signa2nals
signal Cis declared within the
describe the gates are placed betu
internal signa
concurrent statements that
een gnal. The
the keya
begin and end.

FIGURE 10-8 entity two_gates is

VHDL Module with port (A,B,D: in bit; E: out bit):
Two Gates end twogates;
architecture gates of two_gates is
signal C: bit;
begin
C= A and B; -- concurrent
E = C or D; -- statements

end gatesS

When we describe a system in vHDL, we must specify an n

architecture at the top level, and also specify an entity and architectura and
the component modules that are part of the system (see Figure 10-9)
declaration includes a list of interface signals that can be used to comneEach e
modules or to the outside world. We will use entity declarations of the form O

entity entity-name is
port(interface-signal-declaration);]
end lentityl lentity-namel:
The items enclosed in square brackets are optional. The interface-signal-declarat
normally has the following form:
list-of-interface-signals: mode type [: = initial-value
list-of-interface-signals: mode type [ = initial-value|};

FIGURE 10-9
VHDL Program Entity
Architecture
Structure
y
Architecture
Enity Entity
Architecture Architecture
Module
Modute 2 Module N
 293
introdur tion to VHOL

The curlybrackets| indicate 7ero or more

of the enclned clause Inp
signals re of mode in, outpul signals are of repetition
are. mode out. and hr directumal see

Figure9-12) are of mode inout

Figat So
we have oniy used re descrihed n
type bit and bit vector, other types are
ction
ptional initial-value is used to initial1ze the nals on the assod
10.4. The optie
Seeeeotherwise.the delauit initial value is used for the specified type For examn
a t c d

declaration
the port
ple.

nort(A, B: in integer
; =
2;C, D: out bit):
that A and Ba
A and B are input signals of type integer that are initially set to L. ana
that
indicates

D are tput
outpl signals of type bit that are initialized by default to

C nd Is one or more architecture declarations

of
the
ASSociated with each entity

form
architecture-name of entity-name is
architecture
declarations

begin
architecture body
end [architecturel larchitecture-namel
that are used
declarations section,
signals and components describe the
we can declare
n the statements that
The architecture body contains
within the architecture.
of the module. module (refer
operation for a full adder
the entity and architecture
Next, we will write
specifies the inputs and
of a full adder). The entity
4.7 for a description declaration spec
to Section as shown in Figure 10-10. The port
the adder module, and Sum are
outputs of of bit, and that Cout
type
Y and Cin are input signals
ifies that X,
of type bit.
output signals
entity FullAdder is
- Inputs
in bit;
RGURE 10-10
port (X,Y,Cin: Outputs
Full Cout, Sum: out bit);
- -

snty
Declaration

Adder Suni
ira Full Adder end FullAdder;

Module
declaration:
architecture

full adder is specified

by an
of the
The operation

FullAdder is
architecture Equations of
Concurrent assignment statements
begin Y xor Cin
after 10 ns;
10 ns;
Sum = X xor or (Y and Cin) after
or(X and Cin)
Cout= (X and Y)
end Equations;
name
but the entity
(Equations)
is arbitrary, declaration.

architecture
name
associated entity
the used in the
in this example,
must
match the
name

FullAdder)
 294 Unit 10
The VHDL assignt statements for Sum and
out represent the lo0

for the full adder. Several other architectural

descriptions such as ns such
as aa taC eque
truth table
uscd instcad. In the Cout
have been
interconnection of gates could
because VHDL docs not sn cquatio
heses are around (X and Y)
required cify an order
precedence for the logic operatos.

Four-Bit Full Adder

FullAdder module defined abos oove :
Next, wewill show how to use the
nent in a system which consists of four
full adderS connected to form
a
Co
form 4-bit
We first declare the 4-bit adder as an bin
ry adder (see Figure 10-11). the sum output are four hity
Figure 10-12). Because the inputs and bits wide, w
declare them as bit_vectors which are dimensioned 3 downto 0. (W.
We could W
used a range 1 to 4 instead.)) haTave

FIGURE 10-11
4-Bit Binary Adder

C
Full Full Full Full
Adder Adder Adder
Adder

B A2 B, A B Ag B,

Next, we specify the FullAdder as a component within the architectua

ure of
Adder4 (Figure 10-12). The component specification is very similar to the entit
declaration for the full adder, and the input and output port signals correspond to
those declared for the full adder. Following the component statement, we declarea
3-bit internal carry signal C.
In the body of the architecture, we create several instances of the FullAdder
component. (In CAD jargon, we instantiate four copies of the FullAdder.,) Each
copy of FullAdder has a name (such as FA0) and a port map. The signal namesfol
lowing the port map correspond one-to-one with the signals in the component port.
Thus, A(0), B(0), and Ci correspond to the inputs X, Y, and Cin, respectively. C()
and S(0) correspond to the Cout and Sum outputs. Note that the order of the sig
nals in the port map must be the same as the order of the signals in the port of the
component declaration.
In preparation for simulation, we can place the entity and architecture for the
FullAdder and for Adder4 together in one file and compile. Alternatively, we coud
compile the FullAdder separately and place the resulting code in a library which 5
linked in when we compile Adder4.
All of the simulation examples in this text use the ModelSim simulatoriro
Model Tech. Most other VHDL simulators use similar command files and cat
 Introduction to VHDL
295

entityAdder4 is
METO12 in bit_vector(3 downto
ort (A, B: bit_vector(3 0); Ci: in bit,
Srutra
onon
o
S: out downto 0): Co: out
bit);
- Inputs

Outputs
e n dA d d e r 4 :

t Adder chitectureStruct of Adder4 is

component FullAdder
- Inputs
p o r t (X,Y, Cin: in bit;
Cout, Sum: out bit;-- Outputs
e n d c o m p o n e n t ;

signal C:- bit_vector(3 downto 1):

jnstantiate four copies of the FullAdder
begin
FAO: FullAdder port map (A(0), B(0), Ci, C(1), S(0):
FA1: FullAdder port map (A(1),
B(1), C(1), C(2), S(1)):
FA2: FullAdder port map (A(2), B(2), C(2), C(3), S(2:
AG), BB), CB), Co, S(3);
FA3: FullAdder port map
end Structure;

com-
in a similar format. We will use the following simulator
duce
produ
output
Adder4:
test
mands to

B Co C Ci S -put these signals on the output list

add list A set the A inputs to 1111
forceA 1111
set the B inputs to 0001
force B 0001

force Ci 1
-set Ci to1
run the simulation for 50 ns
run 50 ns

force Ci 0
force A 0101
force B 1110

run 50 ns enough
this is m o r e than
simulation for S0 ns because results
to run the simulation
We have
chosen
all of the full adders.The
to propagate through
time for the carry
command list are
for the above
CO
C
delta 0000
ns 0 000
0000 0000 0000
0 0 0001 0 000 1111
1111 001
0001 1101
+0 1111 011
10 0001 1001
1111 111
20 0001 0 0001
1111 111
30 0 0001
1 0001
0 1111 111
40 1110 0101
0101 1 110 0111
50 1110
100 0
0101 1 0011
60 1110 0
0101 100
70 -0 1
1110
0 0101
80