21EC733

Model Question Paper-1/2 with effect from 2021(CBCS Scheme)

USN

7th Semester B.E. Degree Examination

Subject Title DSP Algorithms and Architecture
TIME: 03 Hours Max. Marks: 100

Note: 01. 02. Answer any FIVE full questions, choosing at least ONE question from each
MODULE.
03.
04.

*Bloom’s COs
Module -1 Taxonomy Marks
Level
Q.01 a For the FIR filter y(n)= 0.5 x(n)+ 0.5 x(n-1). Determine i) System L3 1 8
Function ii) Magnitude and phase function iii) Step response iv)
Group Delay.
b Explain IIR filter design L3 1 6
c L1 1 6
Describe the major feature of programmable DSP
OR
Q.02 a Obtain the transfer function of the IIR filter whose difference L3 1 8
equation is given y[n] = 0.9 y(n-1) +0.1 x(n)
b Define decimation and interpolation process. Explain them using L3 1 6
block diagrams and equations with a neat diagram
c Explain FIR filter with its design L2 1 6
Module-2
Q. 03 a Investigate the basic features that should be provided in the DSP L3 2 8
architecture to be used to implement the following Nth order FIR
y[n]= Σ h(i) x(n-i), where n =0,1,2
b Explain Barun and Baugh Wooley multiplier for unsigned and signed L2 2 9
numbers. Show the multiplication operation for 4x4 unsigned
multiplication.
c To find the sum of 64, 16 bit numbers. How many bits should the L3 2 3
accumulator have so that the sum can be computed without the occurrence
of overflow error or loss of accuracy?
OR
Q.04 a Explain the implementation of 8 Tap FIR filter y[n]= Σ h(i) x(n-i) using L2 2 9
parallelism and pipelining .
b Draw the schematic diagram of the saturation logic and explain the L2 2 8
same.
c A barrel shifter is to be designed with 16 inputs for left shifts from 0 to 15 L3 2 3
bits. How many control lines are required to implement the shifter.
Module-3
Q. 05 a L2 2 7
Describe the multiplier/adder unit of TMS320c54xx processor with
a neat block diagram.
b Describe any Four data addressing modes of TMS320c54xx L2 2 8
processor.
c L2 2 5
Compare architectural features of TMS320C25 and DSP6000 fixed

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 21EC733
point digital signal processors.
OR
Q. 06 a Describe the accumulator unit of TMS320c54xx processor with a L2 2 7
neat block diagram.
b Describe Host Port interface and explain its signals. L2 2 8
c Explain the functional building block of TMS320c54xx processor L2 2 5
Module-4
Q. 07 a Determine the number of stages and number of butterflies in each L3 3 7
stage and the total number of butterflies needed for the entire
computation of 512 point FFT
b Explain with the help of a block diagram and mathematical L2 3 8
equations the implementation of a second order IIR filter. No
program code is required.
c Briefly explain IIR filters. L2 3 5
OR
Q. 08 a Explain, how scaling prevents overflow conditions in the butterfly L2 3 7
computation.
b Write the assembly language program for TMS320C54XX L3 3 8
processor to implement an FIR filter.
c Write a subroutine program to find the spectrum of the L3 3 5
transformed data using TMS320C54XX DSP.
Module-5
Q. 09 a Explain with a neat diagram, the synchronous serial interface L2 4 10
between the C54xx and a CODEC device.
b Explain the memory interface block diagram for the TMS 320 L2 4 5
C54xx processor.
c Design a data memory system with address range 000800h – L3 4 5
000fffh for a c5416 processor using 2kx8 SRAM memory chips.
OR
Q. 10 a Explain the operation of pulse position modulation (PPM) to L2 4 10
encode two biomedical signals.
b Explain an interface between an A/D converter and the L2 4 5
TMS320C54XX processor in the programmed I/O mode.
c With the help of block diagram explain JPEG algorithm. L2 4 5
*Bloom’s Taxonomy Level: Indicate as L1, L2, L3, L4, etc. It is also desirable to indicate the COs and POs to be
attained by every bit of questions.

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 21EC733
Model Question Paper-1/2 with effect from 2021(CBCS Scheme)
USN

7th Semester B.E. Degree Examination

Subject Title DSP Algorithms and Architecture
TIME: 03 Hours Max. Marks: 100

Note: 01. 02. Answer any FIVE full questions, choosing at least ONE question from each
MODULE.
03.
04.

*Bloom’s COs
Module -1 Taxonomy Marks
Level
Q.01 a For the FIR filter y(n)= 0.5 x(n)+ 0.5 x(n-1). Determine i) System L3 1 8
Function ii) Magnitude and phase function iii) Step response iv)
Group Delay.
b Explain the sampling process. L1 1 6
c L1 1 6
Describe the major feature of programmable DSP
OR
Q.02 a Explain the operation used in DSP to increase the sampling rate. L3 1 8
The sequence x(n)=[0,2,4,6,8] is interpolated using interpolation
sequence bk =[1/2,1,1/2] and the interpolation factor is 2.find the
interpolated sequence y(m).
b Define decimation and interpolation process. Explain them using L2 1 6
block diagrams and equations with a neat diagram
c Explain FIR filter with its design L2 1 6
Module-2
Q. 03 a Investigate the basic features that should be provided in the DSP L3 2 8
architecture to be used to implement the following Nth order FIR
y[n]= Σ h(i) x(n-i), where n =0,1,2
b Explain briefly about MAC unit. L2 2 9
c To find the sum of 64, 16 bit numbers. How many bits should the L3 2 3
accumulator have so that the sum can be computed without the occurrence
of overflow error or loss of accuracy?
OR
Q.04 a Explain the implementation of 8 Tap FIR filter y[n]= Σ h(i) x(n-i) using L3 2 9
parallelism and pipelining .
b Explain circular and bit reversed addressing mode. L2 2 8
c A DSP has a circular buffer with the start and end addresses are 0200h and L3 2 3
020F h respectively. What would be the new value of the address pointer
of the buffer, if in the course of address computation if get updated to i)
0212 h ii) 01FCh
Module-3
Q. 05 a L2 2 7
Describe the functioning of barrel shifter in TMS320C54XX
processor.
b Explain PMST register. L2 2 8
c L2 2 5
Compare architectural features of TMS320C25 and DSP6000 fixed

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 21EC733
point digital signal processors.
OR
Q. 06 a Explain the operation of serial I/O ports and hardware timer of L2 2 7
TMS320C54XX on chip peripherals.
b Describe Host Port interface and explain its signals. L2 2 8
c Explain the different types of interrupts in TMS320C54xx processors. L2 2 5
Module-4
Q. 07 a What is an interpolation filter? Explain the implementation of L2 3 7
digital interpolation using FIR filter and poly phase sub filter.
b Write the assembly language program for TMS320C54XX processor L3 3 8
to implement an FIR filter.
c Describe the importance of Q notation in DSP algorithm L2 3 5
implementation with examples.
OR
Q. 08 a How many add/subtract and multiply operations are needed to L3 3 7
compute the butterfly structure?
b Derive the equation to implement a butterfly structure in DIT FFT L2 3 8
algorithm.
c Write a subroutine program to find the spectrum of the L3 3 5
transformed data using TMS320C54xx DSP.
Module-5
Q. 09 a Explain with a neat diagram, the memory interface for read-read- L2 4 10
write sequence of operation. Explain the purpose of each signal
involved.
b How interrupts are handled by C54xx DSP processor. L2 4 5
c Design a data memory system with address range 000800h – L2 4 5
000fffh for a c5416 processor using 2kx8 SRAM memory chips.
OR
Q. 10 a Explain with neat diagram, the synchronous serial interface L2 4 10
between the C54xx and a CODEC device.
b Explain an interface between an A/D converter and the L2 4 5
TMS320C54XX processor in the programmed I/O mode.
c With the help of block diagram explain JPEG algorithm. L2 4 5
*Bloom’s Taxonomy Level: Indicate as L1, L2, L3, L4, etc. It is also desirable to indicate the COs and POs to be
attained by every bit of questions.

With the help of the implementation structure, explain the FFT algorithm for DIT-FFT computation on
TMS320C54XX processors. Use ¼ as a scale factor for all butterflies.

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