Scribd
Upload
26 views3 pages

CSE 204 - Final - Spring2024 Question 1

Uploaded by

2311959
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
26 views3 pages

CSE 204 - Final - Spring2024 Question 1

Uploaded by

2311959
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 3

FINAL EXAMINATION

Spring 2024
Department of Computer Science & Engineering
Independent University, Bangladesh (IUB)

CEN 204: Introduction to Computer Hardware and Digital Logic


CSC 204: Introduction to Computer Hardware and Digital Logic
CSE 204: Digital Logic Design

Total Marks: 80
Time Allowed: 120 Minutes

 Answer all four (4) questions


 Figure in bracket [] next to each question indicates marks for that
question
 Answer question serially, i.e., Question 1, 2, 3, and 4

This question paper has three (3) pages (including cover page).
1. You are given the following function:
F(A, B, C) = m(1, 2, 6, 7).

(a) Implement F using a combination of AND and OR gates. [5]

(b) Implement F using a 3:8 decoder and a single multi-input OR gate.

[5]

(c) Implement the function using an 8:1 multiplexer. [5]

(d) Implement the function using a 4:1 multiplexer. [5]

[CO2] (20 marks)

2. The Majority Detector

Design a 3-input digital circuit that identifies which polarity (1 or 0) is the


majority among the input bits.

[CO2] (20 marks)

Page 2 of 3
3. A new latch

Suppose we design a JL latch from a JK latch, by adding an inverter to the K


input. That is, L = ~K.

(a) Derive the Characteristic Table for a JL latch (without a clock input).

[5]

(b) Use K-Maps to derive the simplified Characteristic Equation for this latch.
[5]

(c) Derive the Excitation Table for a JL latch from its Characteristic Table.
[5]

(d) Use K-Maps to derive the simplified Excitation Equations for this latch.

[5]

[CO2] (20 marks)

4. You are given the following (Moore Machine) State Transition Diagram.

0
1 00 01 0

1 1

1
10 11
0
0

State notation format:


STATE/
Design and implement a sequential circuit to meet the above specifications. Use
D flip-flops.

[CO2] (20 marks)

THE END

Page 3 of 3

You might also like