DIGITAL CIRCUITS AND SIGNAL

SIMULATION LAB OBSERVATION

II B.TECH I SEMESTER
(R23)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CHADALAWADA RAMANAMMA ENGINEERING COLLEGE
(AUTONOMOUS)
(Accredited by NAAC, Approved by AICTE, New Delhi & Affiliated to JNTU
Anantapur)
Renigunta Road, Tirupati – 517506, A.P., India.
 DIGITAL CIRCUITS AND SIGNAL SIMULATION

LAB OBSERVATION

(23A04303T)

Name:

H.T. No.:

Year & Semester:_

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CHADALAWADA RAMANAMMA ENGINEERING COLLEGE
(AUTONOMOUS)
(Accredited by NAAC, Approved by AICTE, New Delhi & Affiliated to JNTU
Anantapur)
Renigunta Road, Tirupati – 517506, A.P., India.
B.Tech –II-I Sem (23A04303T) DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB

LIST OF EXPERIMENTS

Branch: ECE Regulation: R23

1. Write a program to generate various Signals and Sequences: Periodic and Aperiodic, Unit Impulse, Unit Step,
Square, Saw tooth, Triangular, Sinusoidal, Ramp, Sinc function.

2. Perform operations on Signals and Sequences: Addition, Multiplication, Scaling, Shifting, Folding,
Computation of Energy and Average Power.

3. Write a program to find the trigonometric & exponential Fourier series coefficients of a rectangular periodic
signal. Reconstruct the signal by combining the Fourier series coefficients with appropriate weightages- Plot
the discrete spectrum of the signal.

4. Write a program to find Fourier transform of a given signal. Plot its amplitude and phase spectrum.

5. Write a program to convolve two discrete time sequences. Plot all the sequences.

6. Write a program to find auto correlation and cross correlation of given sequences.

7. Write a program to verify Linearity and Time Invariance properties of a given Continuous System.

8. Write a program to generate discrete time sequence by sampling a continuous time signal. Show that with
sampling rates less than Nyquist rate, aliasing occurs while reconstructing the signal.

9. Write a program to find magnitude and phase response of first order low pass and high

pass filter. Plot the responses in logarithmic scale.

10. Write a program to find response of a low pass filter and high pass filter, when a speech signal is passed
through these filters.

11. Write a program to generate Complex Gaussian noise and find its mean, variance, Probability Density
Function (PDF) and Power Spectral Density (PSD).

12. Generate a Random data (with bipolar) for a given data rate (say 10kbps). Plot the same for a time period of
0.2 sec.

13. To plot pole-zero diagram in S-plane/Z-plane of given signal/sequence and verify its stability.

Note: All the experiments are to be simulated using MATLAB or equivalent software.
 I. COURSE OBJECTIVES:
• Verify the truth tables of various logic circuits.
• Design sequential/combinational circuit using Hardware Description Language and verify their functionality.
• Simulate various Signals and Systems through MATLAB
• Analyze the output of a system when it is excited by different types of deterministic and random signals.

II. COURSE OUTCOMES:

After the completion of the course students will be able to

• Verify the truth tables of various logic circuits. (L2)
• Understand how to simulate different types of signals and system response. (L2)
• Design sequential and combinational logic circuits and verify their functionality. (L3, L4)
• Analyze the response of different systems when they are excited by different signals and plot power spectral
density of signals. (L4)
• Generate different random signals for the given specifications. (L5)

CO-PO/PSO Mapping
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
CO1 3 - - - - - - - - - - - 3 -
CO2 3 - - - - - - - - - - - 3 -
CO3 - 3 3 - - - - - - - - 3 -
CO4 - 3 3 - - - - - - - - - 3 -
CO5 - - - - 3 - - - - - - - 3 -
CO 3 3 3 3 3 - - - - - - - 3 -
 LABORATORY INSTRUCTIONS

1. While entering the Laboratory, the students should follow the dress code.

2. The students should bring their observation book, record, calculator, necessary stationery items
and graph sheets if any for the lab classes without which the students will not be allowed for doing
the experiment.

3. All the Equipment and components should be handled with utmost care. Any breakage or damage

will be charged.

4. If any damage or breakage is noticed, it should be reported to the concerned in charge immediately.

5. The theoretical calculations and the updated register values should be noted down in the

observation book and should be corrected by the lab in-charge on the same day of the laboratory

session.

6. Each experiment should be written in the record note book only after getting signature from the lab
in-charge in the observation notebook.

7. Record book must be submitted in the successive lab session after completion of experiment.

8. 100% attendance should be maintained for the laboratory classes.

Precautions.

1. Check the equipment before giving the supply.

2. Observations should be done carefully.
 I N D E X

S. Name of the Experiment Date Grade Signature

No.
PART A
1 To design a simple combinational circuit with
four variables and obtain minimal SOP
expression and verify the truth table using
Digital Trainer Kit.

2 To verify functional table of 3 to 8-line

Decoder /De-multiplexer

3 To verify 4 variable logic function using

8 to1 multiplexer.

4 To design full adder circuit and verify its

functional table.
5 To design a four-bit ring counter using D
Flip–Flops/JK Flip Flop and verify output.

6 To design a four-bit Johnson’s counter using

D Flip-Flops/JK Flip Flops and verify output

7 To verify the operation of 4-bit Universal

Shift Register for different Modes of
operation.

8 Draw the circuit diagram of MOD-8

ripple counter and construct a circuit
using T Flip Flops and Test it with a low
frequency clock and sketch the output
waveforms.
9 To design MOD–8 synchronous counter using
T Flip-Flop and verify the result and sketch
the output waveforms.

10 (a) Draw the circuit diagram of a single bit

comparator and test the output
(b) To construct 7 Segment Display
Circuit Using Decoder and7 Segment
LED and test it
S. Name of the Experiment Date Grade Signature
No.
PART B
1 Generation of various Signals and Sequences

2 Operations on Signals and Sequences

3 To find and reconstruct trigonometric &

exponential Fourier series coefficients of a
rectangular periodic signal. Plot its amplitude
and phase spectrum.
4 To find the Fourier transform of a given signal.
Plot its amplitude and phase spectrum.
5 To convolve two discrete time sequences. Plot
all the sequences.
6 To find autocorrelation and cross correlation of
given sequences.
7 To verify Linearity and Time Invariance
properties of a given Continuous System.

8 To generate discrete time sequence by sampling

a continuous time signal. Show that with
sampling rates less than Nyquist rate, aliasing
occurs while reconstructing the signal.

9 To find magnitude and phase response of first

order low pass and high pass filter. Plot the
responses in logarithmic scale.
10 To generate Complex Gaussian noise and find its
mean, variance, Probability Density Function
(PDF) and Power Spectral Density (PSD).
 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Introduction to Xilinx ISE Suite

Procedure:

1. Open Xilinx ISE

2. Create a new source file in a new project with suitable name.
3. Create the file in VHDL/Verilog module.
4. Select the appropriate input and output ports according to the requirements.
5. Type the program and save it.
6. Select Synthesize XST, check for syntax errors and generate report and RTL schematic.
7. In the process window, go to ‘user constraints’ and select ‘assign package pins’ and after that double click on
‘implement design’.
8. Select properties by right clicking on ‘generate programming file’. Select ‘JTAG’ clock in startup options.
9. Select boundary scan in ‘impact window’ after double clicking on ‘configure device’.
10. In ‘generate programming file’ double clicking on ‘programming file generation report. Bit file will be generated.
11. Xilinx boundary scan window will appear when the bit file is selected. Right click on Xilinx component and select
program.
12. Programming properties will appear and finally program will be succeeded.
13. Thus the program can be dumped into FPGA kit and finally output can be seen on the kit.

Simulation tool:
1.Double click the project navigator and select the option File-new project.
2.Give the project name.
3.Select the Verilog module
4.Type Verilog code.
5.Check for syntax.
6.Select the new source, choose Verilog fixture for test bench
7.Choose behavioral simulation and simulate it by Xilinx ISE simulator.
8.Verify the output.

Synthesis tool:
1.Double click the project navigator and select the option File-new project.
2.Give the project name.
3.Select the Verilog module
4.Type Verilog code.
5.Check for syntax.
6.Select - view RTL schematic, Technology schematic and device utilization summary from the synthesis-xst menu.
7. Verify the logic circuit and equivalent parameters.

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

EXP. No.1 Four variables combinational circuit and obtain minimal SOP
DATE: expression

AIM: To design a four variable combinational circuit, obtain minimal SOP expression and verify the truth table using
Digital Trainer Kit.

Hardware required:PC

Software required: Xilinx ISE Design Suite

Theory:

A combinational circuit is a type of digital logic circuit where the output depends solely on the current inputs,
without any memory or feedback from previous states. The circuit's behavior is determined by a logical function of the
inputs, which can be expressed in different forms such as Sum of Products (SOP) or Product of Sums (POS).

Four-Variable Combinational Circuit

In a four-variable combinational circuit, there are four input variables, typically denoted as A, B, C, and D. These
inputs can take binary values (0 or 1), leading to 24=162^4 = 1624=16 possible input combinations. The output of the
circuit is a logical function F(A,B,C,D), which can be represented in a truth table or by a Boolean expression.

Sum of Products (SOP) Expression

The Sum of Products (SOP) is a canonical form of Boolean expression where the function is expressed as a sum
(OR) of product terms (ANDs). Each product term in the SOP form corresponds to a minterm, which is a combination
of input variables that produces a true output (1) for the function.

Reductions of 4 Variable K Maps

The following four variable Karnaugh maps illustrate the reduction of Boolean expressions too tedious for Boolean
algebra. Reductions could be done with Boolean algebra.
However, the Karnaugh map is faster and easier, especially if there are many logic reductions to do.

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The above Boolean expression has seven product terms. They are mapped top to bottom and left to right on the K-map
above. For example, the first P-term A’B’CD is the first row, 3rd cell, corresponding to map location A=0, B=0, C=1,
D=1.
The other product terms are placed in a similar manner. Encircling the largest groups possible, two groups of four are
shown above.
The dashed horizontal group corresponds to the simplified product term AB. The vertical group corresponds to
Boolean CD. Since there are two groups, there will be two product terms in the Sum-Of-Products result
of Out=AB+CD.

Minimal SOP Expression Out = AB+CD

Verilog Code:
module sop(a,b,c,d,y);
input a,b,c,d;
output out;
assign out = (a&b)|(c&d);
endmodule

Testbench Code:

module sop_tb;

//
Inputs
reg a;
reg b;
reg c;
reg d;

//
Outputs
wire out;

// Instantiate the Unit Under Test

(UUT)
sop uut (
.a(a),
.b(b),
.c(c),
.d(d),
.out(out),
);

initial begin
// Initialize Inputs

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
a = 0; b = 0; c = 0; d = 0; #5;
a = 0; b = 0; c = 0; d = 1; #5;
a = 0; b = 0; c = 1; d = 0; #5;
a = 0; b = 0; c = 1; d = 1; #5;
a = 0; b = 1; c = 0; d = 0; #5;
a = 0; b = 1; c = 0; d = 1; #5;
a = 0; b = 1; c = 1; d = 0; #5;
a = 0; b = 1; c = 1; d = 1; #5;
a = 1; b = 0; c = 0; d = 0; #5;
a = 1; b = 0; c = 0; d = 1; #5;
a = 1; b = 0; c = 1; d = 0; #5;
a = 1; b = 0; c = 1; d = 1; #5;
a = 1; b = 1; c = 0; d = 0; #5;
a = 1; b = 1; c = 0; d = 1; #5;
a = 1; b = 1; c = 1; d = 0; #5;
a = 1; b = 1; c = 1; d = 1; #5;
$finish;
end
endmodule

RTL Schematic:

Simulation output waveform:

Result:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

EXP. No.2 To Verify Functional Table Of 3 To 8-Line Decoder /De-Multiplexer

DATE:

Aim: To verify functional table of 3 to 8-line Decoder/De-multiplexer and verify the output using Hardware Description
Language.

Hardware required:PC

Software required: Xilinx ISE Design Suite

Theory:

3 to 8-line decoder IC 74HC238 is used as a decoder/ demultiplexer. 3 to 8-line decoder demultiplexer is a

combinational circuit that can be used as both a decoder and a demultiplexer. IC 74HC238 decodes three binary
address inputs (A0, A1, A2) into eight outputs (Y0 to Y7). The device also has three Enable pins. The same
combination is used as a demultiplexer.
Pin Configuration
The below is the pin configuration for the IC74HC238 3 to 8-line decoder or demultiplexer. It is a 16 pin DIP.
Circuit
The logical circuit explains the working of the IC 74HC238.
Features of 74HC238 IC
• Demultiplexing capability
• Multiple inputs enable easy expansion
• Ideal for memory chip select decoding
• Active HIGH mutually exclusive outputs
• Multiple package option
Application of Decoder
• The Decoders were used in analog to digital conversion in analog decoders.
• Used in electronic circuits to convert instructions into CPU control signals.
• They mainly used in logical circuits, data transfer.
Applications of Demultiplexer
• Used to connect a single source to multiple destinations.
• The Demux is used in communication systems to carry multiple data signals into a single transmission line.
• Used in Arithmetic Logic Units
• Used in serial to parallel converters in data communications.

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Verilog Code:
module decoder3to8(in,out, en);
input [2:0] in;
input en;
output [7:0] out;
reg [7:0] out;

always @( in or en)
begin

if (en)
begin
out=8'd0;
case (in)
3'b000: out[0]=1'b1;
3'b001: out[1]=1'b1;
3'b010: out[2]=1'b1;
3'b011: out[3]=1'b1;
3'b100: out[4]=1'b1;
3'b101: out[5]=1'b1;
3'b110: out[6]=1'b1;
3'b111: out[7]=1'b1;
default: out=8'd0;
endcase
end
else
out=8'd0;
end
endmodule
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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

1:8 Demultiplexer:
Code:

module demux_1to8(I,SEL,Y) ;
input I;
input [2:0]SEL;
output [7:0]Y;
reg [7:0]Y;
always @ (I,SEL)
begin
case(SEL)
3'b000: Y=4'b00000001;
3'b001: Y=4'b00000010;
3'b010: Y=4'b00000100;
3'b011: Y=4'b00001000;
3'b011: Y=4'b00010000;
3'b011: Y=4'b00100000;
3'b011: Y=4'b01001000;
3'b011: Y=4'b10001000;

endcase
end
endmodule

Testbench Code for 1to8 Demux:

module demux_1to8_tb;
// Inputs
reg I;
reg [2:0] SEL;
// Outputs
wire [7:0] Y;

// Instantiate the Unit Under Test (UUT)

demux_1to8 uut (
.I(I),
.SEL(SEL),
.Y(Y) );
initial begin
// Initialize Inputs
I = 1;
SEL = 3'b000; #5;
SEL = 3'b001; #5;
SEL = 3'b010; #5;
SEL = 3'b011; #5;

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
SEL = 3'b100; #5;
SEL = 3'b101; #5;
SEL = 3'b110; #5;
SEL = 3'b111; #5;

$finish;
end
endmodule

Testbench code for 3 to 8 decoder:

module dec_tb;
// Inputs
reg [2:0] in;
// Outputs
wire [7:0] out;
// Instantiate the Unit Under Test (UUT)
dec uut
(
.in(in),
.out(out) );
initial begin
// Initialize Inputs
in = 3'b000; #5;
in = 3'b001; #5;
in = 3'b010; #5;
in = 3'b011; #5;
in = 3'b100; #5;
in = 3'b101; #5;
in = 3'b110; #5;
in = 3'b111; #5;
$finish;
end
endmodule

RTL Schematic:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Simulation output waveform:

Result:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

EXP. No.3 4 variable logic function verification using 8 to1 multiplexer

DATE:

AIM: To design a four variable logic function using 8 to 1 multiplexer and verify the output using Hardware
Description Language.
Hardware required:PC

Software required: Xilinx ISE Design Suite

Theory:
Implement the following function using 8:1 multiplexer workaround: F (A,B, C,D) = ∑m (0,1,3,5,7,10,,11,13,14,15)

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
Verilog Code:
module mux8to1(
input A, B, C, D,
output F
);
wire [7:0] mux_in;

// Minimize the function for each combination of select lines (B, C, D)

assign mux_in[0] = ~A; // minterm 0
assign mux_in[1] = ~A; // minterm 1
assign mux_in[2] = A; // minterm 2 (not used)
assign mux_in[3] = 1'b1; // minterm 3
assign mux_in[4] = 1'b0; // minterm 4 (not used)
assign mux_in[5] = 1'b1; // minterm 5
assign mux_in[6] = A; // minterm 6 (not used)
assign mux_in[7] = 1'b1; // minterm 7

// Select line
assign F = mux_in[{B,C,D}];

endmodule

Testbench Code:

module mux8to1_tb;
// Inputs
reg A;
reg B;
reg C;
reg D;

// Outputs
wire F;

// Instantiate the Unit Under Test (UUT)

mux8to1 uut (
.A(A),
.B(B),
.C(C),
.D(D),
.F(F)
);

initial begin
// Initialize Inputs
A = 0;B = 0; C = 0; D = 0; #50;
A = 0;B = 0; C = 0; D = 1; #50;

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
A = 0;B = 0; C = 1; D = 0; #50;
A = 0;B = 0; C = 1; D = 1; #50;
A = 0;B = 1; C = 0; D = 0; #50;
A = 0;B = 1; C = 0; D = 1; #50;
A = 0;B = 1; C = 1; D = 0; #50;
A = 0;B = 1; C = 1; D = 1; #50;
A = 1;B = 0; C = 0; D = 0; #50;
A = 1;B = 0; C = 0; D = 1; #50;
A = 1;B = 0; C = 1; D = 0; #50;
A = 1;B = 0; C = 1; D = 1; #50;
A = 1;B = 1; C = 0; D = 0; #50;
A = 1;B = 1; C = 0; D = 1; #50;
A = 1;B = 1; C = 1; D = 0; #50;
A = 1;B = 1; C = 1; D = 1; #50;
$finish;

end

endmodule

RTL Schematic:

Simulation output waveform:

Result:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

EXP. No.4 Design full adder circuit and verify its functional table
DATE:

AIM: To design full adder circuit and verify its functional table using Hardware Description Language.

Hardware required:PC

Software required: Xilinx ISE Design Suite

Theory:

Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This carry bit from its previous
stage is called carry-in bit. A combinational logic circuit that adds two data bits, A and B, and a carry-in bit, Cin, is called
a full-adder.
The Boolean functions describing the full-adder are:
Sum, S = (x  y)  Cin
Carry, C = xy + Cin (x  y)

Boolean Expression:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
Logic Circuit:

Verilog Code:

module full_adder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum = a^b^c;
assign carry=(a&b)|(b&c)|(c&a);
endmodule

Testbench Code:

module full_adder_tb;

//
Inputs
reg a;
reg b;
reg c;

//
Outputs
wire
sum;
wire
carry;

// Instantiate the Unit Under Test

(UUT)full_adder uut (
.a(a),
.b(b),
.c(c),
.sum(sum),
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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
.carry(carry)
);

initial begin
// Initialize Inputs
a = 0; b = 0; c = 0; #5;
a = 0; b = 0; c = 1; #5;
a = 0; b = 1; c = 0; #5;
a = 0; b = 1; c = 1; #5;
a = 1; b = 0; c = 0; #5;
a = 1; b = 0; c = 1; #5;
a = 1; b = 1; c = 0; #5;
a = 1; b = 1; c = 1; #5;

$finish;

end
endmodule

RTL Schematic:

Simulation output waveform:

Result:

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EXP. No. 5 Four-bit ring counter using D Flip–Flops/JK Flip Flops

DATE:

AIM: To design a four-bit ring counter using D/JK Flip-flops and verify the output using Hardware Description
Language.
Hardware required:PC

Software required: Xilinx ISE Design Suite

Theory:
A ring counter is a type of shift register counter where the output of the last flip-flop is fed back to the input of the first flip-flop,
forming a ring-like structure. In a four-bit ring counter, there are 4 flip-flops, and only one of them is set to '1' at any given time
while the others are set to '0'. This '1' circulates around the ring, creating a sequence of outputs.

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Verilog Code:

Using D Flip Flops:

module ring_counter_d(
input clk, // Clock input
input reset, // Active high reset input
output [3:0] q // 4-bit output
);

reg [3:0] q_reg;

always @(posedge clk or posedge reset) begin

if (reset)
q_reg <= 4'b1000; // Initial state
else
q_reg <= {q_reg[2:0], q_reg[3]}; // Rotate the bits
end

assign q = q_reg;

endmodule

Using JK Flip Flops:

module ring_counter_jk(
input clk, // Clock input
input reset, // Active high reset input
output [3:0] q // 4-bit output
);

reg [3:0] q_reg;

always @(posedge clk or posedge reset) begin

if (reset)
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q_reg <= 4'b1000; // Initial state
else begin
q_reg[0] <= q_reg[3]; // Feedback from last flip-flop
q_reg[1] <= q_reg[0];
q_reg[2] <= q_reg[1];
q_reg[3] <= q_reg[2];
end
end

assign q = q_reg;

endmodule

Testbench Code:

module ring_tb_v;

// Inputs
reg clk;
reg reset;

// Outputs
wire [3:0] q;

// Instantiate the Unit Under Test (UUT)

ring uut (
.clk(clk),
.reset(reset),
.q(q)
);

initial
// Initialize Inputs
clk = 0;
always #10 clk = ~clk;

initial begin
reset = 1; #50;
reset = 0; #50;

$finish;

end

endmodule

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

RTL Schematic:

Simulation output waveform:

Result:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

EXP. No. 6 Four-bit Johnson’s counter using D Flip-Flops/JK Flip Flops

DATE:

AIM: To design a four-bit Johnson’s counter using D/JK flip-flops and verify the output using Hardware Description
Language.

Hardware required:PC

Software required: Xilinx ISE Design Suite

Theory:
A Johnson counter, also known as a twisted ring counter, is a type of shift register where the complement of the last flip-flop’s
output is fed back to the input of the first flip-flop. A four-bit Johnson counter cycles through 8 unique states (twice the number
of flip-flops), making it a MOD-8 counter. This counter can be implemented using either D flip-flops or JK flip-flops.

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Verilog Code:

Using D Flip Flops:

module johnson_counter_dff (
input clk,
input reset,
output reg [3:0] q
);

always @(posedge clk or posedge reset) begin

if (reset)
q <= 4'b0000; // Reset the counter to 0
else begin
q[3] <= ~q[0];
q[2:0] <= q[3:1];
end
end

endmodule

Using JK Flip Flops:

module johnson_counter_4bit_jk(
input clk, // Clock input
input reset, // Reset input
output reg [3:0] q // 4-bit counter output
);

// Internal JK Flip-Flop signals

reg [3:0] j, k;
reg [3:0] q_int;

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
always @(posedge clk or posedge reset) begin
if (reset) begin
q_int <= 4'b0000;
end else begin
q_int[3] <= ~q_int[0];
q_int[2] <= q_int[3];
q_int[1] <= q_int[2];
q_int[0] <= q_int[1];
end
end

assign q = q_int;

endmodule

Testbench Code:

module johnson_tb;

// Inputs
reg clk;
reg reset;

// Outputs
wire [3:0] q;

// Instantiate the Unit Under Test (UUT)

ring uut (
.clk(clk),
.reset(reset),
.q(q)
);

initial
// Initialize Inputs
clk = 0;
always #10 clk = ~clk;

initial begin
reset = 1; #50;
reset = 0; #50;

$finish;

end
endmodule

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
RTL Schematic:

Simulation output waveform:

Result:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

EXP. No. 7 4-bit Universal Shift Register for different Modes of operation
DATE:

AIM: To write HDL codes for the universal shift register

HARDWARE REQUIRED: PC
SOFTWARE REQUIRED : Xilinx ISE Design Suite
Theory:
A universal shift register is a sequential logic that can store data within and on every clock pulse it transfers data to the
output port.
The universal shift register can be used as
1. Parallel In Parallel Out shift register
2. Parallel In Serial Out shift register
3. Serial In Parallel Out shift register
4. Serial In Serial Out shift register

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Verilog Code:
module universal_shift_reg(
input clk, rst_n,
input [1:0] select, // select operation
input [3:0] p_din, // parallel data in
input s_left_din, // serial left data in
input s_right_din, // serial right data in
output reg [3:0] p_dout, //parallel data out
output s_left_dout, // serial left data out
output s_right_dout // serial right data out
);
always@(posedge clk) begin

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
if(!rst_n) p_dout <= 0;
else begin
case(select)
2'h1: p_dout <= {s_right_din,p_dout[3:1]}; // Right Shift
2'h2: p_dout <= {p_dout[2:0],s_left_din}; // Left Shift
2'h3: p_dout <= p_din; // Parallel in - Parallel out
default: p_dout <= p_dout; // Do nothing
endcase
end
end
assign s_left_dout = p_dout[0];
assign s_right_dout = p_dout[3];
endmodule

Testbench Code:

module TB;
reg clk, rst_n;
reg [1:0] select;
reg [3:0] p_din;
reg s_left_din, s_right_din;
wire [3:0] p_dout; //parallel data out
wire s_left_dout, s_right_dout;

universal_shift_reg usr(clk, rst_n, select, p_din, s_left_din, s_right_din, p_dout, s_left_dout, s_right_dout);

always #2 clk = ~clk;

initial begin
$monitor("select=%b, p_din=%b, s_left_din=%b, s_right_din=%b --> p_dout = %b, s_left_dout = %b,
s_right_dout = %b",select, p_din, s_left_din, s_right_din, p_dout, s_left_dout, s_right_dout);
clk = 0; rst_n = 0;
#3 rst_n = 1;

p_din = 4'b1101;
s_left_din = 1'b1;
s_right_din = 1'b0;

select = 2'h3; #10;

select = 2'h1; #20;
p_din = 4'b1101;
select = 2'h3; #10;
select = 2'h2; #20;
select = 2'h0; #20;

$finish;
end
// To enable waveform

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end

endmodule

RTL Schematic:

Simulation output waveform:

Result:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

EXP. No. 8 Construct MOD-8 ripple counter circuit using T-Flip-Flops and Test It with a low
DATE: frequency clock

AIM: To construct MOD-8 ripple counter circuit using T-flip-flops and test it with a low frequency clock using Hardware
Description Language.

Hardware required:PC

Software required: Xilinx ISE Design Suite

Theory:

A MOD-8 ripple counter is a type of asynchronous counter that counts from 0 to 7 (which is 8 states, hence MOD-8)
and then resets to 0. It is called a "ripple" counter because the output of one flip-flop triggers the next flip-flop in the
sequence, causing a "ripple" effect as the clock signal propagates through the flip-flops.

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Verilog Code:
module mod8_ripple_counter_t(
input wire clk, // Clock input
input wire reset, // Reset input
output reg [2:0] q // 3-bit counter output
);

reg t0, t1, t2; // T Flip-Flops

always @(posedge clk or posedge reset) begin

if (reset) begin
t0 <= 1'b0;
t1 <= 1'b0;
t2 <= 1'b0;
end else begin
t0 <= ~t0; // Toggle T Flip-Flop 0
if (t0 == 1'b0) begin
t1 <= ~t1; // Toggle T Flip-Flop 1 when T0 toggles
if (t1 == 1'b0) begin
t2 <= ~t2; // Toggle T Flip-Flop 2 when T1 toggles
end
end
end
end

assign q = {t2, t1, t0};

endmodule

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Testbench Code:

module tb_mod8_ripple_counter_t;

reg clk;
reg reset;
wire [2:0] q;

// Instantiate the MOD-8 ripple counter

mod8_ripple_counter_t uut (
.clk(clk),
.reset(reset),
.q(q)
);

// Generate low-frequency clock signal

always begin
#20 clk = ~clk; // 50 MHz clock (adjust #20 for a lower frequency)
end

// Test sequence
initial begin
// Initialize signals
clk = 0;
reset = 1;

// Apply reset
#30 reset = 0;

// Run the simulation for a while

#500 $finish;
end

// Monitor signals
initial begin
$monitor("At time %t, q = %b", $time, q);
end

endmodule

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RTL Schematic:

Simulation output waveform:

Result:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

EXP. No. 9 MOD–8 synchronous counter using T Flip-Flop

DATE:

AIM: To construct MOD-8 synchronous counter using T flip-flop and verify the result using Hardware Description
Language.

Hardware required:PC

Software required: Xilinx ISE Design Suite

Theory:

A MOD-8 synchronous counter is a type of digital counter that counts from 0 to 7 (which is 8 states, hence MOD-8).
After reaching the count of 7, it resets to 0 and continues counting in a cyclic manner. The counter uses T flip-flops as
the basic building blocks.

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Verilog Code:

module mod8_counter_t(
input wire clk, // Clock input
input wire reset, // Reset input
output reg [2:0] q // 3-bit counter output
);

// T Flip-Flop toggles on every clock edge

reg t[2:0];

always @(posedge clk or posedge reset) begin

if (reset) begin
q <= 3'b000;
end else begin
// T Flip-Flop logic: toggle based on previous state
t[0] <= ~t[0];
if (t[0] == 1'b0) begin
t[1] <= ~t[1];
if (t[1] == 1'b0) begin
t[2] <= ~t[2];
end
end
q <= {t[2], t[1], t[0]};
end
end

endmodule

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Testbench Code:

module tb_mod8_counter_t;

reg clk;
reg reset;
wire [2:0] q;

// Instantiate the MOD-8 counter

mod8_counter_t uut (
.clk(clk),
.reset(reset),
.q(q)
);

// Generate clock signal

always begin
#5 clk = ~clk; // 100 MHz clock
end

// Test sequence
initial begin
// Initialize signals
clk = 0;
reset = 1;

// Apply reset
#10 reset = 0;

// Run the simulation for a while

#200 $finish;
end

// Monitor signals
initial begin
$monitor("At time %t, q = %b", $time, q);
end
endmodule

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

RTL Schematic:

Simulation output waveform:

Result:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

EXP. No. 10(a) Single bit comparator

DATE:

AIM: To design single bit comparator and test the output using Hardware Description Language.

Hardware required:PC

Software required: Xilinx ISE Design Suite

Theory:

A single-bit comparator is a digital logic circuit used to compare two binary inputs, each of 1 bit. The comparator
evaluates whether the two inputs are equal, or if one is greater than or less than the other.

Inputs and Outputs:

• Inputs:
o A: A single-bit binary input (either 0 or 1).
o B: Another single-bit binary input (either 0 or 1).
• Outputs:
o A > B: A binary output that is 1 if A is greater than B, and 0 otherwise.
o A = B: A binary output that is 1 if A is equal to B, and 0 otherwise.
o A < B: A binary output that is 1 if A is less than B, and 0 otherwise.

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Verilog Code:
module single_bit_comparator(
input a, // Input bit a
input b, // Input bit b
output a_eq_b, // Output: a equals b
output a_gt_b, // Output: a greater than b
output a_lt_b // Output: a less than b
);

assign a_eq_b = (a == b);

assign a_gt_b = (a > b);
assign a_lt_b = (a < b);

endmodule

Testbench Code:
module tb_single_bit_comparator;

reg a;
reg b;
wire a_eq_b;
wire a_gt_b;
wire a_lt_b;

// Instantiate the single-bit comparator

single_bit_comparator uut (
.a(a),
.b(b),
.a_eq_b(a_eq_b),
.a_gt_b(a_gt_b),
.a_lt_b(a_lt_b)
);

// Test sequence
initial begin
initial begin
a = 0; b = 0; #5;
a = 0; b = 1; #5;
a = 1; b = 0; #5;
a = 1; b = 1; #5;
$finish;
end

endmodule

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

RTL Schematic:

Simulation output waveform:

Result:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

EXP. No. 10(b) Construct 7 Segment Display Circuit Using Decoder and 7 Segment LED
DATE:

AIM: To construct seven segment display circuit using decoder and seven segment LED and verify the output using
Hardware Description Language.

Hardware required:PC

Software required: Xilinx ISE Design Suite

Theory:

A seven-segment display is an electronic component used to display decimal numbers (0-9) and some alphabets (like
A, b, C, d, E, F) using LEDs arranged in a specific pattern. The display consists of seven LEDs (labeled a through g)
arranged in a figure-eight pattern, and sometimes an eighth LED is used for a decimal point.

Seven-Segment Display Types:

1. Common Cathode (CC): All cathodes of the LEDs are connected together to a ground (GND) terminal, and the anodes
are controlled individually through current-limiting resistors.
2. Common Anode (CA): All anodes are connected together to a positive supply voltage, and the cathodes are connected
to the ground through current-limiting resistors.

Decoder/Driver Circuit:

A decoder/driver circuit is used to convert binary input signals into the corresponding signals required to light up the
appropriate segments on the seven-segment display. The most common decoders used are:

• 74LS47 (for common anode displays)

• 74LS48 (for common cathode displays)

Working Principle:

1. Binary Input: The seven-segment display circuit typically accepts a 4-bit binary input representing the
numbers 0 to 9. This input can be provided by a set of switches or a binary counter.
2. Decoder Functionality:
o The decoder/driver takes the 4-bit binary input and decodes it into seven output signals that correspond to the
segments a to g of the seven-segment display.
o The output signals are then used to drive the segments of the display. For example, to display the number "3,"
the decoder would activate segments a, b, c, d, and g.
3. Current Limiting Resistors: Resistors are placed in series with each LED segment to limit the current
flowing through them, protecting the LEDs from damage due to excessive current.
4. Display Output:
o For a common anode display, the decoder outputs low (0) signals to turn on the corresponding segments by
connecting them to ground.

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
o For a common cathode display, the decoder outputs high (1) signals to turn on the corresponding segments by
connecting them to the supply voltage.

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Verilog Code:
module seven_segment_decoder(
input wire [3:0] binary_in, // 4-bit binary input
output reg [6:0] seg // 7-segment display output (a to g)
);

always @(*) begin

case (binary_in)
4'd0: seg = 7'b0111111; // Display 0
4'd1: seg = 7'b0000110; // Display 1
4'd2: seg = 7'b1011011; // Display 2
4'd3: seg = 7'b1001111; // Display 3
4'd4: seg = 7'b1100110; // Display 4
4'd5: seg = 7'b1101101; // Display 5
4'd6: seg = 7'b1111101; // Display 6
4'd7: seg = 7'b0000111; // Display 7
4'd8: seg = 7'b1111111; // Display 8
4'd9: seg = 7'b1101111; // Display 9
default: seg = 7'b0000000; // Turn off all segments
endcase
end

endmodule

Testbench Code:

module tb_seven_segment_decoder;

reg [3:0] binary_in;

wire [6:0] seg;

// Instantiate the 7-segment decoder

seven_segment_decoder uut (
.binary_in(binary_in),
.seg(seg)
);

// Test sequence
initial begin
// Monitor signals
$monitor("At time %t: binary_in = %d, seg = %b", $time, binary_in, seg);

// Test case 0
binary_in = 4'd0;
#10;

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

// Test case 1
binary_in = 4'd1;
#10;

// Test case 2
binary_in = 4'd2;
#10;

// Test case 3
binary_in = 4'd3;
#10;

// Test case 4
binary_in = 4'd4;
#10;

// Test case 5
binary_in = 4'd5;
#10;

// Test case 6
binary_in = 4'd6;
#10;

// Test case 7
binary_in = 4'd7;
#10;

// Test case 8
binary_in = 4'd8;
#10;

// Test case 9
binary_in = 4'd9;
#10;

// End simulation
$finish;
end

endmodule

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
RTL Schematic:

Simulation output waveform:

Result:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
MATLAB INTRODUCTION:
MATLAB, which stands for Matrix Laboratory, is a state-of-the-art mathematical
software package, which is used extensively in both academia and industry. It is an interactive
program for numerical computation and data visualization, which along with its programming
capabilities provides a very useful tool for almost all areas of science and engineering. Unlike
other mathematical packages, such as MAPLE or MATHEMATICA, MATLAB cannot perform
symbolic manipulations without the use of additional Toolboxes. It remains however, one of the
leading software packages for numerical computation.

As you might guess from its name, MATLAB deals mainly with matrices. A scalar is a 1-
by-1 matrix and a row vector of length say 5, is a 1-by-5 matrix.. One of the many advantages of
MATLAB is the natural notation used. It looks a lot like the notation that you encounter in a
linear algebra. This makes the use of the program especially easy and it is what makes MATLAB
a natural choice for numerical computations. The purpose of this experiment is to familiarize
MATLAB, by introducing the basic features and commands of the program.

MATLAB is case-sensitive, which means that a + B is not the same as a + b. The

MATLAB prompt (») in command window is where the commands are entered.

Operators:

1. + addition

2. -subtraction

3. * multiplication

4. ^ power

5. ' transpose

6. \ left division

7. / right division

Remember that the multiplication, power and division operators can be used in conjunction with
a period to specify an element-wise operation.

Built in Functions:

1. Scalar Functions:

Certain MATLAB functions are essentially used on scalars, but operate element-wise when

applied to a matrix (or vector). They are summarized below.

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
1. sin -trigonometric sine

2. cos -trigonometric cosine

3. tan -trigonometric tangent

4. asin -trigonometric inverse sine (arcsine)

5. acos -trigonometric inverse cosine (arccosine)

6. atan -trigonometric inverse tangent (arctangent)

7. exp -exponential

8. log -natural logarithm

9. abs -absolute value 10. sqrt -square root

11. rem -remainder 12. round -round towards nearest integer

13. floor -round towards negative infinity 14. ceil -round towards positive infinity

2. Vector Functions:

Other MATLAB functions operate essentially on vectors returning a scalar value. Some of

these functions are given below.

1. max largest component : get the row in which the maximum element lies

2. min smallest component

3. length length of a vector

4. sort sort in ascending order

5. sum sum of elements

6. prod product of elements

7. median median value

8. mean mean value std standard deviation

3. Matrix Functions:

Much of MATLAB’s power comes from its matrix functions. These can be further separated into
two sub-categories. The first one consists of convenient matrix building functions, some of
which are given below.

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

1. eye -identity matrix

2. zeros -matrix of zeros

3. ones -matrix of ones

4. diag -extract diagonal of a matrix or create diagonal matrices

5. triu -upper triangular part of a matrix

6. tril -lower triangular part of a matrix

7. rand -randomly generated matrix

eg: diag([0.9092;0.5163;0.2661])

ans =

0.9092 0 0

0 0.5163 0

0 0 0.2661

Commands in the second sub-category of matrix functions are

1. size size of a matrix

2. det determinant of a square matrix

3. inv inverse of a matrix

4. rank rank of a matrix

5. rref reduced row echelon form

6. eig eigenvalues and eigenvectors

Procedure to run Matlab Program:

1.Open the Matlab

2.Open the new m file
3.Type the program and save it in current directory
4.Compile and run the program
5.For the output see the command window and figure window

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

1. Generations of various Signals and Sequences

Aim: Generate various signals and sequences (Periodic and aperiodic), such as Unit Impulse,
Unit Step, Square, Saw tooth, Triangular, Sinusoidal, Ramp, Sinc.
Software Required: Matlab software
Theory: If the amplitude of the signal is defined at every instant of time, then it is called
continuous time signal. If the amplitude of the signal is defined at only at some instants of time,
then it is called discrete time signal. If the signal repeats itself at regular intervals, then it is called
periodic signal. Otherwise they are called aperiodic signals.
EX: ramp, Impulse, unit step, sinc- Aperiodic signals square, sawtooth, triangular sinusoidal –
periodic signals.
» plot(x,y)

It is good practice to label the axis on a graph and if applicable indicate what each axis
represents. This can be done with the xlabel and ylabel commands.

» xlabel('x')

» ylabel('y=cos(x)')

Inside parentheses, and enclosed within single quotes, we type the text that we wish to be
displayed along the x and y axis, respectively. We could even put a title on top using

» title('Graph of cosine from -pi to pi')

» plot (x,y,’g’)

Where the third argument indicating the color, appears within single quotes. We could get a
dashed line instead of a solid one by typing

» plot (x,y,’--’)

or even a combination of line type and color, say a blue dotted line by typing

» plot (x,y,’b:’)

We can get both graphs on the same axis, distinguished by their line type, using

» plot(x,y,'r--',x,z,'b:')

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
When multiple curves appear on the same axis, it is a good idea to create a legend to label and
distinguish them. The command legend does exactly this.

» legend ('cos(x)','sin(x)')

The text that appears within single quotes as input to this command, represents the legend
labels. We must be consistent with the ordering of the two curves, so since in the plot command
we asked for cosine to be plotted before sine, we must do the same here.

At any point during a MATLAB session, you can obtain a hard copy of the current plot
by either issuing the command print at the MATLAB prompt, or by using the command menus
on the plot window. In addition, MATLAB plots can by copied and pasted (as pictures) in your
favorite word processor (such as Microsoft Word). This can be achieved using the Edit menu on
the figure window. Another nice feature that can be used in conjunction with plot is the
command grid, which places grid lines to the current axis (just like you have on graphing paper).
Type help grid for more information. Other commands for data visualization that exist in
MATLAB include subplot create an array of (tiled) plots in the same window log log plot using
log-log scales semi logx plot using log scale on the x-axis semi logy plot using log scale on the
y-axis
The Sinc Function
The sinc function computes the mathematical sinc function for an input vector or matrix x.

Viewed as a function of time, or space, the sinc function is the inverse Fourier transform of the
rectangular pulse in frequency centered at zero of width 2p and height
The sinc function has a value of 1 when x is equal to zero, and a value of for all other elements
of x.
% Generation of signals and sequences
clc;
clear all;
close all;
%~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%generation of unit impulse signal
t1=-1:0.01:1
y1=(t1==0);
subplot(2,2,1);
plot(t1,y1);
xlabel('time');
ylabel('amplitude');
title('unit impulse signal');
%generation of impulse sequence
subplot(2,2,2);
stem(t1,y1);
xlabel('n');
ylabel('amplitude');

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
title('unit impulse sequence');
%~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%generation of unit step signal
t2=-10:1:10;
y2=(t2>=0);
subplot(2,2,3);
plot(t2,y2);
xlabel('time');
ylabel('amplitude');
title('unit step signal');
%generation of unit step sequence
subplot(2,2,4);
stem(t2,y2);
xlabel('n');
ylabel('amplitude');
title('unit step sequence');
%~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%generation of square wave signal
t=0:0.002:0.1;
y3=square(2*pi*50*t);
figure;
subplot(2,2,1);
plot(t,y3);
axis([0 0.1 -2 2]);
xlabel('time');
ylabel('amplitude');
title('square wave signal');
%generation of square wave sequence
subplot(2,2,2);
stem(t,y3);
axis([0 0.1 -2 2]);
xlabel('n');
ylabel('amplitude');
title('square wave sequence');
%~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%generation of sawtooth signal
y4=sawtooth(2*pi*50*t);
subplot(2,2,3);
plot(t,y4);
axis([0 0.1 -2 2]);
xlabel('time');
ylabel('amplitude');
title('sawtooth wave signal');
%generation of sawtooth sequence
subplot(2,2,4);
stem(t,y4);
axis([0 0.1 -2 2]);

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
xlabel('n');
ylabel('amplitude');
title('sawtooth wave sequence');
%~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%generation of triangular wave signal
y5=sawtooth(2*pi*50*t,.5);
figure;
subplot(2,2,1);
plot(t,y5);
axis([0 0.1 -2 2]);
xlabel('time');
ylabel('amplitude');
title(' triangular wave signal');
%generation of triangular wave sequence
subplot(2,2,2);
stem(t,y5);
axis([0 0.1 -2 2]);
xlabel('n');
ylabel('amplitude');
title('triangular wave sequence');
%generation of sinsoidal wave signal
y6=sin(2*pi*40*t);
subplot(2,2,3);
plot(t,y6);
axis([0 0.1 -2 2]);
xlabel('time');
ylabel('amplitude');
title(' sinsoidal wave signal');
%generation of sin wave sequence
subplot(2,2,4);
stem(t,y6);
axis([0 0.1 -2 2]);
xlabel('n');
ylabel('amplitude');
title('sin wave sequence');
%~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%generation of ramp signal
y7=t;
figure;
subplot(2,2,1);
plot(t,y7);
xlabel('time');
ylabel('amplitude');
title('ramp signal');
%generation of ramp sequence
subplot(2,2,2);
stem(t,y7);

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
xlabel('n');
ylabel('amplitude');
title('ramp sequence');
%~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%generation of sinc signal
t3=linspace(-5,5);
y8=sinc(t3);
subplot(2,2,3);
plot(t3,y8);
xlabel('time');
ylabel('amplitude');
title(' sinc signal');
%generation of sinc sequence
subplot(2,2,4);
stem(y8);
xlabel('n');
ylabel('amplitude');
title('sinc sequence');

OUTPUT WAVEFORM:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Result:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
1. Operations on Signals and Sequences

Aim: To performs functions on signals and sequences such as addition, multiplication, scaling,
shifting, folding, computation of energy and average power.

Theory:

Signal Addition
Addition: any two signals can be added to form a third signal,
z (t) = x (t) + y (t)
Multiplication:
Multiplication of two signals can be obtained by multiplying their values at every instant. z
z(t) = x (t) y (t)
Time reversal/Folding:
Time reversal of a signal x(t) can be obtained by folding the signal about t=0.
Y(t)=y(-t)
Signal Amplification/Scaling : Y(n)=ax(n) if a < 1 attenuation
a >1 amplification
Time shifting: The time shifting of x(n) obtained by delay or advance the signal in time by
using y(n)=x(n+k)
If k is a positive number, y(n) shifted to the right i e the shifting delays the signal
If k is a negative number, y(n ) it gets shifted left. Signal Shifting advances the signal
Program :

clc;
clear all;
close all;
% generating two input signals
t=0:.01:1;
x1=sin(2*pi*4*t);
x2=sin(2*pi*8*t);
subplot(2,2,1);
plot(t,x1);
xlabel('time');
ylabel('amplitude');
title('input signal 1');
subplot(2,2,2);

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
plot(t,x2);
xlabel('time');
ylabel('amplitude');
title('input signal 2');
% addition of signals
y1=x1+x2;
subplot(2,2,3);
plot(t,y1);
xlabel('time');
ylabel('amplitude');
title('addition of two signals');
% multiplication of signals
y2=x1.*x2;
subplot(2,2,4);
plot(t,y2);
xlabel('time');
ylabel('amplitude');
title('multiplication of two signals');
% scaling of a signal1
A=2;
y3=A*x1;
figure;
subplot(2,2,1);
plot(t,x1);
xlabel('time');
ylabel('amplitude');
title('input signal')
subplot(2,2,2);
plot(t,y3);
xlabel('time');
ylabel('amplitude');
title('amplified input signal');
% folding of a signal1
h=length(x1);
nx=0:h-1;
subplot(2,2,3);
plot(nx,x1);
xlabel('nx');
ylabel('amplitude');
title('input signal')
y4=fliplr(x1);
nf=-fliplr(nx);
subplot(2,2,4);
plot(nf,y4);
xlabel('nf');
ylabel('amplitude');
title('folded signal');

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
%shifting of a signal 1
figure;
subplot(3,1,1);
plot(t,x1);
xlabel('time t');
ylabel('amplitude');
title('input signal');
subplot(3,1,2);
plot(t+2,x1);
xlabel('t+2');
ylabel('amplitude');
title('right shifted signal');
subplot(3,1,3);
plot(t-2,x1);
xlabel('t-2');
ylabel('amplitude');
title('left shifted signal');
%operations on sequences
n1=1:1:9;
s1=[1 2 3 0 5 8 0 2 4];
figure;
subplot(2,2,1);
stem(n1,s1);
xlabel('n1');
ylabel('amplitude');
title('input sequence1');
s2=[1 1 2 4 6 0 5 3 6];
subplot(2,2,2);
stem(n1,s2);
xlabel('n2');
ylabel('amplitude');
title('input sequence2');
% addition of sequences
s3=s1+s2;
subplot(2,2,3);
stem(n1,s3);
xlabel('n1');
ylabel('amplitude');
title('sum of two sequences');
% multiplication of sequences
s4=s1.*s2;
subplot(2,2,4);
stem(n1,s4);
xlabel('n1');
ylabel('amplitude');
title('product of two sequences');
%~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
% program for energy of a sequence
z1=input('enter the input sequence');
e1=sum(abs(z1).^2);
disp('energy of given sequence is');e1
% program for energy of a signal
t=0:pi:10*pi;
z2=cos(2*pi*50*t).^2;
e2=sum(abs(z2).^2);
disp('energy of given signal is');e2
% program for power of a sequence
p1= (sum(abs(z1).^2))/length(z1);
disp('power of given sequence is');p1
% program for power of a signal
p2=(sum(abs(z2).^2))/length(z2);
disp('power of given signal is');

Output:
enter the input sequence[1 3 2 4 1]
energy of given sequence is
e1 = 31
energy of given signal is
e2 = 4.0388
power of given sequence is
p1 = 6.2000
power of given signal is
p2 = 0.3672

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Result:

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Dept. of ECE CHADALAWADA RAMANAMMA ENGINEERING COLLEGE(A) Page | 62
 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
3.To find the trigonometric & exponential Fourier series coefficients of a
rectangular periodic signal, reconstruct the signal and [lot the discrete
spectrum of the signal.
Aim: To find the trigonometric & exponential Fourier series coefficients of a rectangular
periodic signal. Reconstruct the signal by combining the Fourier series coefficients with
appropriate weightages- Plot the discrete spectrum of the signal.

Theory: to compute the trigonometric fourier series coefficients of a periodic square wave time
signal that has a value of 2 from time 0 to 3 and a value of -12 from time 3 to 6. It then repeats
itself. I am trying to calculate in MATLAB the fourier series coefficients of this time signal and
am having trouble on where to begin.

The equation is x(t) = a0 + sum(bk*cos(2*pi*f*k*t)+ck*sin(2*pi*f*k*t))

The sum is obviously from k=1 to k=infinity.
a0, bk, and ck are the coefficients
Program:

% Description: This M-file plots the truncated Fourier Series

% representation of a square wave as well as its
% amplitude and phase spectrum.

clear; % clear all variables

clf; % clear all figures

N = 11; % summation limit (use N odd)

wo = pi; % fundamental frequency (rad/s)
c0 = 0; % dc bias
t = -3:0.01:3; % declare time values

figure(1) % put first two plots on figure 1

% Compute yce, the Fourier Series in complex exponential form

yce = c0*ones(size(t)); % initialize yce to c0

for n = -N:2:N, % loop over series index n (odd)

cn = 2/(j*n*wo); % Fourier Series Coefficient
yce = yce + real(cn*exp(j*n*wo*t)); % Fourier Series computation
end

subplot(2,1,1)
plot([-3 -2 -2 -1 -1 0 0 1 1 2 2 3],... % plot original y(t)

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

[-1 -1 1 1 -1 -1 1 1 -1 -1 1 1], ':');

hold;
plot(t,yce); % plot truncated exponential FS
xlabel('t (seconds)'); ylabel('y(t)');
ttle = ['EE341.01: Truncated Exponential Fourier Series with N = ',...
num2str(N)];
title(ttle);
hold;

% Compute yt, the Fourier Series in trigonometric form

yt = c0*ones(size(t)); % initialize yt to c0

for n = 1:2:N, % loop over series index n (odd)

cn = 2/(j*n*wo); % Fourier Series Coefficient
yt = yt + 2*abs(cn)*cos(n*wo*t+angle(cn)); % Fourier Series computation
end

subplot(2,1,2)
plot([-3 -2 -2 -1 -1 0 0 1 1 2 2 3],... % plot original y(t)
[-1 -1 1 1 -1 -1 1 1 -1 -1 1 1], ':');
hold; % plot truncated trigonometric FS
plot(t,yt);
xlabel('t (seconds)'); ylabel('y(t)');
ttle = ['EE341.01: Truncated Trigonometric Fourier Series with N = ',...
num2str(N)];
title(ttle);
hold;

% Draw the amplitude spectrum from exponential Fourier Series

figure(2) % put next plots on figure 2

subplot(2,1,1)
stem(0,c0); % plot c0 at nwo = 0

hold;
for n = -N:2:N, % loop over series index n
cn = 2/(j*n*wo); % Fourier Series Coefficient
stem(n*wo,abs(cn)) % plot |cn| vs nwo
end
for n = -N+1:2:N-1, % loop over even series index n
cn = 0; % Fourier Series Coefficient
stem(n*wo,abs(cn)); % plot |cn| vs nwo
end

xlabel('w (rad/s)')
ylabel('|cn|')
ttle = ['EE341.01: Amplitude Spectrum with N = ',num2str(N)];
title(ttle);
grid;
hold;

% Draw the phase spectrum from exponential Fourier Series

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

subplot(2,1,2)
stem(0,angle(c0)*180/pi); % plot angle of c0 at nwo = 0

hold;
for n = -N:2:N, % loop over odd series index n
cn = 2/(j*n*wo); % Fourier Series Coefficient
stem(n*wo,angle(cn)*180/pi); % plot |cn| vs nwo
end
for n = -N+1:2:N-1, % loop over even series index n
cn = 0; % Fourier Series Coefficient
stem(n*wo,angle(cn)*180/pi); % plot |cn| vs nwo
end
xlabel('w (rad/s)')
ylabel('angle(cn) (degrees)')
ttle = ['EE341.01: Phase Spectrum with N = ',num2str(N)];
title(ttle);
grid;
hold;

OUTPUT WAVEFORM:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Result:

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Dept. of ECE CHADALAWADA RAMANAMMA ENGINEERING COLLEGE(A) Page | 66
 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
4. To find Fourier transform of a given signal and plot its amplitude
and phase spectrum.

Aim: To find the Fourier Transform of a given signal and plotting its magnitude and phase
spectrum.
Software Required: Matlab software
Theory:
Fourier Transform:
The Fourier transform as follows. Suppose that ƒ is a function which is zero outside of some
interval [−L/2, L/2]. Then for any T ≥ L we may expand ƒ in a Fourier series on the interval
[−T/2,T/2], where the "amount" of the wave e2πinx/T in the Fourier series of ƒ is given by By
definition Fourier Transform of signal f(t) is defined as

Program:
clc;
clear all;
close all;
fs=1000;
N=1024; % length of fft sequence
t=[0:N-1]*(1/fs);
% input signal
x=0.8*cos(2*pi*100*t);
subplot(3,1,1);
plot(t,x);
axis([0 0.05 -1 1]);
grid;
xlabel('t');
ylabel('amplitude');
title('input signal');
% Fourier transform of given signal
x1=fft(x);
% magnitude spectrum
k=0:N-1;
Xmag=abs(x1);
subplot(3,1,2);
plot(k,Xmag);
grid;
xlabel('t');
ylabel('amplitude');
title('magnitude of fft signal')
%phase spectrum

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Xphase=angle(x1);
subplot(3,1,3);
plot(k,Xphase);
grid;
xlabel('t');
ylabel('angle');
title('phase of fft signal');

OUTPUT WAVEFORM:

Result:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
5. To convolve two discrete time sequences and plot all the sequences
Aim: Write the program for convolution between two signals and also between two
sequences.
Software Required: Matlab software
Theory:
Convolution involves the following operations.
• Folding
• Multiplication
• Addition
• Shifting

Convolution is an integral concatenation of two signals. It is used for the determination of the
output signal of a linear time-invariant system by convolving the input signal with the impulse
response of the system. Note that convolving two signals is equivalent to multiplying the Fourier
transform of the two signals.

These operations can be represented by a Mathematical Expression as follows:

x[n]= Input signal Samples
h[ n-k]= Impulse response co-efficient.
y[ n]= Convolution output.
n = No. of Input samples
h = No. of Impulse response co-efficient.
Example : X(n)={1 2 -1 0 1}, h(n)={ 1,2,3,-1}

Program:
clc;
close all;
clear all;
%program for convolution of two sequences
x=input('enter input sequence: ');
h=input('enter impulse response: ');
y=conv(x,h);
subplot(3,1,1);
stem(x);
xlabel('n');
ylabel('x(n)');
title('input sequence')

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

subplot(3,1,2);
stem(h);
xlabel('n');
ylabel('h(n)');
title('impulse response sequence')
subplot(3,1,3);
stem(y);
xlabel('n');
ylabel('y(n)');
title('linear convolution')
disp('linear convolution y=');
disp(y)
%program for signal convolution
t=0:0.1:10;
x1=sin(2*pi*t);
h1=cos(2*pi*t);
y1=conv(x1,h1);
figure;
subplot(3,1,1);
plot(x1);
xlabel('t');
ylabel('x(t)');
title('input signal')
subplot(3,1,2);
plot(h1);
xlabel('t');
ylabel('h(t)');
title('impulse response')
subplot(3,1,3);
plot(y1);
xlabel('n');
ylabel('y(n)');
title('linear convolution');
.
Output:
enter input sequence: [1 3 4 5]
enter impulse response: [2 1 4]
linear convolution y=
2 7 15 26 21 20

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

RESULT:

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Dept. of ECE CHADALAWADA RAMANAMMA ENGINEERING COLLEGE(A) Page | 71
 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
6. To find auto correlation and cross correlation of given sequences.
Aim: To compute Auto correlation and Cross correlation between signals and sequences.
Software Required: Mat lab software
Theory:
Correlations of sequences:
It is a measure of the degree to which two sequences are similar. Given two real-valued
sequences x(n) and y(n) of finite energy,
Convolution involves the following operations.
1. Shifting
2. Multiplication
3. Addition
Program:
clc;
close all;
clear all;
% two input sequences
x=input('enter input sequence');
h=input('enter the impulse suquence');
subplot(2,2,1);
stem(x);
xlabel('n');
ylabel('x(n)');
title('input sequence');
subplot(2,2,2);
stem(h);
xlabel('n');
ylabel('h(n)');
title('impulse sequence');
% cross correlation between two
y=xcorr(x,h);
subplot(2,2,3);
stem(y);
xlabel('n');
ylabel('y(n)');
title(' cross correlation between two sequences ');
% auto correlation of input sequence
z=xcorr(x,x);
subplot(2,2,4);
stem(z);

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
xlabel('n');
ylabel('z(n)');
title('auto correlation of input sequence');
% cross correlation between two signals
% generating two input signals
t=0:0.2:10;
x1=3*exp(-2*t);
h1=exp(t);
figure;
subplot(2,2,1);
plot(t,x1);
xlabel('t');
ylabel('x1(t)');
title('input signal');
subplot(2,2,2);
plot(t,h1);
xlabel('t');
ylabel('h1(t)');
title('impulse signal');
% cross correlation
subplot(2,2,3);
z1=xcorr(x1,h1);
plot(z1);
xlabel('t');
ylabel('z1(t)');
title('cross correlation ');
% auto correlation
subplot(2,2,4);
z2=xcorr(x1,x1);
plot(z2);
xlabel('t');
ylabel('z2(t)');
title('auto correlation ');

Output: enter input sequence [1 2 5 7]

enter the impulse sequence [2 6 0 5 3]

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Result:

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Dept. of ECE CHADALAWADA RAMANAMMA ENGINEERING COLLEGE(A) Page | 74
 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
7. To verify Linearity and Time Invariance properties of a given
Continuous/Discrete System.

Aim: Verify the Linearity of a given Discrete System.

Software Required: Mat lab software 7.0 and above
Theory:
linearity property:
Any system is said to be linear if it satisfies the superposition principal. Superposition principal
state that Response to a weighted sum of input signal equal to the corresponding weighted sum
of the outputs of the system to each of the individual input signals. If x(n) is a input signal and
y(n) is a output signal then y(n)=T[x(n)]
y1(n)=T[x1(n)] and y2(n)=T[x2(n)]
x3=[a*x1(n) +b *x2(n) ]
Y3(n)= T [x3(n)]
T [a*x1(n)+b*x2(n) ] = a y1(n)+ b y2(n)
Program (A) :
% Verification of Linearity of a given System.
% a) y(n)=nx(n) b) y=x^2(n)
clc;
clear all;
close all;
n=0:40;
a1=input('enter the scaling factor a1=');
a2=input('enter the scaling factor a2=');
x1=cos(2*pi*0.1*n);
x2=cos(2*pi*0.4*n);
x3=a1*x1+a2*x2;
%y(n)=n.x(n);
y1=n.*x1;
y2=n.*x2;
y3=n.*x3;
yt=a1*y1+a2*y2;
yt=round(yt);
y3=round(y3);
if y3==yt
disp('given system [y(n)=n.x(n)]is Linear');
else
disp('given system [y(n)=n.x(n)]is non Linear');
end
%y(n)=x(n).^2
x1=[1 2 3 4 5];
x2=[1 4 7 6 4];
x3=a1*x1+a2*x2;
y1=x1.^2;

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

y2=x2.^2;
y3=x3.^2;
yt=a1*y1+a2*y2;
if y3==yt
disp('given system [y(n)=x(n).^2 ]is Linear');
else
disp('given system is [y(n)=x(n).^2 ]non Linear');
end

Output:
enter the scaling factor a1=3
enter the scaling factor a2=5
given system [y(n)=n.x(n)]is Linear
given system is [y(n)=x(n).^2 ]non Linear
Program (B) :

% Verification of Time Invariance of a Discrete System

% a)y=x^2(n) b) y(n)=nx(n)
clc;
clear all;
close all;
n=1:9;
x(n)=[1 2 3 4 5 6 7 8 9];
d=3; % time delay
xd=[zeros(1,d),x(n)];%x(n-k)
y(n)=x(n).^2;
yd=[zeros(1,d),y];%y(n-k)
disp('transformation of delay signal yd:');disp(yd)
dy=xd.^2; % T[x(n-k)]
disp('delay of transformation signal dy:');disp(dy)
if dy==yd
disp('given system [y(n)=x(n).^2 ]is time invariant');
else
disp('given system is [y(n)=x(n).^2 ]not time invariant');
end
y=n.*x;
yd=[zeros(1,d),y(n)];
disp('transformation of delay signal yd:');disp(yd);
n1=1:length(xd);
dy=n1.*xd;
disp('delay of transformation signal dy:');disp(dy);
if yd==dy
disp('given system [y(n)=nx(n)]is a time invariant');
else
disp('given system [y(n)=nx(n)]not a time invariant');
end

Output:
transformation of delay signal yd:
0 0 0 1 4 9 16 25 36 49 64 81
delay of transformation signal dy:
0 0 0 1 4 9 16 25 36 49 64 81
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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

given system [y(n)=x(n).^2 ]is time invariant

transformation of delay signal yd:
0 0 0 1 4 9 16 25 36 49 64 81
delay of transformation signal dy:
0 0 0 4 10 18 28 40 54 70 88 108
given system [y(n)=nx(n)]not a time invariant

Result:

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
8. To generate discrete time sequence by sampling a continuous time signal.
Show that with sampling rates less than Nyquist rate, aliasing occurs while
reconstructing the signal.

Aim: Verify the sampling theorem.

Software Required: Matlab software
Theory:
Sampling Theorem:
\A bandlimited signal can be reconstructed exactly if it is sampled at a rate atleast twice the
maximum frequency component in it."

The maximum frequency component of g(t) is fm. To recover the signal g(t) exactly from its
samples it has to be sampled at a rate fs ≥ 2fm.
The minimum required sampling rate fs = 2fm is called ' Nyquist rate

Program:
clc;
clear all;
close all;
t=-10:.01:10;
T=4;
fm=1/T;
x=cos(2*pi*fm*t);
subplot(2,2,1);
plot(t,x);
xlabel('time');
ylabel('x(t)');
title('continous time signal');
grid;
n1=-4:1:4;
fs1=1.6*fm;
fs2=2*fm;
fs3=8*fm;
x1=cos(2*pi*fm/fs1*n1);
subplot(2,2,2);
stem(n1,x1);
xlabel('time');
ylabel('x(n)');
title('discrete time signal with fs<2fm');
hold on;
subplot(2,2,2);
plot(n1,x1);
grid;
n2=-5:1:5;
x2=cos(2*pi*fm/fs2*n2);

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

subplot(2,2,3);
stem(n2,x2);
xlabel('time');
ylabel('x(n)');
title('discrete time signal with fs=2fm');
hold on;
subplot(2,2,3);
plot(n2,x2)
grid;
n3=-20:1:20;
x3=cos(2*pi*fm/fs3*n3);
subplot(2,2,4);
stem(n3,x3);
xlabel('time');
ylabel('x(n)');
title('discrete time signal with fs>2fm')
hold on;
subplot(2,2,4);
plot(n3,x3)
grid;

Result:

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Dept. of ECE CHADALAWADA RAMANAMMA ENGINEERING COLLEGE(A) Page | 79
 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
9. To find magnitude and phase response of first order low pass and high
pass filter. Plot the responses in logarithmic scale.

Aim: To find magnitude and phase response of first order low pass and high pass filter. Plot the
responses in logarithmic scale.

Theory: To get the phase response in the time domain you need to estimate the delay between
the input and the output at the test frequency and then convert to phase. For sure, taking the angle
of the RMS ratio will not yield that delay. If you really want to estimate the delay in the time
domain, there is a function called finddelay that may be of use.

However, the alternative approach is to work in the frequncy domain, i.e., use the ratio of the
frequency response of the output to the frequency resposne of the input to directly stimate the
magnitude and phase response of the system. The code that follows shows how to do that for a
simple low pass filter. Keep in mind, that any approach you use may begin to suffere as you test
frequency gets close to the Nyquist frequency. You can experiment with this code to see how
close you can get before this simple approach begins to break down.

Program :

f=1:15;
% second order filter with 10 Hz pass band
H = @(f,s) 1./(1./(2*pi*f).^2*s.^2 + 2./(2*pi*f)*s + 1);
H10 = @(s) H(10,s);
% magnitude estimation
magn = abs(H10(1j*2*pi*f));
% phase estimation
phase = rad2deg( angle(H10(1j*2*pi*f)) );
figure;
subplot(2,1,1);
semilogx(f,mag2db(magn));
title('Frequency response of the filter using abs(Out/Inp)')
xlabel('Frequency');
ylabel ('Change in output/input P-P' );
subplot(2,1,2);
semilogx(f,phase);
title('Phase response of the filter using angle(Out/Inp)')
xlabel('Frequency');
ylabel ('phase' );
% check against inbuilt functions
H_tf = @(f) tf(1,[1./(2*pi*f).^2 2./(2*pi*f) 1]);
figure;
bodeplot(H_tf(10),2*pi*f)

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Result:

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Dept. of ECE CHADALAWADA RAMANAMMA ENGINEERING COLLEGE(A) Page | 81
 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

10. To find response of a low pass filter and high pass filter, when a speech
signal is passed through these filters.

Aim: To find response of a low pass filter and high pass filter, when a speech signal is passed
through these filters.

Theory:

y = lowpass(x,wpass) filters the input signal x using a lowpass filter with normalized passband
frequency wpass in units of π rad/sample. lowpass uses a minimum-order filter with a stopband
attenuation of 60 dB and compensates for the delay introduced by the filter. If x is a matrix, the function
filters each column independently.
y = lowpass(x,fpass,fs) specifies that x has been sampled at a rate of fs hertz. fpass is the
passband frequency of the filter in hertz.
y = lowpass(xt,fpass) lowpass-filters the data in timetable xt using a filter with a passband frequency
of fpass hertz. The function independently filters all variables in the timetable and all columns inside each
variable.
y = lowpass( ,Name,Value) specifies additional options for any of the previous syntaxes using name-
value pair arguments. You can change the stopband attenuation, the transition band steepness, and the
type of impulse response of the filter.
[y,d] = lowpass( ) also returns the digitalFilter object d used to filter the input.
lowpass( ) with no output arguments plots the input signal and overlays the filtered signal.

Program :
% Read standard sample tune that ships with MATLAB.
[dataIn, Fs] = audioread('guitartune.wav');
% Filter the signal
fc = 800; % Make higher to hear higher frequencies.
% Design a Butterworth filter.
[b, a] = butter(6,fc/(Fs/2));
freqz(b,a)
% Apply the Butterworth filter.
filteredSignal = filter(b, a, dataIn);
% Play the sound.
player = audioplayer(filteredSignal, Fs);
play(player);

Result:

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Dept. of ECE CHADALAWADA RAMANAMMA ENGINEERING COLLEGE(A) Page | 82
 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

11. To generate Complex Gaussian noise and find its mean, variance,
Probability Density Function (PDF) and Power Spectral Density (PSD).

Aim: Write the program for generation of Gaussian noise and computation of its mean, mean
square value, standard deviation, variance, and skewness.
Software Required: Matlab software
Theory:
Gaussian noise is statistical noise that has a probability density function (abbreviated pdf) of
the normal distribution (also known as Gaussian distribution). In other words, the valuestha the
noise can take on are Gaussian-distributed. It is most commonly used as additive white noise to
yield additive white Gaussian noise (AWGN).Gaussian noise is properly defined as the noise
with a Gaussian amplitude distribution. says nothing of the correlation of the noise in time or of
the spectral density of the noise. Labeling Gaussian noise as 'white' describes the correlation of
the noise. It is necessary to use the term "white Gaussian noise" to be correct. Gaussian noise is
sometimes misunderstood to be white Gaussian noise, but this is not the case.
Program:
clc;
clear all;
close all;
%generates a set of 2000 samples of Gaussian distributed random numbers
x=randn(1,2000);
%plot the joint distribution of both the sets using dot.
subplot(211)
plot(x,'.');
title('scatter plot of gaussian distributed random numbers');
ymu=mean(x)
ymsq=sum(x.^2)/length(x)
ysigma=std(x)
yvar=var(x)
yskew=skewness(x)
p=normpdf(x,ymu,ysigma);
subplot(212);
stem(x,p);
title(' gaussian distribution');
Output:
ymu = 0.0403
ymsq = 0.9727
ysigma = 0.9859
yvar = 0.9720
yskew = 0.0049

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Result:

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Dept. of ECE CHADALAWADA RAMANAMMA ENGINEERING COLLEGE(A) Page | 84
 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER
12. Generate a Random data (with bipolar) for a given data rate (say 10kbps).
Plot the same for a time period of 0.2 sec.

Aim: To Generate a Random data (with bipolar) for a given data rate (say 10kbps). Plot the same
for a time period of 0.2 sec.

Theory:

X = rand returns a single uniformly distributed random number in the interval (0,1).

X = rand(n) returns an n-by-n matrix of random numbers.

X = rand(sz1,...,szN) returns an sz1-by-...-by-szN array of random numbers

where sz1,...,szN indicate the size of each dimension. For example, rand(3,4) returns a 3-by-4
matrix.

X = rand(sz) returns an array of random numbers where size vector sz specifies size(X). For
example, rand([3 4]) returns a 3-by-4 matrix.

X = rand( ,typename) returns an array of random numbers of data type typename.

The typename input can be either 'single' or 'double'. You can use any of the input arguments in
the previous syntaxes.

Program :
clc;
clear all;
a=-3
b=3
x=rand
c=a+(b-a)*x
y=c^2
z=y
for i=1:1000
x1=rand
c1=a+(b-a)*x1
y1=c1^2
if y1<z
z=y1
else
z;
end
end

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

13. To plot pole-zero diagram in S-plane/Z-plane of given signal/sequence and

Aim: Write the program for locating poles and zeros and plotting pole-zero maps in s-plane
and z-plane for the given transfer function.
Software Required: Matlab software
Theory:
Z-transforms
The Z-transform, like many other integral transforms, can be defined as either a one-sided or
two-sided transform.

Program
clc;
clear all;
close all;

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

%enter the numerator and denamenator cofficients in square brackets

num=input('enter numerator co-efficients');

den=input('enter denominator co-efficients');

% find poles and zeros
poles=roots(den)
zeros=roots(num)
% find transfer function H(s)
h=tf(num,den);
% plot the pole-zero map in s-plane
sgrid;
pzmap(h);
grid on;
title('locating poles and zeros on s-plane');
%plot the pole zero map in z-plane
figure
zplane(poles,zeros);
grid on;
title('locating poler and zeros on z-plane');
Result: Pole-zero maps are plotted in s-plane and z-plane for the given transfer function.
Output:
enter numerator co-efficients[1 -1 4 3.5]
enter denominator co-efficients[2 3 -2.5 6]
poles =
-2.4874
0.4937 + 0.9810i
0.4937 - 0.9810i
zeros =
0.8402 + 2.1065i
0.8402 - 2.1065i
-0.6805

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 DIGITAL CIRCUITS AND SIGNAL SIMULATION LAB II B.TECH I SEMESTER

Result:

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Dept. of ECE CHADALAWADA RAMANAMMA ENGINEERING COLLEGE(A) Page | 88