Accessing I/O Devices

 One of the basic features of a computer is its ability to transfer data to and from I/O
devices.
 An interconnection network is used to transfer data among the processor, memory, and
I/O devices. The commonly used interconnection network called a bus.
 The arrangement shown in below figure is a simple single bus structure that implements
the interconnection network.

 The bus enables all the devices connected to it to exchange the information.
 The bus consists of three sets of lines used to carry address, data, and control signals.
 Each I/O device is assigned a unique set of addresses.
 When the processor places a particular address on the address lines, it is examined by
the address decoders of all devices on the bus.
 The device that recognizes this address responds to the commands issued on the control
lines.
 The processor uses the control lines to request either a Read or a Write operation,
transferring the requested data over the data lines.
 When I/O devices and memory share the same address space, the arrangement is known
as memory-mapped I/O
 In memory-mapped I/O any machine instruction that can access memory can be used to
transfer data to or from an I/O device.
For example, if the input device in Figure is a keyboard and if DATAIN is its data register, the
instruction
Move DATAIN, R2
Reads the data from DATAIN and stores them into the processor register R2.
Similarly
Move R2,DATAOUT
Sends the data in R2 to DATAOUT for display.

 The hardware required to connect the I/O devices to bus is shown below

 I/O device is connected to the bus using an I/O interface circuit which has: - Address
decoder, control circuit, and data and status registers.
  Address decoder decodes the address placed on the address lines thus enabling the
device to recognize its address.
 Data register holds the data being transferred to or from the processor.
 Status register holds information necessary for the operation of the I/O device.
 Data and status registers are connected to the data lines, and have unique addresses.
 I/O interface circuit coordinates I/O transfers.

The rate of transfer to and from I/O devices is slower than the speed of the processor. This
creates the need for mechanisms to synchronize data transfers between them.
INTERRUPTS
 In the programmed I/O transfer, the program enters a wait loop in which it repeatedly
tests the device status.
 During this period, the processor is not performing any useful computation.
 There are many situations where other tasks can be performed while waiting for an I/O
device to become ready.
 I/O device can alert the processor when it becomes ready by sending a hardware signal
called an interrupt request to the processor.
 Since the processor is no longer required to continuously test the status of I/O devices, it
can use the waiting period to perform other useful tasks.
 Indeed, by using interrupts, such waiting periods can ideally be eliminated.

Consider a program 1 that is currently being executed by processor, if the processor gets
interrupt request during execution of i th instruction. The processor first completes execution of
instruction ‘i’. The routine the processor executes in response to interrupt request is known as
‘interrupt service routine’ (DISPLAY routine in the given example). After execution of
interrupt service routine, the processor has to come back to instruction ‘i+1’

 Therefore, return address must be saved.

 Generally, the return address is saved on the processor stack or in a special register.

 The processor must inform the device that its request has been recognized so that it may
remove its interrupt request signal.
 A special control signal known as an ‘interrupt acknowledge signal ‘is used to inform
the device that its request is recognized.
Difference between Interrupt service routine and Subroutine.

Interrupt service routine Subroutine

Interrupt-service routine may not be related Performs a function required by the program
to the portion of the program being executed from which it is called, subroutine has
at the time the interrupt request is received. relation to the portion of the program being
executed

 Interrupt-service routine may not have anything in common with the program it
interrupts.
 Interrupt-service routine and the program that it interrupts may belong to different users.
 As a result, before branching to the interrupt-service routine, not only the PC, but other
information such as condition code flags, and processor registers used by both the
interrupted program and the interrupt service routine must be stored.
 This will enable the interrupted program to resume execution upon return from interrupt
service routine.

 Saving and restoring information can be done automatically by the processor or

explicitly by program instructions.
 Saving and restoring registers involves memory transfers:
 Increases the total execution time.
 Increases the delay between the time an interrupt request is received, and the
start of execution of the interrupt-service routine. This delay is called ‘interrupt
latency’.
 To reduce the interrupt latency, most processors save only the minimal amount of
information.
 This minimal amount of information includes Program Counter and processor status
registers.

Enabling and Disabling Interrupts

 The programmer must have complete control over the interrupts that take place during
program execution.
 The arrival of an interrupt request from an external device causes the processor to
suspend the execution of one program and start the execution of another.
 Since interrupts can arrive at any time, they may alter the sequence of events that are
designed by the programmer.
 Hence, the interruption of program execution must be carefully controlled.
 Therefore all computers must have an ability to enable and disable such interruptions as
desired.
 The processor should ignore interrupt requests in many situations.
 For instance, the timer circuit should raise interrupt requests only when the COMPUTE
routine is being executed. It should be prevented from doing so when some other task is
being performed.
 In another case, it may be necessary to guarantee that a particular sequence of
instructions is executed to the end without interruption because the interrupt-service
routine may change some of the data used by the instructions in question. For these
reasons, some means for enabling and disabling interrupts must be available to the
programmer.
 It is convenient to be able to enable and disable interrupts at both the processor and I/O
device ends.
  The processor can either accept or ignore interrupt requests.
 An I/O device can either be allowed to raise interrupt requests or prevented from doing
so.
 A commonly used mechanism to achieve this is to use some control bits in registers that
can be accessed by program instructions.
 The processor has a status register (PS), which contains information about its current
state of operation.
 Let one bit, IE, of this register, be assigned for enabling/disabling interrupts.
 Then, the programmer can set or clear IE to cause the desired action.
 When IE = 1, interrupt requests from I/O devices are accepted and serviced by the
processor.
 When IE = 0, the processor simply ignores all interrupt requests from I/O devices.
 The interface of an I/O device includes a control register that contains the information
that governs the mode of operation of the device.
 One bit in this register may be dedicated to interrupt control.
 The I/O device is allowed to raise interrupt requests only when this bit is set to 1.

Consider the specific case of a single interrupt request from one device. When a device activates
the interrupt-request signal, it keeps this signal activated until it learns that the processor has
accepted its request. This means that the interrupt-request signal will be active during execution
of the interrupt-service routine, perhaps until an instruction is reached that accesses the device
in question. It is essential to ensure that this active request signal does not lead to successive
interruptions, causing the system to enter an infinite loop from which it cannot recover. A good
choice is to have the processor automatically disable interrupts before starting the execution of
the interrupt-service routine. The processor saves the contents of the program counter and the
processor status register. After saving the contents of the PS register, with the IE bit equal to 1,
the processor clears the IE bit in the PS register, thus disabling further interrupts. Then, it begins
execution of the interrupt-service routine. When a Return-from interrupt instruction is executed,
the saved contents of the PS register are restored, setting the IE bit back to 1. Hence, interrupts
are again enabled.

Sequence of events involved in handling an interrupt request from a single device.

The device raises an interrupt request.

The processor interrupts the program currently being executed and saves the contents of
the PC and PS registers.
Interrupts are disabled by clearing the IE bit in the PS to 0.
The action requested by the interrupt is performed by the interrupt-service routine,
during which time the device is informed that its request has been recognized, and in
response, it deactivates the interrupt-request signal.
Upon completion of the interrupt-service routine, the saved contents of the PC and PS
registers are restored (enabling interrupts by setting the IE bit to 1), and execution of the
interrupted program is resumed.

Handling Multiple Devices

Generally, number of devices capable of initiating interrupts are connected to the processor.
Because these devices are operationally independent, there is no definite order in which they
will generate interrupts.
Now the processor must analyze the following issues

 How can the processor determine which device is requesting an interrupt?

 Given that different devices are likely to require different interrupt-service routines, how
can the processor obtain the starting address of the appropriate routine in each case?
 When the processor is executing an interrupt service routine for one device, can other
device interrupt the processor?
 If two interrupt requests are received simultaneously, then how processor handles the
interrupts?

 When an interrupt request is received, it is necessary to identify the particular device that
raised the request.
 Furthermore, if two devices raise interrupt requests at the same time, it must be possible
to break the tie and select one of the two requests for service.
 When the interrupt-service routine for the selected device has been completed, the
second request can be serviced.
 This interrupt information is available in the status register of the device requesting an
interrupt:
 The status register of each device has an IRQ bit which is set to 1 when it requests an
interrupt.
 The simplest way to identify the interrupting device is to have the interrupt-service
routine poll for all I/O devices in the system.
 The first device with IRQ equal to 1 is the one that is serviced.
 Polling mechanism is easy, but time-consuming to query the status bits of all the I/O
devices connected to the bus.

Vectored Interrupts
 Vectored Interrupts approach is used to reduce the time involved in the polling process.
 Any device requesting an interrupt may identify itself directly to the processor. Then,
the processor can immediately start executing the corresponding interrupt-service
routine.
 Device can do so by sending a special code (4 to 8 bits) to the processor over the bus.
 Code supplied by the device may represent a part of the starting address of the interrupt-
service routine.
 The commonly used scheme is to allocate permanently an area in the memory to hold
the addresses of interrupt services routines and these addresses are usually referred to as
vectored interrupts.

Interrupt Nesting
 The interrupts should be disabled during the execution of an interrupt-service routine, to
ensure that a request from one device will not cause more than one interruption.
 Similarly, when several devices are involved, interrupts should be disabled during the
execution of an interrupt-service routine, because the processor will accept an interrupt
request from a second device if it completes the interrupt request of first device.
 Interrupt-service routines are typically short, and the delay they may cause is acceptable
for most simple devices.
 For some devices, however, a long delay in responding to an interrupt request may lead
to erroneous operation. For example, a computer that keeps track of the time of day
using a real clock.
  Therefore, long delay in responding to real clock may result in erroneous time.
 Hence the processor has to accept an interrupt request from the clock during the execution
of an interrupt service routine for another device, i.e., to nest interrupts.
 An interrupt request from a high-priority device should be accepted while the processor is
servicing a request from a lower-priority device.
 I/O devices should be organized in a priority structure.
 The processor’s priority is encoded in a few bits of the processor status register.
 Priority can be changed by instructions that write into the processor status register.
 Usually, these are privileged instructions, or instructions that can be executed only in the
supervisor mode.
 Privileged instructions cannot be executed in the user mode.
 Prevents a user program from accidentally or intentionally changing the priority of the
processor.

INTR1 I NTRp
Proces
Device Device Devi p

INTA INT p

Prio

 Each device has a separate interrupt-request and interrupt-acknowledge line.

 Each interrupt-request line is assigned a different priority level.
 Interrupt requests received over these lines are sent to a priority arbitration circuit in the
processor.
 If the interrupt request has a higher priority level than the priority of the processor, then
the request is accepted.

Simultaneous Requests
Consider the problem of simultaneous arrivals of interrupt requests from two or more devices.
The processor must decide which request to service first. Polling the status registers of the I/O
devices is the simplest such mechanism. In this case, priority is determined by the order in which the
devices are polled. When vectored interrupts are used, we must ensure that only one device is
selected to send its interrupt vector code. This is done in hardware, by using arbitration circuits.
DIRECT MEMORY ACCESS
Data are transferred from an I/O device to the memory by first reading them from the I/O device
using an instruction such as
Move DATAIN,R2
which loads the data into a processor register. Then, the data read are stored into a memory location.
The reverse process takes place for transferring data from the memory to an I/O device. An
instruction to transfer input or output data is executed only after the processor determines that the
I/O device is ready, either by polling its status register or by waiting for an interrupt request. In
either case, considerable overhead is incurred, because several program instructions must be
executed involving many memory accesses for each data word transferred.

When transferring a block of data, instructions are needed to increment the memory address and
keep track of the word count. The use of interrupts involves operating system routines which incur
additional overhead to save and restore processor registers, the program counter, and other state
information.

 Blocks of data are often transferred between the main memory and I/O devices such as
disks.
 The technique for controlling such transfers without frequent, program-controlled
intervention by the processor is known as DMA.
 A special control unit is provided to manage the transfer, without continuous intervention by
the processor.
 The unit that controls DMA transfers is referred to as a DMA controller. It may be part of
the I/O device interface, or it may be a separate unit shared by a number of I/O devices.
 Although a DMA controller transfers data without intervention by the processor, its
operation must be under the control of a program executed by the processor, usually an
operating system routine.
 To initiate the transfer of a block of words, the processor sends to the DMA controller the
starting address, the number of words in the block, and the direction of the transfer.
 The DMA controller then proceeds to perform the requested operation. When the entire
block has been transferred, it informs the processor by raising an interrupt.
Figure shows an example of the DMA controller registers that are accessed by the processor to
initiate data transfer operations.
  Two registers are used for storing the starting address and the word count.
 The third register contains status and control flags.
 The R/W bit determines the direction of the transfer. When this bit is set to 1 by a program
instruction, the controller performs a Read operation, that is, it transfers data from the
memory to the I/O device.
 Otherwise, it performs a Write operation.
 Additional information is also transferred as may be required by the I/O device.
 When the controller completes transferring a block of data and is ready to receive another
command, it sets the Done flag to 1.
 Bit 30 is the Interrupt-enable flag, IE. When this flag is set to 1, it causes the controller to
raise an interrupt after it has completed transferring a block of data.
 Finally, the controller sets the IRQ bit to 1 when it has requested an interrupt.

Below figure shows how DMA controllers are used in a computer system
  DMA controller connects a high-speed Ethernet to the computer’s I/O bus (a PCI bus).
 The disk controller, which controls two disks, also has DMA capability and provides two
DMA channels.
 It can perform two independent DMA operations as if each disk had its own DMA
controller.
 The registers needed to store the memory address, the word count, and so on, are duplicated
so that one set can be used with each disk.
 To start a DMA transfer of a block of data from the main memory to one of the disks, OS
routine writes the address and word count information into the registers of disk controller.
 The DMA controller proceeds independently to implement the specified operation.
 When the transfer is completed, this fact is recorded in the status and control register of the
DMA channel by setting the Done bit.
 At the same time, if the IE bit is set, the controller sends an interrupt request to the processor
and sets the IRQ bit.
 The status register may also be used to record other information, such as whether the
transfer took place correctly or errors occurred.

Cycle Stealing
Requests by DMA devices for using the bus have higher priority than processor requests
Top priority is given to high-speed peripherals such as,
Disk
High-speed Network Interface
Graphics display device.
Since the processor originates most memory access cycles, the DMA controller can be said to
steal the memory cycles from the processor.
This technique is called Cycle stealing.

Burst Mode
The DMA controller may be given exclusive access to the main memory to transfer a block of data
without interruption. This is known as Burst/Block Mode

Bus Master
The device that is allowed to initiate data transfers on the bus at any given time is called the
Bus master.

Bus Arbitration
It is the process by which the next device to become the bus master is selected and the bus
mastership is transferred to it.
There are 2 approaches to bus arbitration. They are,
Centralized arbitration ( A single bus arbiter performs arbitration)
Distributed arbitration (all devices participate in the selection of next bus master).
Centralized Arbitration:
Here the processor is the bus master and it may grant bus mastership to one of its DMA controller.

A DMA controller indicates that it needs to become the bus master by activating the Bus
Request line (BR) which is an open drain line.
The signal on BR is the logical OR of the bus request from all devices connected to it.
When BR is activated, the processor activates the Bus Grant Signal (BGI) and indicates to
the DMA controller that they may use the bus when it becomes free.
This signal is connected to all devices using a daisy chain arrangement.
If DMA requests the bus, it blocks the propagation of Grant Signal to other devices and it
indicates to all devices that it is using the bus by activating open collector line, Bus Busy
(BBSY).
The timing diagram shows the sequence of events for the devices connected to the processor is
shown.
DMA controller 2 requests and acquires bus mastership and later releases the bus. During its tenure
as bus master, it may perform one or more data transfer.
After it releases the bus, the processor resources bus mastership

Distributed Arbitration:
It means that all devices waiting to use the bus have equal responsibility in carrying out
the arbitration process.

 Each device on the bus is assigned a 4 bit id.

 When one or more devices request the bus, they assert the Start-Arbitration signal & place
their 4 bit ID number on four open collector lines, ARB0 to ARB3.
 A winner is selected as a result of the interaction among the signals transmitted over these
lines. The net outcome is that the code on the four lines represents the request that has the
highest ID number. The drivers are of open collector type.
 Hence, if the i/p to one driver is equal to 1, the i/p to another driver connected to the same
bus line is equal to ”0‟(ie. bus the is in low-voltage state).