APPENDIX-

of which unity has the value

1. A binary number with n-digits all are

(6) 2 (c) 2 - 1 d ) 2"-1

(a) n-1 L

2. The 1's complement of a 4-bit number 1001 is

(6) 0110 (c) 1010 (d) 1000
(a) 1001
3. The 2's complement of 4 is
(c) 1011 (d) 1010
(a) 0100 b) 1100 f3 T)
4. The 2's complement of a -N is 1011, the value of +W is
(d) 0011
(a) 0100 (b) 0110 0101
5. BCD number is obtained by
(a) converting decimal number to binary

) each decimal number is represented by a 4-bit binary

(c)converting decimal to octal
(d)converting binary to decimal
6. The 2's complement of a 2's complement binary number is

(a) 1's complement of the binary number

(6) 2's complement of the binary number

e)original number
(d) None
7. Given binary number is 0000 0111, its 2's complement in hexadecimal förm is
(a) F8 (b) F9 (c) 07 )FO
8. Addition of 1111.01 and 0111.10 is
(a) 11110.11 (b) 10110.11 (c) 1011.11 (a) 1011.10
9. Pick out the code from the following which is not a self complementing code
(a) 2421 code 8 4 2 1 code (C) 6423 code (d) 3321 code
10. Gray code is
(a) Non-weighted code (b) cyclic code
(c) Reflected code all the above
A
11. In the Hamming code for each group of 'm"information digits, k-parity checking digits an
with condition.
(a) 22 = m (b) 2 = m +1 o) 2 2 m k++1 (d) 28 s m +k+1
12. In the Hamming code 1001101, error has occured in ... ..position

(a) 4 (b) 5 (c) 1 (a) 7

694
 695
A
in. .. base
true ****
100 = 1 0is
(b) 5 c) 6 L,d) 10
is
any number

ihex
valid (b) 8A.9B (c) 6G4.51
The
) TH.32
(d) 601
is not a valid octal number?
the following
Which o fthe

(b) 64.15 ) 82.3

(o) 732
(d) 11.11 1 1
46453 +
6453
= 7687, for this operation the possible bases are
1234
& (6)11 (c) 12 d) all
lo) 10

self-complementing
code among the following is
The
a ) 2422
(6) 3322 ()8421 ld) 5211
number 1s 1011, its equivalent binary number is
&Thegiven gray 011 111o
(6) 1000 (c) 1111 (d) 1011
) 1101

9's complement of 234 is

o) 234 (b) 765 3 (c) 766 (d) 432

Thelaw, x+ry .

(b) x + z +y (d) xy +Xz

(a) y+z
is the dual for x + xy = x
**************

x { x + v ) =x
a) y)=x (6) x(r+y)= )x(v)=
IS known as consensus theorem

AB+ AC+BC =AB+ AC (6) AB+AC=(4+C)(A +B)

) (4+B ( +C)= AC+ AB + = A+B

UsingDemorgan's theorem (x +y
Ab) xy (c)x+y (d) x+
Minterm is a
...i
Sum t uncomplemented
W h contains each variable as factors in either complemented or

form
product ferm which
which contains each variable as factors in either complemented or
n
uncomplemented formn
producf term
"which contains each variable in only complemented
form
product term which contains each variable in uncomplemented
ha n torm
main theo
tis being applied in the Karnaugh map simplitication is
Demorgan's theoremn
Demoroa
(6) Consensus theorem
Combitheorem
ning theorem Aa+ Aa =,A (d) None
 Digital Des
696
fixing the value of a minterm
26. In Karnaugh map * * * * * * * * * *
code is used for
(c) 642-3
(a) cyclic code
(a)Excess-3 (b) 2421
will be covered by more than one subcu-
27. In the minimization using K-map, sometimes one cell
this can be justified by... . law theoretically
(b) Distributive law
(a) Associative law
d Idempotent law
(c) Commutative law
=

ABC + ABCD + ABCDE . .

the expression A + AB +
28. Simplify (d) D
(b) B (e) C
(a)A
is equivalent to.
2, 3, 6)
************°******

29. The logic expression for Y(4,B,C) Em(0, =

(a) nm(1, 4, 5, 7) (6) TIm0, 2, 3, 6) (cHm(1, 4, 5, 7) (d) none

30. Write the product of sum expression

of (A, B,C) Enu(1, 2, 4)
=

3, 5, 6) (6) En(1, 2, 4) )n{0, 3, 5, 6, 7)() 432

(a) En0,
is
31. An example of canonical SOP
ABC + AB d ABC+ ABT
+ BC + AB (b) AB (c)
(a) ABC
32. The dual of the
function f =
xy+ yz is

(c) r+y-+z dy(r+)(y+=)

(a) (x)y +) (b) (x+y)()
statement is not correct
33. Which of the following A
zx+ zxy = zr +y
(b) x{x+)=* (c) xy+ xy
= x (d)
yX+Xy = x

34. The number of cells

in a 4-variable K-map is
(d) 3
(a) 4 16 (c)8
+ Xz +
=

35. Simplify xy yz * * * * * * *

(d) y +
(b) xz + yz (c) x
(a) xy t y
the minterm
the following code is used in K-map for representing
36. Which of (d) BCD
I Gray code () Excess-3 code
(a) 8421
.. number of cells in the K-map
function contain..
* *

37. Six variable

(b) 16 (c) 32 ) 64
(a) 8
the simplified equation is
38. If fw,x, y,2) Xm{1, 3, 5, 7)
=

(c) wz
(d) wz
A) wz
(b) wz

decimal position of the minterm ABCD in the K-map

39. What is the (ad) 14
()15
(a) 2 (60
dix-A 697
In a 4-variable K-map if we covered 8-adjacent cells as a group than the resultant term conta
.. number of variables
(a) 4 (b) 3 (c) 2
The following two equations are true as per Boolean arithmetic operations AB +B=1 a"
and
BC 0 , the value ofA is . . .***********
(a) 0 (c) 2 d ) don't care
For each cell, number of adjacent cells in a
4-variable K-map is
(a) 2 b) 4
)3 (d) 8
If f(4,B, CD) = 1 then the K-map contains. .. number of logic 1's

(a) 4 b) 8 165 (d) 32

The minterm corresponding to decimal number 13 is

(a) ABCD
by A+B+C+D B+C+D ABCD
The value of C is P
(a) 0 (b) 1 (c) 2 ddon't care
In a tabular method, the minimal expression of a function contains
(a) only prime implicants
(b) Prime implicants and essential prime implicants
(c) only essential prime implicants
(d) all variables
In a 4-variable K-map, the function contains all minterms then the minimal expression is

(a) A bT (c) 0 (d) dno't care

A function f(4,B,C) contains minterms 1, 2, 3, 6 and 7 its complement contains

(b) Em(1, 2, 3, 5, 6, 7)
(a) Em0, 4)
)Im1, 2, 3, 5, 6,7) Kd) TIm(0, 4, 5)

to
- Boolean expression (A+C\B +C) simplifies

(c) BC + AB (d) None

a)C+AB (b) C(A+ B)
to
.The Boolean expression AB + ABC simplifies
(c) C (d) None
(a) AC AB
by
given minterm is represented
. . . ******

each
*n K-map,
a
(c) don't care (l) None
(b) 0
 698
Digital
52. In a
K-map, given maxterm is represented by
(a) 1 6) 0 (c) don't care (d) None
53. The given maxterm is 4 + B+ C its equivalent binary is represented as
(a) 101 (6) O10 (e) 111 d000
54. The given minterm ABC in its equivalent binary represented i
(a) 101 (b) 010 a) 000
55. In the K-map,
of variables
iftwo cells are
said to be adjacent, they are differentiated by *********** IIU

(b) 2 (c) (d)n-1

56. Looping pair of adjacent 1's in
a a K-map eliminates.. number of variable
Ma) T (b) 2 )n (d) n - 1

57. In then-variables K-map, after looping a quad of adjacent 1's, the resultant term contains..
number of variables
(6) 2 (c)n- 1 Ldyn-2
58. 4-B= B.A is . law

(acommutative (6) associative (c) distributive (d) absorption

59. Union law states that
.
Ka x-1=1x=x 6) x{r +y)=x (c) ab c)=(a-b)c (d) x+++1
60. An identity element with respect to +, is designated by
(6) 1 (c)0 (d) None
61. The dual ofthe given function can be obtained by
changing + and. operation (6) complementing 0 and 1
()both d) None
62. If F= A(B+ C), then its dual is . B
la A + BC (6) AB + BC (c) ABC (d) AB
63. The function and its dual are same, the function is called as . . .
a) seBf dual (6) complement (c) same (a) inverse
64. The complement of minterm 4 is
lay maxterm 4 (b) minternm 0
(c) minterm 13 (d) maxterm 13
65. Which of the following is the non-standard form

(a) AB +(B+A) (b) (4+ B)(4+ B)

)(A+ B)(A+B) (d) AB + AB
66. The resultant of the function which cannot be further simplified is called ... *****"

(a) minimal (b) irredundant (c)either a or b (d) None

 699
endix-A

. ab = . .

(a) ab +ab (b) ab (c)ab+ab d) (a +6)(a + b)

S. (ab) =

(a) ab +ab Cb) (+b)(a +5) TDb (d) all

.A BO AB
=
.. .
(a) A BB (b) A® B (c) A® BB Ad)A+ BB

0. A A =.

(a) o (b) 1 (c) A

1. AO A =.

(a) 0 (b)1 (c) A (d) A

2. A 0 =. ADA=
(a) 0
AD OA
3. A®1 =.
(a) 0 (b) 1 (c) A ADA=
4. A AO AO... A = .. for even number of A's

(b) 1 (c) A (d) A

.... for odd number of A's
5. A® A®AO...A =.

(a) 0 (d) A
6. Which gate is suitable for bit comparison
(a) EX-OR gate (b) AND )Ex-NOR (a) NOR

If input A is given to an inverter, the output will be

I7. an

(a) A A (c)1
is
78. The sum expression in half adder

a ) x9y tb)(xFy)(F +) (c) (c+xy) (d) all

sublractor is same as
79. The difference bit output of a half
(a) difference bit of a full subtractor p) sum bit of a half adder
(d) carry bit of a half adder
(c)sum bit of a full adder
80. A full adder can be realized by
I w o hulf adders, one OR gate
(a) one half-adder, two OR gates
(d) one half adder, one OR gate
(c) two half adders, two OR gates
700
Digital Desig
81. The carry
expression for a full adder is
(a) xy+z ) xy +
yE +
x (c) xVz +X yz (cd) None
82. The number of full adders in a 4-bit parallel adder is
(u) one (b) two (c)four (cd) 16
83. In a look ahead carry adder, the carry of each stage (except initial stage) is a function of
(a) carry propagate (b) carry generate (both (d) none
84. TIhe .... . .. number of NAND gates are required to realize a half subtractor
t five (b) six (Yseven (cl) eight
85. Full subtractor can be realized by using
(a) one half-subtractor and one OR gate b)Awo half subtractors and one OR gate

(c) one half-subtractor and one AND gate (d) two half-subtractors and one AND gate
86. Magnitude comparator is a circuit that compares

e magnitude of two numbers (b) magnitude of three number

(c) magnitude of four numbers (a) sign of the two numbers
87. A decoder with 'n' inputs produces maximum of . ***
number of minterms

(b) 2" 1 (c) 2 - 1 (d) 21

88. Any Boolean function can be implemented if it can be represented in .. form

(b) POS canonical SOP (d) Canonical POS

(a) SOP
89. For economical realization, decoder is used to realize a function which contains...

(6) more number of don't cares

(Aess number of don't cares

(d) None
(c) for any case

90. A 4-to-64 decoder can be obtained by cascading . .

16 decoders and one 2 to 4 decoder

afour 4 to
(b) five 4 to 16 decoders
2-to-4 decoder
(c) three 4 to 16 decoders and two
(d) cannot be possible
(where m # n and 2" > 1m)
encoder is. .
91. The general representation of an
(b) m:2" (c) n : 2'" d) 2":
(a) 2": m

92. Multiplexer is represented by 2"

(c) n 2" (d) I x
(b) 2" n
2"1

93. MUX i s . . ***

... implementation
(d) NOR-AND
) OR-AND (c) NAND-OR
(a) AND-OR

is represented by ...
94. Demultiplexer (d1 x 2"
(b) 2" n 2"
(a) 2"1
 701
pendix-A
95. What is the nmber of inputs, outputs of'a decoder that accepts 64 different input coinbinato
(b)6 (d) 8
(a)5 (c) 64
96. Which of the following statements refer to decoder ?
(u) only one input can be activated at any time
(b) has more output than inputs
(e) can be used as BCD to 7 segment display interface
d a l l the above
97. Whiclh of the following statements belong to an encoder ?
(a) Has more inputs than outputs
(b)we can get the priority ofthe inputs
(c) only one input is considered at any time
)att
98. Which of the following statement belong to a MUX ?

(a)Aas more inputs than outputs (b) uses select inputs

(d) all
(c) parallel to serial conversion
used in
1 for ON and the output Y
99. If in the switching circuit, switches A, B have values of 0 for OFF,
is.
has 0 for 0 volts, 1 for 5 V than the expression for y

(6) A +B leA+B (d) None

(a) AB
0 and closed as 1, than the expression for the circuit, y is given by
100. For the circuit, taking open as

A BC + D ()A(BC +D) (d) None

(a) A + (B + C)D (b) +

statements are ade

101. For NAND gate, the following
followed by a NOT gate
It is equivalent to an AND gale
) low
to it are low, the output is
di) If all input
to it are high, the output is low
(i) lt all inputs
OR operation
is equivalent to
)NAND operation
are
of these, the only true statements

b (), (ii) (C) (i), (iv) (d) (i). (iv)

(a) (), (Gi)
 702
Digital D
102. The expression A(A + B) . *********'****

(a) A +B3 (6) A (c) B () AB

103. The number of Boolean
functions that can be generated by n-variables is equal to . .

(a) 2" (c) 21 (al)-2"

104. The Boolean expression AO BOA is equal to.

(a) AB+AB (6) AB+ AB C)B

105. The Boolean
expression AB+ AB + AB =
..f ..
A+B (6) AB (c) A+ B (d) AB
106, The minimum number
of NAND gates required to implement the function F=
(ï+)(E+
(a) 3 (6) 4 (c) 5 (d) 6
107. The operation which is commutative but not associative
(a) AND 6) OR (c) EX-OR )NAND
108. The dual function of ABC+ BC+ BC) is .

d+(B+C){B +C){B +C) (6) A+(BC+BC + BC)

(c) ABC + ABC+ ABC (d) A+ BC+ BC + BC
109. A sequential circuit is one, whose output depends on
(a) present inputs (6) present states both (d) none
110. The next state in sequential circuit is
a a
function of
(a) present inputs (6) present states (both
(d) none
111. The speed of the sequential circuits as compared to combinational circuit is
Aa) slow (b) tast (c) equal (d) none
112. Which of the following is an example of a sequential circuit
(a) parallel adder 6 ) serial adder (c) BCD adder ahead adder
(c) look
I13. Sequential circuits are classified in..
types
(a) three (b) four (c) five (d) two
114. The characteristic equation of RS tlip-tlop is
(a) S+ R (b) S+ RO ( S+ R ) SsQ+ R
115. The characteristio equation of D flip-tlop is

(b) D (c) DQ (d) DO

116. The next state of D flip-flop is

(same as input (6) complement of input

c) independent of input (d) none
ndix-A 703

While designing a divide by 2 circuit using D flip-flop, the D input is connected by

(a) b) (c) clock (d) none

The characteristic equation of JK flip-flop is

(a) JQ+K + Ro (c) Jo+ KO (d) JQ+ KQ

When both inputs of JK flip-flop are "0'" then the next state is

(a) 0 (b) 1 (c)Q) (d) )

When both inputs of JK flip-flop are "1", then the next state is

(a) 0 (6) 1 (c) O)

The characteristic equation of T flip-flop is

TO+To (b) TO+T (c) TO (d) TO

. When does the next state of the T flip-flop complement the present state (i.e. T value)
(a) 0 6) 1 (c)both (d) none

. In which flip-flops race around condition occurs?

o JK (b) T (c) both (d) none
How many number of flip-flops are used in master-slave flip-flop ?

(6) 3 (c)1 (d) 4

(2
What is the condition for race around problem ?
A <ip c t both (d) none
J= K =1
. Which of the following are asynchronous inputs?
(b) clear c)both (d) none
(a) preset
is not used ?
. In active low direct inputs, which of the conditions
(b) Preset = 0, clear = 1
V)Preset clear 0 = =

(d) Preset = clear = 1

(c) Preset =1, clear
=
0

While converting the SR flip-flop into D flip-flop, the SR inputs are

3.
(6) S=D, R=D (c) S= R= D (d) S= R = D
S = D, R=D
JK flip-flop, the SR inputs are
9. While converting the SR flip-flop into
S R =
K S = JQ, R= QK (d) S= QK, R= JO5
(b)
=

(a) S R =J
=
0, then the values of R and S are
. If the present state =
0, next state
(b) 1, 0
(c) 0, T d ) x, 0
a) 0,0 state and next state a r a
then tne present
. If the values of R and S are 0, I respectively are
(e) 0, 1 (d) 1, 0
(b) 0, 0
(a) 1,1
 704

132. The table which contains present state, next state and 1lip-flop inputs is called
(a) truth table (b) characteristic table
excitation table d) realization table
133. In JK flip-flop. under what condition does 0 to I transition occur
(a) J= K = 1 (b) J = K = 0
(c) J =X,K =

0 J- 1, K -X
134. If J=X and: K = I what are the present state and next state ?
(a) 0, 1 Ab) 1. 0 (c) 0, 0 (d) 1. 1
135. If the next state is 1, then the D input is
(a) 0 Ab) 1 (c) X (d) None
136. In T flip-flop. both states are same., then the T value is
(b) 1 (c) X (d) Nonee
137. Shifting a binary data right by bit shift
to one position using right register, results is
(a) addition by 2 (b) subtraction of 2
(e) multiplication by 2 (d division by 2
138. A counter with 6 flip-flops can have the maximum number of states as
(a) 6
*256 (64 (d) 8
139. The maximum number of flip-flops required for a MOD-10 counter is
(a) 10 (6)4 (c) 3 (d) 5
140: The maximum count value that can be obtained by a counter which is binary 5 flip-ilop 1
(a) 32 (6) 3 (c) 5 (d) None
141. The maximum modulè number that can be obtained by a
ripple counter using 4-tlip-10p%
(b) 4 (c) 32 (d) 15
142. A MOD-6
synchronous counter is designed by using JK flip-flop, the number of counter
by it is sP
(a) 6 (b) 5 (c)3 (d) 2
143. The number of flip-flops required for a MOD-16 ripple counter are..
a) 2 b) 4
() 15 (d) 16
144. A BCD counter has .... different states
(a) 3 (6) 4 c ) 10 (d) 9
145. The counter frequency of decade counter, when it is divided by 100 kHz
a ) 10 kHz 6) 50 kHz
signal is
(c) 25 kHz (a) I kHz
146. The output frequency of a MOD-16
counter, clocked by a 10 kHz clock
(a) 2.5 klHz (6) 6.25 kHz
signal is
(c) 6.25 kHz () 10 kHz
147. Which type of counter
requires more number of flip-flops for a given MOD number
(u) ripple counter (fing counter
(c) Johnson counter () BCD counter
ndix-A 705
The maximum frequency to which a MOD-16 ripple counter using 4 JK flip-flop With
propagation delay of 50 n sec is
(a) 4 MHz (b) 3.2 MHz (c) 50 MHz ( 5 MHz
A sequential circuit with 3 numbers
of inputs produces an input alphabet containing.
number of input sets
(a) 3 (6) 2 (d) 8
The next state of a Mealy machine is a function of
(a) present state (6) present inputs both (d) None
The Mealy circuit output depends
(a) only on the present state of the flip-flop
6) only on the next state of the flip-flop
o n both present state and next state of the flip-flop
(d) none
The Moore circuit output depends
o n l y on the present state of the flip-flop
(6) only on the next state of the flip-flop
(c) on both present state and next state of the flip-flop

(d) none
Minimization ofthe number of state reduce the
(a)complexity (b) gates () Lost
number of d all
Iftwo states A and B ofa machine M are distinguishable, then they are distinguishable by a
sequence of . . .. length, (assume n is number of states in the machine)
. . .

(b) n or less (c)n*1 (d) does not depend on 'n'

n-1) or less
The state reduction process in the incompletely.specified machines can be done by. . .
table eboth (d) not possible
(a) Merger graph (b) Merger
The Schottky diode is a
(b) PN junction
(a) MOS device
(d) vacuum device
Metal semiconductor junction
The switching speed of Schottky diode
diode
(a) is lower than that of a PN junction
junction diode
6) is same as that of PN
diode
i s higher than that of PN junction
a)may be lower or higher than that of a PN junction diode
as a switch, switches between
A
Schottky transistor when used
)cutoff and active region
(a) cutoff and saturation region
(d different operating points in the active region
(C) active artlusaturation region
706
Digital De-
159. Schottky transistors are preferred over normal transistors in digital circuits because of the=
alower propagation O (b) higher propagation delay
(c) lower power dissipation (4) higher power dissipation
160. Higher switching speed is possible in Schottky transistor Over normal transistor because
(a)the transistor operates in cut-off and saturation regions
(6) the transistor operates in active and saturation
regions
t h e transistor is prevented from entering into saturation
(d) the transistor is not allowed to go to cut off
161. RTL circuit consists of
(a) diodes and resistors
b)bipoles junction transistor and resistor
(c) JFET and resistors (d) MOS devices and resistors
162. The logic family which has minimum power dissipation is
(a) TTL (6) PL (c)ECL CMOSs
163. The logic family with highest noise margins is
(a) 1L HTL (c) TTL (d) CMOS
164. DCTL is not used because

(a) of large power requirements (6) of high noise margin

o f the problem of current hogging (a) of none of the above
165. The logic family suitable for making LSI is
(a) TTL (b) HTL
166. The
(cL (d) RTL
speed at wlhich Schottky TTL can
operate is
(a) lower than that of standard TTL
(6) higher than that of standard
(c) same as that of slandard TTIL
() is lower than or equal to that of standardTt
167. 11L is modified version off
(u) RIL (b) DTL (c) TTL ()DCTL
168. ECL is
(a) a saturated bipolar logic Ab) a non-saturated bipolar loge
(c) a unipolar logic
(d) none of the above
169. The switching speed of ECL is very
high because
(a) the transistors switched between cut-off
are
and saturation region
(b) the transistor are switched between active
and saturation
)the transistorS are switched between
regions
cut-off and active region
(d) the transistors may operate in any of the
three regions
170. For 1L, the logic levels
corresponding 0 and l respectively
to
(a) 0 and 5 V (b) 0.2 and 5 V
C0.2 and 0.8 V (d) 0.8 and 5 V
pendix-A 707
1. PL consists basically of
(a) normal bipolar junction transistors
(b) multiple collector transistors
multiple emitter transistor (d) one multiple emitter and some normal transistors
2. Wired logic is not possible in
(a) ECL
T T L with active pull-up
()open collector TTL (d) TTL with passive pull-up
13. The TTL logic family with minimum. value of figure of merit is
(a) Schottky TTL ( low power TTL
(c) high power TTL ) l o w power Schottky TTL
74. ECL have higher fan-out because of their
(a) high input impedance (b) low output impedance
b o t h (a) and (6) a) complementary output
75. For the circuit shown in Fig. Q175, the output Y is given by
A

B
Y

C
D-

Fig. Q175
(c) AB CD d ) A + B+C+ DD
(a) (A B) (C + D) (6) AB + CD
+

76. Tristate logic has

and 1 three output states: 0, I and high-impedance
(a) only two output states 0
(d) logic-1 output when tristated
(c) logic-0 output when tristated
77. Tristate logic is used for
merit (b) increasing the fanout
(a) improving the figure of
() improving the speed of operation
) b u s oriented systems

78. MOS logic circuit consists of

(b) MOS devices and resistors
only MOS devices
(d) MOS and bipolar devices
MOS devices and diodes
(c)
79. CMOS consists of
logic
MOS devices (b) only p-channel devices
(a)onlyn-channel p-channel and n-channel MOS devices
(c) MOS devices and capacitors
where electric noise level is hi
industrial environment
for h
80. The logic family best suited ( ) MOS (d) ECL
(6) TTL
)HTL MSI digital ICs is
family for SSI and
81
T h e most popular logic TTL (d) DTL
(6) NMOS
(a) 1PL
 708 Digital De-

182. Schottky TTL is a ECL

non-saturated bipolar logic (6) saturated bipolar logic
)current source logic (d) high threshold logic
183. HTL is a modified form of
(a) CMOSS (6) NMOS c)TTL ua DTL
184. The output of two RTL gates are connected together as shown in Fig. Q184. The log
expression Y will be

A
B-

C
D-

Fig. Q184
(a) A+B+C+D A+B+C+D
(e) (4+ B)-(C+D) (d) AB +CD
185. A flip-flop has two outputs which are
(a) always zero (b) always one
always complementary (d) in one of the above status
186. The basic
memory element in a digital circuit
(a) consist of NAND gate
(b) consists of NOR gate
i s a flip-flop
187. A
d) is a shift register
flip-flop is used to store
o n e bit of information
(b) two bits of
information
(c) one nibble of information
188. In
(d) one
byte of information
an SR flip-flop, the S-R inputs must not be
Jay S =
R =
1 (6) S= R = 0
(c) S= 0, R = 1
189. When (d) S= 1, R = 0
a
flip-flop is set, its
output will be
(a)=0, =0 br Q=1, =0
190. When
flip-flop is reset, its
a ()Q=0, =1 (d) O=1, Q=1
output will be
(a) Q=0, =0 6) Q=1, Q=0
191. In a JK =0, =1 ( 0=1,
(d) Q=1, =1
flip-flop, when J= K =1 and clock is 0=1
(a) not change
(b) become 0
applied the output Q will
kd) be complement of the output before the (c) become1
clock was
applied
ppendix-A
709
192. Race around condition occurs
in JK
(a) both the inputs are 0
a
flip-flop when
bboth inputs are 1
(c) the inputs are
complementary
(d) any one of the above
input combinations is present
193. Master-slave configuration is used in flip-flops to
(a) increase its clocking rate (6) reduce power dissipation
eliminate race around condition (d) improve its reliability
94. The output Q, of a JK flip-flop is 1. It changes to 0 when a clock pulse is applied. The input
J and K are respectively
(a) 0 andX (6) 1 andX e X and 1
(d)Xand 0
95. The output Q, of an SR flip-flop is 1. It changes to 0 when a clock pulse is applied. The inputs
S and R are respectively.

(a) Xand1 0 and 1 () X and 0 (d) 0 and X

96. The output 2, of a JK flip-flop is 0. It changes to 1 when a clock pulse is applied. The inputs
J and K are respectively.
1 and X (b) 0 and X (c) Xand 0 (d) X and1
97. Flip-flops can be used to make
)latches (6)bounce elimination switches
dall of the above
e ) registers
98. In a counter consisting of four JK flip-flops, all get triggered simultaneously. This counter circuit

combinational circuit (b) is an asynchronous circuit

(a) is a
(d) may be combinational or sequent al circuit
is a synchronous circuit
99. A universal register
(a) accept serial input (b) accept parallel input
(c) gives serial and parallel outputs i s outputs of all of the above
will have
00. A ring counter consisting of five flip-flops
(b) 10 states 32 states (d) intinite states
go 5 states
counter consisting of six flip-flops will have
01. A twisted-ring (Johnson)
b ) 12 states
6 4 states (d) 124 states
(a) 6 states
decade counter is
02. The number of states in a
) 10 (al) 16
(a) 4 (b) 8
clock pulse
counter, for every input
In a 4-bit binary ripple
U5. clocked simultaneously
(a) all the flip-flops get
clocked at a time
one flip-flop get
(6) only
clocked at a time
the flip-flops get
C)two of false
statements are
a l l the above
710
Digital Desigr
time of 25 ns each. The maximun
204. A 4-bit ripple counter uses flip-flops with propagation delay
will be
possible time required for change of state (d) 100 ns
(6) 50 ns (c) 75 ns
(a) 25 ns
delay time of 25 ns each. The
205. A 4-bit synclhronous counter uses flip-flops with propagation
will be
maximum possible time required for change of
state

(c) 75 ns (d) 100 ns

a25 ns (b) 50 ns
ripple counter consisting of four flip-flops is
206. The maximum possible number of states in a

(6) 8 (c) 10 16
(a) 4
decade counter is
207. The maximum number of flip-flops required for a synchronous
(l) 8
(a)1 (b) 2 e4
circuit is
208. The minimum number of flip-flops required for a divide-by-12
(c) 12 (d) 16
4 (6) 8
by MOD-5 counter is
209. The MOD-2 counter followed a

MOD-5 counter followed by a MOD-2 counter

(a) same as a

a decade counter

(c) a MOD-7 counter

(d) none of the above

100 us can be obtained from square wave of time perioo
210. Symmetrical square wave of time period
10 us by using
(a) divide-by-5 circuit
(b) BCD counter

edivide-by-5 circuit
followed by a divide-by-2 circuit

(d) 4-bit binary counter as soor

counter has preset input 0101. The presetting operation takes place
211. A 4-bit presettable up
counter is of this
as the counter becomes maximum i.e. 1111. The modulus
(b) 10 (c) 11 (d) 15
(a) 5
circuit consists of
212. In general, a sequential logic
(a) only flip-flops
(b) only gates
combinational logic circuits
flip-flops and
circuits
(d) only combinational logic
213. The design of a clocked sequential circuit requires
(b) the state assignment
(a) the state reduction
state decoder a) all of the above
(c) the design of next
214. Semiconductor
memories are widely used because of
(b) their low cost
their small size
(a)
(c) their compatibility a l l of the above
bendix-A
711
5. A memory of size M * N bits can store
(a) N words of M-bits each AddresS m
(c) M bits )Mwords of N-bits each
(d) N bits
6. The address bus width of a
memory of size 1024 x 8 bits is xD(D ata Liu
(a) 8-bit 10-bit (c) 12-bits (d) 16-bits
7. The data bus width of a
memory size 2048 x 8 bits is
(6) 10 (c) 12 (d) 16
8. The memory has 16-bit
address, the number of locations in this memory are
(a)16 (b) 32 (c) 1024
9. It is desired to have a 64 x 8 65536
memory. The menories available are of 16 x 4 size. The number
of memories required will be

8 (b) 6 (c) 4 (d) 2

:0. A RAM is
a ) a random access memory (b) a volatile memory
(c) either static or dynamic memory (d) has all of the above characteristics
:1. A static RAM is fabricated using
aonly the bipolar technology (b) only the MOS technology
) either bipolar or MOS technology (d) none of the above
2. A dynamic RAM can be fabricated using
MOS technology (6) TTL
:3. A read only memory
(c) ECL (d) PL

(a) Is a random access type (6) is non-volatile

)is programmable (dhas all of the above characteristics
4. A PROM
(ais mask programmed (b) is erasable by ultraviolet radiation
Ke)can be programmed (d) can be programmed any number of times
5. An EPROM is
(a) non-erasable (b) volatile
)programmable and erasable (d) erasable and not
programmable
for making MOS
0. Floating gate is fabricated
(a) ROM (b) PROM CEPROM (d) EAPROM
the power supply of a ROM is switched ofl, its contents
When
(a) become all zeros (b) become all ones
(d) are unpredictable
remain intact
28. A PLA is
mask programmable
tb) field programmable
(C)can be programmed by a users only once

a)can be erased and programned

712
Digital Desi
229. The capacity of a PLA is specified in terms of
(a) number of inputs only (b) number of outputs only
(C)number of inputs and outputs only number of inputs, product terms and output"
230. A PLA is
a LSI device (b) a MSI device (c) a SSI device (d) a discrete device
231. A PLA consists of

(a) AND matrix (6) OR matrix

(c) invert/non-invert matrix a l l of the above
232. Read and write memory (RAM) is same as

aRAM (6) ROM (c) PROM d) EPROM

233. A PLA can be usedd
o to realize combinational logic (b) to realize sequential logic
(C) as a dynamic memory (d) as a microprocessor
234. The minimum number of resistors required in a 4-bit DA network of weighted register type i
a 4 (6)8 (c) 15 (a) 16
235. In a 4-bit weighted resistor DAC, the resistor value corresponding to MSB is 2 k2. The registe
value corresponding to LSB will be
(a) 1 k2 (b) 2 k2 (c) 4 k2
)16 k
236. In an R-2R ladder DAC, the input resistance is
(a) not same for all digital inputs (6) R for each input
(c) 2R for each input )3R for each input
237. The resolution of a DAC converter is approximately 0.4% of its full scale range is
( a n 8-bit converter (6) an 10-bit converter
(c) a 12-bit converter (d) a 16-bit converter
238. The speed of conversion is maximum in
(a) successive approximation ADC Parallel comparator ADC
(c) counter ramp ADC () Dual slop ADC
239. For a l12-bit ADC the range ofinput signal is O to +10 V. The voltage corresponding to 1L

will be
(a) 0 (b) 0.0012 V (c) 0.0024 V ( ) 0.833 V

240. An A/D converter

(a) consists of only a DAC with ingputs and outputs interchanged
(b) consists of a DAC along with same other components

(c) never contains a DAC

other components
may consist of DAC along with
some
(d)