Dr. N.G.P.

INSTITUTE OF TECHNOLOGY
Approved by AICTE-New Delhi & Affiliated to Anna University, Chennai
Recognized by UGC & Accredited by NAAC with A+ Grade & NBA (BME, CSE, ECE, EEE & MECH)
Dr.N.G.P Nagar, Kalapa , Coimbatore – 641048.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

22UEC504- MICROCONTROLLERS AND ARM PROCESSORS
Internal Test – 1 Answer Key
PART – A
1. List the hardware interrupts of 8086. CO1/K1
Ans: INTR and NMI are called hardware interrupts. INTR is mask able & NMI is non-mask
able. INTR interrupts (Type 0-255) can be used to interrupt a program execu on. This
interrupt is implemented by using two pins: INTR and INTA. This interrupt can be enabled
or disabled by disabled by STI (IF=1) or CLI (IF=0) respec vely.
2. Name the general-purpose registers in 8086. CO1/K1
Ans: General-purpose registers:
 The registers AX, BX, CX and DX are the general purpose 16-bit registers.
 AX is used as 16-bit accumulator. The lower 8-bit is designated as AL and higher
8-bit is designated as AH. AL can be used as an 8-bit accumulator for 8-bit
opera on.
 All data register can be used as either 16 bit or 8 bit. BX is a 16 bit register, but
BL indicates the lower 8-bit of BX and BH indicates the higher 8-bit of BX.
 The register CX is used default counter in case of string and loop instruc ons.
 The register BX is used as offset storage for forming physical address in case of
certain addressing modes.
 DX register is a general-purpose register which may be used as an implicit
operand or des na on in case of a few instruc ons.

3. Illustrate the 8086-flag register format. CO1/K2

Ans:

4. If the execu on unit generate an effec ve address of 43A2H and the DS CO1/K2
register contains 4000H, find the physical address generate by the BIU.
Ans:
 EA=43A2H, DS=4000H
BA=(DS)*10
MA (Physical Address) =BA+EA BA=4000x10-40000 MA=40000+43A2
MA=443A2H

5. State the size of the memory systems used in 8051. CO2/K1

Ans:
 4KB of ROM memory-Program memory
 128 Bytes of RAM-data memory
 64 Kbytes address space available for program memory
 64 Kbytes address space available for data memory

6. Illustrate the format of PSW of 8051. CO2/K2

Ans:
Program Status Word: The PSW keeps the current status of the arithme c and logical
opera ons, in different bits,
 8051 has 4 math flags that respond automa cally to the outcomes of arithme c
and logical opera ons and 3 general purpose user flags that can be set 1 (or)
cleared to 0 by the programmer as desired.
 The math flags are carry (c), Auxiliary Carry (AC), Overflow (OV), and parity (p).
 User flags are named flag 0 (FO), Register bank select bets RSO and RS1.

7. List the func ons supported by the special func on register of 8051. CO2/K1
Ans: The 8051 opera ons that do not use the internal 128 bytes RAM address from 00H
to &7FH are done by a group of special internal register, SFR (special func on register)
which may be addressed like internal RAM.
 Accumulator
 B Register
 Program Status Word.
 Stack Pointer.
 Data Pointer.
 Port (0 – 3)
 Interrupt priority control register.
 Interrupt enable control register.
8. Illustrate the PIN diagram of 8051. CO2/K2
Ans:

9. What is the primary goal of RISC architecture? CO3/K1

Ans: The primary goal of RISC architecture is to simplify instruc ons to achieve higher
performance by execu ng instruc ons in a single clock cycle.

10. Outline the significance of the thumb instruc on set in ARM architecture. CO3/K1
Ans: The Thumb instruc on set provides a more compact code representa on, reducing
memory usage while maintaining performance, especially in systems with limited
resources.

PART-B
11.a Explain the architecture of the 8086 microprocessors, highligh ng the CO1/K2
role and func on of each major block.
Ans:
 It has 2 processing unit 1) Bus interface unit (BIU)
2) Execu on unit (EU)
 BIU and EU functions independently.
 BIU fetches instructions, read data from memory and ports, & writes data to
memory and
 I/O ports.
 Execution unit receives program instruction codes and data from BIU, executes
these
 instructions and shores the results either in general purpose register or in BIU
unit.
 EU has no connections to the system buses. It receives and outputs all its data
from BIU.
BIU contains 1) Segment registers
2) Instruc on pointer
3) Instruc on queue.
EU contains 1) ALU
2) Index register
3) Pointer
4) Flag register
5) General purpose registers
Explain each block in BIU & EU

11.b (i). Explain the various types of addressing modes in 8086 with examples. CO1/K2
Ans: Addressing Modes: An addressing mode is the way of iden fies the operand for
an instruc ons. The memory address of an operand consists of 2 components.
1. Star ng address of the memory segment.
2. Offset (or) Effec ve address.
Displacement: 8 bit / 16 bit immediate value.
Base: It is the content of the base register BX/BP.
Index: It is the content of the index register SI/DI.
Memory address (MA) = star ng address of memory segment offset.
The 8086 has 12 addressing modes.
 Register
 Immediate
 Direct
 Register indirect
 Based
 Indexed
 Based indexed
 String
 Direct I/O port
 Indirect I/O port
 Relative
 Implied
Explain the each addressing modes with examples.
 (ii). Interpret the performance of mul plica on and division opera ons in CO2/K2
8086 microprocessors with examples.
Mul plica on opera on:
ORG 1000H
MOV AX, 4444H
MOV BX, 4444H
MUL BX
MOV SI, 1200H
MOV [SI], DX
MOV SI, 1202H
MOV [SI], AX
MOV AH, 4CH
INT 21H
CODE ENDS
END

Division opera on:

ORG 1000H
MOV DX, 0000H
MOV AX, 8888H
MOV CX, 4444H
DIV CX
MOV SI, 1200H
MOV [SI], AX
MOV SI, 1202H
MOV [SI], DX
MOV AH, 4CH
INT 21H
CODE ENDS
END
12.a Illustrate the architecture of the 8051 microcontroller, highligh ng the CO2/K2
func ons of each block.
Ans:
 It is an 8-bit microcontroller.
 Single-supply +5 volt operation using HMOS technology.
 4096 bytes program memory on-chip (ROM).
 128 bytes data memory on-chip (RAM).
 Four register banks namely Bank0, Bank1, Bank2, Bank3.
 It has 32 general purpose registers each of 8-bit, 16 bytes of bit
 addressable RAM locations and 80bytes of general-purpose data memory or
scratch pad.
 It supports 64 Kilobytes of separate program memory (ROM) and data memory
(RAM).
 8-bit bidirectional data bus and 16-bit unidirectional address bus.
 on-chip clock oscillator.
 It has four 8 bit ports namely port 0, port1, port2 and port3.
  Three internal and two external Interrupts.
 It has two16bit timer/counters.
 It has full duplex UART.

Explain each block in the architecture

 SFR- Special Func on Registers:

12.b (i).Write an assembly language program for the 8051 microcontroller to CO2/K2
interface an LED and control its blinking rate using mers.
Ans:
ORG 0000H ; Set the origin of the program to address 0000H
SJMP MAIN ; Jump to main program

ORG 000BH ; Interrupt Vector Table for Timer 0 Overflow Interrupt

MAIN: ; Main program starts here
MOV TMOD, #01H ; Set Timer 0 in Mode 1 (16-bit mer)
AGAIN: ; Main loop to toggle LED
MOV TL0, #0F0H ; Load lower byte of Timer 0
MOV TH0, #0BH ; Load higher byte of Timer 0
SETB TR0 ; Start Timer 0
HERE: JNB TF0, HERE ; Wait un l Timer 0 overflows (TF0 = 1)
CLR TR0 ; Stop Timer 0
CLR TF0 ; Clear Timer 0 overflow flag (TF0)
CPL P1.0 ; Toggle LED connected to P1.0
SJMP AGAIN ; Repeat the process

END ; End of the program

Explana on:
 ORG 0000H: The origin directive is used to set the starting address of
the program. We jump to the main program at address 0000H using
SJMP MAIN.
 MOV TMOD, #01H: The TMOD register is configured to set Timer 0 in
Mode 1 (16-bit timer).
 MOV TL0, #0F0H and MOV TH0, #0BH: These instructions load the
lower byte (TL0) and higher byte (TH0) of Timer 0 to create a delay.
 SETB TR0: This starts Timer 0 by setting the TR0 (Timer Run Control
for Timer 0) bit.
 JNB TF0, HERE: This is a loop that waits for the Timer 0 overflow flag
(TF0) to be set, indicating that the timer has counted to the desired
value.
 CLR TR0 and CLR TF0: The timer is stopped, and the overflow flag is
cleared.
 CPL P1.0: The CPL instruction toggles the bit on pin P1.0 where the
LED is connected.
 SJMP AGAIN: The program jumps back to the AGAIN label to
continue blinking the LED.

(ii). Describe the role of the special func on registers (SFR’s) in the 8051 CO2/K2
microcontroller, give examples of commonly used SFR’s.
Ans:
In the 8051 microcontroller, Special Func on Registers (SFRs) are a set of
dedicated memory loca ons used to control various func ons of the
microcontroller. These registers are located in the upper 128 bytes of the
internal RAM, and they allow programmers to configure and control
peripheral devices such as mers, I/O ports, serial communica on, and
interrupt handling.
Role of SFRs in 8051:
1. Hardware Control: SFRs are responsible for controlling the hardware
features of the microcontroller, such as mers, serial ports, and
interrupts. They provide a direct interface for configuring the
hardware components.
2. Peripheral Access: SFRs allow access to the I/O ports (P0, P1, P2, and
P3) and peripherals like UART, mers, and counters. They make it
easier for the programmer to manage and interact with these
components.
3. System Configura on: SFRs configure system se ngs like clock
frequency, power modes, and interrupt priority.
4. Status Monitoring: SFRs help in monitoring the status of various
hardware components such as mers (overflow flag), serial
communica on (data ready, transmission complete), and interrupts.
Commonly Used SFRs in 8051:
1. Accumulator (ACC) - Address: E0H
o It is used for arithme c and logic opera ons. Most of the
instruc ons in the 8051 work with the accumulator.
2. B Register - Address: F0H
o The B register is primarily used during mul plica on and
division opera ons.
3. Program Status Word (PSW) - Address: D0H
o The PSW contains status flags like the carry flag (CY), auxiliary
carry flag (AC), parity flag (P), overflow flag (OV), and others.
These flags are used to indicate the results of arithme c
opera ons.
4. Stack Pointer (SP) - Address: 81H
o The Stack Pointer holds the address of the top of the stack in
internal RAM. It is automa cally incremented or decremented
when data is pushed to or popped from the stack.
5. Data Pointer (DPTR) - Address: 82H/83H
o The DPTR is a 16-bit register used for poin ng to data in external
memory. It is o en used in instruc ons like MOVX and MOVC
to access external data memory or code memory.
6. Timer Control Register (TCON) - Address: 88H
o The TCON register controls the opera on of the mers and
external interrupts. For example, it holds the TF0 (Timer 0
 overflow flag), TR0 (Timer 0 run control), IE0 (External Interrupt
0 flag), etc.
o Example bits:
 TF0 (Timer 0 overflow flag)
 TR0 (Timer 0 run control bit)
7. Timer Mode Register (TMOD) - Address: 89H
o TMOD sets the mode of opera on for mers 0 and 1. It defines
the mer's mode (Mode 0, 1, 2, or 3) and whether it operates
as a mer or counter.
8. Serial Control Register (SCON) - Address: 98H
o The SCON register controls the serial port. It contains flags for
transmission, recep on, and mode selec on for serial
communica on.
o Example bits:
 TI (Transmit Interrupt Flag)
 RI (Receive Interrupt Flag)
9. Interrupt Enable Register (IE) - Address: A8H
o The IE register enables or disables interrupts. Each bit
corresponds to a specific interrupt source such as mers, serial
port, and external interrupts.
o Example bits:
 EX0 (External Interrupt 0 enable)
 ET0 (Timer 0 interrupt enable)
10.Port Registers (P0, P1, P2, P3) - Addresses: 80H, 90H, A0H, B0H
o These registers correspond to the four I/O ports of the 8051.
They control the data sent to or received from the I/O pins.
o Example:
 P1 (Address: 90H): Used to read from or write to Port 1
pins.
11.Power Control Register (PCON) - Address: 87H
o The PCON register controls power management features, such
as se ng the microcontroller in idle or power-down mode.
 Timer Configura on Example:
MOV TMOD, #01H ; Set Timer 0 in Mode 1 (16-bit Timer)
MOV TL0, #0F0H ; Load lower byte of Timer 0
MOV TH0, #0BH ; Load higher byte of Timer 0
SETB TR0 ; Start Timer 0 by se ng TR0 in TCON
Port Control Example:
SETB P1.0 ; Set P1.0 to logic HIGH (turn on an LED connected to P1.0)
CLR P1.0 ; Clear P1.0 to logic LOW (turn off the LED)

SFRs play a crucial role in configuring, controlling, and monitoring the

hardware components of the 8051 microcontroller, making it easier to
interface with peripherals and manage system-level opera ons.

PART – C
13.a Explain the ARM architecture, focusing on the RISC design philosophy and CO3/K2
differen ate the ARM from tradi onal CISC processors.
Ans:
ARM Architecture Overview:
The ARM (Advanced RISC Machine) architecture is a family of Reduced
Instruc on Set Compu ng (RISC) architectures designed for high
performance and power efficiency. ARM processors are widely used in
embedded systems, mobile devices, and increasingly in servers due to their
scalable performance and energy efficiency.
RISC Design Philosophy:
RISC (Reduced Instruc on Set Compu ng) is a design philosophy aimed at
simplifying the instruc on set of a processor to increase efficiency. In
contrast to CISC (Complex Instruc on Set Compu ng), which focuses on
minimizing the number of instruc ons per program (even at the cost of
complex instruc ons), RISC aims to streamline processing by using simple
instruc ons that can execute in a single clock cycle.
The RISC design principles followed by ARM processors are:
1. Simplified Instruc on Set:
o ARM processors use a smaller set of instruc ons compared to
CISC processors. These instruc ons are simple and are designed
to execute within a single clock cycle. This reduces the
complexity of decoding instruc ons, speeding up execu on.
2. Uniform Instruc on Length:
o All ARM instruc ons are 32 bits long (except for the Thumb
instruc on set, which is 16 bits). This uniformity simplifies
instruc on decoding and fetch processes.
3. Load/Store Architecture:
o ARM uses a load/store architecture, meaning data is loaded into
registers from memory before it is manipulated, and results are
stored back into memory later. In contrast, CISC architectures
may perform opera ons directly on memory.
4. Fixed Instruc on Execu on Time:
o Each ARM instruc on executes in a fixed amount of me
(typically one clock cycle), leading to predictable performance
and simpler pipelining.
5. Efficient Use of Registers:
o ARM processors have a large number of general-purpose
registers. Using registers reduces the number of memory
accesses, which are typically slower.
6. Pipelining:
o ARM architectures use pipelining, which allows mul ple
instruc ons to be processed simultaneously at different stages
(fetch, decode, execute). This improves overall throughput and
efficiency.
7. Condi onal Execu on:
 o ARM has extensive support for condi onal execu on, meaning
that instruc ons are executed only if certain condi ons are met,
reducing the need for branching and improving performance.

13.b Relate the ARM architecture with tools and so ware environment support CO3/K2
for embedded system so ware development.
Ans:
ARM Architecture and Embedded System Development Tools
The ARM architecture is widely used in embedded systems due to its
power efficiency and performance. The ecosystem of tools suppor ng
ARM-based development is rich, providing essen al components for every
stage of development:
1. Development Environments (IDEs):
o Keil MDK-ARM: Ideal for ARM Cortex-M development with an
ARM compiler and debugger.
o ARM Development Studio: Supports all ARM processors with
powerful debugging tools.
o IAR Embedded Workbench: Known for highly op mized code
genera on.
2. Compilers:
 o ARM Compiler (ARMCC): Generates op mized machine code
for ARM devices.
o GCC (GNU Compiler Collec on): Open-source compiler with
ARM support.
o LLVM: Modular, open-source compiler framework used with
Clang.
3. Debugging and Profiling Tools:
o ULINK Debug Adapters and DSTREAM: Hardware-based tools
for on-chip debugging and tracing.
o OpenOCD: Open-source on-chip debugging tool.
o gdb: Command-line debugger for ARM devices.
4. Opera ng Systems and Middleware:
o CMSIS: ARM Cortex-M so ware interface standard with
peripheral drivers and RTOS support.
o FreeRTOS: Lightweight RTOS for real- me applica ons.
o mbed OS: ARM’s IoT-focused OS for Cortex-M processors.
5. Simula on Tools:
o QEMU: Emulator for ARM architectures.
o Proteus VSM for ARM: Simulates ARM-based systems and
peripherals.
6. Cross-Pla orm Build Systems:
o CMake: Manages portable build processes.
o Makefile: Defines build instruc ons for ARM-based projects.
Benefits of ARM Tools:
 Op miza on: ARM-specific compilers focus on performance and
power efficiency.
 Real- me Debugging: Tools like Keil MDK and ULINK provide real-
me, on-chip debugging.
 RTOS Integra on: Seamless integra on with FreeRTOS and CMSIS for
efficient task management.

Faculty In-charge Course Coordinator HoD-ECE