Expt1

1. Verilog Description of a 4-Bit Adder

Here's a simple Verilog code for a 4-bit adder:

module FourBitAdder (
input [3:0] A, B,
input Cin,
output [3:0] Sum,
output Cout
);
wire [3:0] carry;

assign {Cout, Sum} = A + B + Cin;

endmodule

2. Test-bench to Verify Functionality

A test-bench to verify the functionality of the 4-bit adder:

module FourBitAdder_tb;
reg [3:0] A, B;
reg Cin;
wire [3:0] Sum;
wire Cout;

FourBitAdder uut (
.A(A),
.B(B),
.Cin(Cin),
.Sum(Sum),
.Cout(Cout)
);

initial begin
// Initialize inputs
A = 4'b0000; B = 4'b0000; Cin = 0;
#10 A = 4'b0101; B = 4'b0011; Cin = 0;
#10 A = 4'b1111; B = 4'b0001; Cin = 1;
#10 A = 4'b1010; B = 4'b0101; Cin = 0;
#10 $stop;
end

initial begin
 $monitor("Time = %0d, A = %b, B = %b, Cin = %b, Sum = %b, Cout =
%b", $time, A, B, Cin, Sum, Cout);
end
endmodule

3. Synthesize the Design

To synthesize the design, you would typically use a tool like Synopsys Design
Compiler. Here is a general outline of the steps:

1. Read the Verilog file:

2. read_verilog FourBitAdder.v
3. Set constraints:
4. create_clock -period 10 [get_ports clk]
5. set_input_delay 2 [all_inputs]
6. set_output_delay 2 [all_outputs]
7. Compile the design:
8. compile_ultra
9. Generate the gate-level netlist: tcl write -format verilog -hierarchy
-output FourBitAdder_netlist.v

4. Analyze the Report

After synthesis, you can analyze the report to identify the critical path, maximum
delay, total number of cells, power requirement, and total area required. Here is an
example of what you might look for:

 Critical Path: The longest path in the design that determines the maximum
clock frequency.
 Maximum Delay: The delay of the critical path.
 Total Number of Cells: The total number of logic cells used in the design.
 Power Requirement: The total power consumption of the design.
 Total Area Required: The total silicon area required for the design.

These details will be available in the synthesis report generated by the tool.
Expt2

1. Verilog Code for 4-Bit Shift-and-Add Multiplier

Here's a Verilog description of a 4-bit shift-and-add multiplier:

module ShiftAddMultiplier (
input [3:0] A, B,
output [7:0] Product
);
reg [7:0] P;
reg [3:0] Q;
reg [3:0] M;
reg Q_1;
integer i;

always @(A or B) begin

P = 8'b0;
Q = B;
M = A;
Q_1 = 1'b0;

for (i = 0; i < 4; i = i + 1) begin

if (Q[0] == 1'b1) begin
P = P + {M, 4'b0};
end
{P, Q, Q_1} = {P[7], P, Q, Q_1} >> 1;
end
end

assign Product = P;
endmodule

2. Test-bench to Verify Functionality

A test-bench to verify the functionality of the 4-bit shift-and-add multiplier:

module ShiftAddMultiplier_tb;
reg [3:0] A, B;
wire [7:0] Product;

ShiftAddMultiplier uut (
.A(A),
.B(B),
.Product(Product)
);
 initial begin
// Initialize inputs
A = 4'b0000; B = 4'b0000;
#10 A = 4'b0011; B = 4'b0010; // 3 * 2 = 6
#10 A = 4'b0101; B = 4'b0011; // 5 * 3 = 15
#10 A = 4'b1111; B = 4'b0001; // 15 * 1 = 15
#10 A = 4'b1010; B = 4'b0101; // 10 * 5 = 50
#10 $stop;
end

initial begin
$monitor("Time = %0d, A = %b, B = %b, Product = %b", $time, A, B,
Product);
end
endmodule

3. Synthesize the Design

To synthesize the design, you would typically use a tool like Synopsys Design
Compiler. Here is a general outline of the steps:

1. Read the Verilog file:

2. read_verilog ShiftAddMultiplier.v
3. Set constraints:
4. create_clock -period 10 [get_ports clk]
5. set_input_delay 2 [all_inputs]
6. set_output_delay 2 [all_outputs]
7. Compile the design:
8. compile_ultra
9. Generate the gate-level netlist: tcl write -format verilog -hierarchy
-output ShiftAddMultiplier_netlist.v

4. Analyze the Report

After synthesis, you can analyze the report to identify the critical path, maximum
delay, total number of cells, power requirement, and total area required. Here is an
example of what you might look for:

 Critical Path: The longest path in the design that determines the maximum
clock frequency.
 Maximum Delay: The delay of the critical path.
 Total Number of Cells: The total number of logic cells used in the design.
 Power Requirement: The total power consumption of the design.
 Total Area Required: The total silicon area required for the design.
Expt3

1. Verilog Description of a 32-Bit ALU

Here's a Verilog code for a 32-bit ALU:

module ALU32Bit (
input [31:0] A, B,
input [2:0] ALU_Sel,
output reg [31:0] ALU_Result,
output reg Zero
);
always @(*) begin
case (ALU_Sel)
3'b000: ALU_Result = A + B; // Addition
3'b001: ALU_Result = A - B; // Subtraction
3'b010: ALU_Result = A * B; // Multiplication
3'b011: ALU_Result = A / B; // Division
3'b100: ALU_Result = A & B; // AND
3'b101: ALU_Result = A | B; // OR
3'b110: ALU_Result = A ^ B; // XOR
3'b111: ALU_Result = ~(A | B); // NOR
default: ALU_Result = 32'b0;
endcase
Zero = (ALU_Result == 32'b0) ? 1'b1 : 1'b0;
end
endmodule

2. Test-bench to Verify Functionality

A test-bench to verify the functionality of the 32-bit ALU:

module ALU32Bit_tb;
reg [31:0] A, B;
reg [2:0] ALU_Sel;
wire [31:0] ALU_Result;
wire Zero;

ALU32Bit uut (
.A(A),
.B(B),
.ALU_Sel(ALU_Sel),
.ALU_Result(ALU_Result),
.Zero(Zero)
);
 initial begin
// Initialize inputs
A = 32'h00000000; B = 32'h00000000; ALU_Sel = 3'b000;
#10 A = 32'h0000000F; B = 32'h00000001; ALU_Sel = 3'b000; //
Addition
#10 A = 32'h0000000F; B = 32'h00000001; ALU_Sel = 3'b001; //
Subtraction
#10 A = 32'h0000000F; B = 32'h00000002; ALU_Sel = 3'b010; //
Multiplication
#10 A = 32'h0000000F; B = 32'h00000003; ALU_Sel = 3'b011; //
Division
#10 A = 32'h0000000F; B = 32'h0000000F; ALU_Sel = 3'b100; // AND
#10 A = 32'h0000000F; B = 32'h0000000F; ALU_Sel = 3'b101; // OR
#10 A = 32'h0000000F; B = 32'h0000000F; ALU_Sel = 3'b110; // XOR
#10 A = 32'h0000000F; B = 32'h0000000F; ALU_Sel = 3'b111; // NOR
#10 $stop;
end

initial begin
$monitor("Time = %0d, A = %h, B = %h, ALU_Sel = %b, ALU_Result =
%h, Zero = %b", $time, A, B, ALU_Sel, ALU_Result, Zero);
end
endmodule

3. Synthesize the Design

To synthesize the design using Xilinx tools, follow these steps:

1. Read the Verilog file:

2. read_verilog ALU32Bit.v
3. Set constraints:
4. create_clock -period 10 [get_ports clk]
5. set_input_delay 2 [all_inputs]
6. set_output_delay 2 [all_outputs]
7. Compile the design:
8. synth_design -top ALU32Bit -part xc7z020clg484-1
9. Generate the gate-level netlist: tcl write_verilog -force
ALU32Bit_netlist.v

4. Analyze the Report

After synthesis, analyze the report to identify the critical path, maximum delay, total
number of cells, power requirement, and total area required. Here is an example of
what you might look for:
  Critical Path: The longest path in the design that determines the maximum
clock frequency.
 Maximum Delay: The delay of the critical path.
 Total Number of Cells: The total number of logic cells used in the design.
 Power Requirement: The total power consumption of the design.
 Total Area Required: The total silicon area required for the design.

These details will be available in the synthesis report generated by the tool.

Expt4

1. Verilog Description

D Flip-Flop
module DFlipFlop (
input D, clk,
output reg Q
);
always @(posedge clk) begin
Q <= D;
end
endmodule
SR Flip-Flop
module SRFlipFlop (
input S, R, clk,
output reg Q
);
always @(posedge clk) begin
if (S && !R)
Q <= 1;
else if (!S && R)
Q <= 0;
end
endmodule
JK Flip-Flop
module JKFlipFlop (
input J, K, clk,
output reg Q
);
always @(posedge clk) begin
if (J && !K)
Q <= 1;
else if (!J && K)
Q <= 0;
else if (J && K)
 Q <= ~Q;
end
endmodule

2. Test-bench to Verify Functionality

D Flip-Flop Test-bench
module DFlipFlop_tb;
reg D, clk;
wire Q;

DFlipFlop uut (
.D(D),
.clk(clk),
.Q(Q)
);

initial begin
clk = 0;
forever #5 clk = ~clk;
end

initial begin
D = 0;
#10 D = 1;
#10 D = 0;
#10 D = 1;
#10 $stop;
end

initial begin
$monitor("Time = %0d, D = %b, Q = %b", $time, D, Q);
end
endmodule
SR Flip-Flop Test-bench
module SRFlipFlop_tb;
reg S, R, clk;
wire Q;

SRFlipFlop uut (
.S(S),
.R(R),
.clk(clk),
.Q(Q)
);
 initial begin
clk = 0;
forever #5 clk = ~clk;
end

initial begin
S = 0; R = 0;
#10 S = 1; R = 0;
#10 S = 0; R = 1;
#10 S = 1; R = 1;
#10 S = 0; R = 0;
#10 $stop;
end

initial begin
$monitor("Time = %0d, S = %b, R = %b, Q = %b", $time, S, R, Q);
end
endmodule
JK Flip-Flop Test-bench
module JKFlipFlop_tb;
reg J, K, clk;
wire Q;

JKFlipFlop uut (
.J(J),
.K(K),
.clk(clk),
.Q(Q)
);

initial begin
clk = 0;
forever #5 clk = ~clk;
end

initial begin
J = 0; K = 0;
#10 J = 1; K = 0;
#10 J = 0; K = 1;
#10 J = 1; K = 1;
#10 J = 0; K = 0;
#10 $stop;
end

initial begin
$monitor("Time = %0d, J = %b, K = %b, Q = %b", $time, J, K, Q);
 end
endmodule

3. Synthesize the Design

To synthesize the design using Xilinx tools, follow these steps:

1. Read the Verilog file:

2. read_verilog DFlipFlop.v SRFlipFlop.v JKFlipFlop.v

3. Set constraints:
4. create_clock -period 10 [get_ports clk]
5. set_input_delay 2 [all_inputs]
6. set_output_delay 2 [all_outputs]

7. Compile the design:

8. synth_design -top DFlipFlop -part xc7z020clg484-1
9. synth_design -top SRFlipFlop -part xc7z020clg484-1
10. synth_design -top JKFlipFlop -part xc7z020clg484-1

11. Generate the gate-level netlist: tcl write_verilog -force

DFlipFlop_netlist.v write_verilog -force SRFlipFlop_netlist.v
write_verilog -force JKFlipFlop_netlist.v

4. Analyze the Report

After synthesis, analyze the report to identify the critical path, maximum delay, total
number of cells, power requirement, and total area required. Here is an example of
what you might look for:

 Critical Path: The longest path in the design that determines the maximum
clock frequency.
 Maximum Delay: The delay of the critical path.
 Total Number of Cells: The total number of logic cells used in the design.
 Power Requirement: The total power consumption of the design.
 Total Area Required: The total silicon area required for the design.

These details will be available in the synthesis report generated by the tool.

Expt5

1. Verilog Code for 4-bit Synchronous MOD-N Counter with

Asynchronous Reset
Here's a Verilog description of a 4-bit synchronous MOD-N counter with an
asynchronous reset:
module ModNCounter (
input clk,
input reset,
output reg [3:0] count
);
parameter N = 10; // Change N to the desired MOD value

always @(posedge clk or posedge reset) begin

if (reset)
count <= 4'b0000;
else if (count == N-1)
count <= 4'b0000;
else
count <= count + 1;
end
endmodule

2. Test-bench to Verify Functionality

A test-bench to verify the functionality of the 4-bit synchronous MOD-N counter:

module ModNCounter_tb;
reg clk;
reg reset;
wire [3:0] count;

ModNCounter #(.N(10)) uut (

.clk(clk),
.reset(reset),
.count(count)
);

initial begin
clk = 0;
forever #5 clk = ~clk;
end

initial begin
reset = 1;
#10 reset = 0;
#100 reset = 1;
#10 reset = 0;
#100 $stop;
end

initial begin
$monitor("Time = %0d, reset = %b, count = %b", $time, reset,
count);
end
endmodule

3. Synthesize the Design

To synthesize the design using Xilinx tools, follow these steps:
1. Read the Verilog file:

2. read_verilog ModNCounter.v

3. Set constraints:

4. create_clock -period 10 [get_ports clk]

5. set_input_delay 2 [all_inputs]
6. set_output_delay 2 [all_outputs]

7. Compile the design:

8. synth_design -top ModNCounter -part xc7z020clg484-1

9. Generate the gate-level netlist:

10. write_verilog -force ModNCounter_netlist.v

4. Analyze the Report

After synthesis, analyze the report to identify the critical path, maximum delay, total
number of cells, power requirement, and total area required. Here is an example of
what you might look for:

 Critical Path: The longest path in the design that determines the maximum clock
frequency.
 Maximum Delay: The delay of the critical path.
 Total Number of Cells: The total number of logic cells used in the design.
 Power Requirement: The total power consumption of the design.
 Total Area Required: The total silicon area required for the design.

5. Verify Functionality Using Gate-Level Netlist

To verify the functionality using the gate-level netlist, you can use the same test-
bench with the synthesized netlist. Compare the results at RTL and gate-level to
ensure they match.

Expt6

Let's break down the tasks step by step for designing and analyzing a CMOS inverter.

Part (a): CMOS Inverter Design and Analysis

1. Construct the Schematic

 Load Capacitance: 0.1pF

 Width Settings:
o ( Wn = Wp )
o ( Wn = 2Wp )
 o ( Wn = \frac{Wp}{2} )
 Length: Set according to the selected technology (e.g., 180nm, 90nm, etc.)

2. Input Signal Configuration

 Rise Time: 1ns

 Fall Time: 1ns
 Pulse Width: 10ns
 Time Period: 20ns

3. Simulation and Plotting

 Use a simulation tool like Cadence Virtuoso or LTspice to set up the input
signal and simulate the inverter.
 Plot the input voltage and output voltage waveforms.

4. Compute Delays

 tpHL (Propagation Delay High to Low): Time taken for the output to
transition from high to low.
 tpLH (Propagation Delay Low to High): Time taken for the output to
transition from low to high.
 td (Total Delay): Average of tpHL and tpLH.

5. Tabulate Results

 Run simulations for all three geometrical settings.

 Tabulate the results for tpHL, tpLH, and td.
 Identify the best geometry for minimum delay.

Part (b): Layout Design and Post-Layout Analysis

1. Draw Layout

 Width Settings: ( Wp = 40 ), ( Wn = 20 )
 Use a layout tool like Cadence Virtuoso to draw the layout of the inverter.
 Ensure the layout follows optimum layout methods to minimize parasitics and
area.

2. Verify DRC and LVS

 DRC (Design Rule Check): Ensure the layout adheres to the design rules of
the selected technology.
 LVS (Layout vs. Schematic): Verify that the layout matches the schematic.
3. Extract Parasitics

 Extract parasitic capacitances and resistances from the layout.

4. Perform Post-Layout Simulations

 Run post-layout simulations including the extracted parasitics.

 Compare the results with pre-layout simulations to observe the impact of
parasitics.

5. Compare Results

 Compare the delay, power, and other performance metrics between pre-
layout and post-layout simulations.

Example of Tabulated Results

Geometry tpHL (ns) tpLH (ns) td (ns)

( Wn = Wp ) x.xx x.xx x.xx

( Wn = 2Wp ) x.xx x.xx x.xx

( Wn = \frac{Wp}{2} ) x.xx x.xx x.xx

Would you like more detailed guidance on any specific step or tool usage?

Exp7

Let's go through the steps to design, verify, and analyze a 2-input CMOS NOR gate
with similar delay to the CMOS inverter.

1. Schematic of 2-Input CMOS NOR Gate

To design a 2-input CMOS NOR gate, you can use the following configuration:

 PMOS Transistors: Two PMOS transistors in parallel.

 NMOS Transistors: Two NMOS transistors in series.

2. Verify Functionality

Use a simulation tool like Cadence Virtuoso or LTspice to verify the functionality of
the NOR gate. Apply the following input combinations and observe the output:

 Input Combinations:
o A = 0, B = 0
o A = 0, B = 1
o A = 1, B = 0
 o A = 1, B = 1

3. Compute Delay (td)

Measure the propagation delays (tpHL and tpLH) for each input combination and
compute the average delay (td).

4. Tabulate Results

Create a table to summarize the delays for each input combination.

5. Increase Drive Strength

Increase the drive strength of the NOR gate to 2X and 4X by scaling the widths of the
transistors. Repeat the delay measurements and tabulate the results.

Example of Tabulated Results

Original Drive Strength

Input Combination tpHL (ns) tpLH (ns) td (ns)

A = 0, B = 0 x.xx x.xx x.xx

A = 0, B = 1 x.xx x.xx x.xx

A = 1, B = 0 x.xx x.xx x.xx

A = 1, B = 1 x.xx x.xx x.xx

2X Drive Strength
Input Combination tpHL (ns) tpLH (ns) td (ns)

A = 0, B = 0 x.xx x.xx x.xx

A = 0, B = 1 x.xx x.xx x.xx

A = 1, B = 0 x.xx x.xx x.xx

A = 1, B = 1 x.xx x.xx x.xx

4X Drive Strength
Input Combination tpHL (ns) tpLH (ns) td (ns)

A = 0, B = 0 x.xx x.xx x.xx

A = 0, B = 1 x.xx x.xx x.xx

A = 1, B = 0 x.xx x.xx x.xx

A = 1, B = 1 x.xx x.xx x.xx

Steps to Follow

1. Design the Schematic: Use a schematic editor to design the 2-input CMOS
NOR gate.
2. Set Up Simulation: Configure the input signal and load capacitance.
3. Run Simulations: Measure the delays for each input combination.
4. Increase Drive Strength: Scale the transistor widths and repeat the
simulations.
5. Tabulate Results: Summarize the delays in a table.

Exp8

Let's go through the steps to construct the schematic of the Boolean expression ( Y
= (AB + CD + E)' ) using CMOS logic, verify its functionality, and analyze the delay.

1. Construct the Schematic

To implement the Boolean expression ( Y = (AB + CD + E)' ) using CMOS logic, we

need to create a NOR gate for the expression inside the parentheses and then an
inverter to get the final output.

Steps:

1. AND Gates: Create two AND gates for ( AB ) and ( CD ).

2. OR Gate: Combine the outputs of the AND gates and the input ( E ) using an
OR gate.
3. NOR Gate: Use a NOR gate to invert the output of the OR gate.

Schematic:

 AND Gate 1: Inputs ( A ) and ( B )

 AND Gate 2: Inputs ( C ) and ( D )
 OR Gate: Inputs are the outputs of AND Gate 1, AND Gate 2, and ( E )
 NOR Gate: Input is the output of the OR gate

2. Verify Functionality

Use a simulation tool like Cadence Virtuoso or LTspice to verify the functionality of
the expression. Apply different combinations of input vectors and observe the
output.

3. Compute Delay (td)

Measure the propagation delays (tpHL and tpLH) for different input combinations and
compute the average delay (td).

4. Tabulate Results
Create a table to summarize the delays for different input combinations.

Example of Tabulated Results

Input Combination tpHL (ns) tpLH (ns) td (ns)

A = 0, B = 0, C = 0, D = 0, E = 0 x.xx x.xx x.xx

A = 0, B = 1, C = 0, D = 1, E = 1 x.xx x.xx x.xx

A = 1, B = 1, C = 0, D = 0, E = 0 x.xx x.xx x.xx

A = 1, B = 1, C = 1, D = 1, E = 1 x.xx x.xx x.xx

Steps to Follow

1. Design the Schematic: Use a schematic editor to design the CMOS logic
circuit for the given Boolean expression.
2. Set Up Simulation: Configure the input signal and load capacitance.
3. Run Simulations: Measure the delays for different input combinations.
4. Tabulate Results: Summarize the delays in a table.

Exp9

Part (a): Common Source Amplifier Design and Analysis

1. Construct the Schematic

A common source amplifier with a PMOS current mirror load can be designed as
follows:

 NMOS Transistor: Acts as the amplifying device.

 PMOS Transistors: Form the current mirror load.

Schematic:

1. NMOS Transistor: Source connected to ground, gate connected to the input

signal, and drain connected to the output node.
2. PMOS Current Mirror: Two PMOS transistors with their sources connected to
VDD. The gate of both PMOS transistors is connected together and to the
drain of one of the PMOS transistors (reference transistor). The drain of the
other PMOS transistor (output transistor) is connected to the drain of the
NMOS transistor.

2. Transient and AC Response

 Transient Response: Apply a step input signal and observe the output
waveform.
  AC Response: Perform an AC analysis to obtain the frequency response and
measure the gain and bandwidth.

3. Measure Unit Gain Bandwidth (UGB) and Amplification Factor

 UGB: The frequency at which the gain of the amplifier drops to 1.

 Amplification Factor: The ratio of the output signal amplitude to the input
signal amplitude.

4. Vary Transistor Geometries

 Vary the widths of the NMOS and PMOS transistors and observe the impact on
UGB and amplification factor.

Example of Tabulated Results

Geometry UGB (MHz) Amplification Factor

Wn = 1µm, Wp = 1µm x.xx x.xx

Wn = 2µm, Wp = 2µm x.xx x.xx

Wn = 4µm, Wp = 4µm x.xx x.xx

Part (b): Layout Design and Post-Layout Analysis

1. Draw Layout

 Use a layout tool like Cadence Virtuoso to draw the layout of the common
source amplifier.
 Ensure the layout follows optimum layout methods to minimize parasitics and
area.

2. Verify DRC and LVS

 DRC (Design Rule Check): Ensure the layout adheres to the design rules of
the selected technology.
 LVS (Layout vs. Schematic): Verify that the layout matches the schematic.

3. Extract Parasitics

 Extract parasitic capacitances and resistances from the layout.

4. Perform Post-Layout Simulations

 Run post-layout simulations including the extracted parasitics.

 Compare the results with pre-layout simulations to observe the impact of
parasitics.
Example of Observations

Parameter Pre-Layout Post-Layout

UGB (MHz) x.xx x.xx

Amplification Factor x.xx x.xx

Delay (ns) x.xx x.xx

Steps to Follow

1. Design the Schematic: Use a schematic editor to design the common

source amplifier with a PMOS current mirror load.
2. Set Up Simulation: Configure the input signal and perform transient and AC
analysis.
3. Run Simulations: Measure UGB and amplification factor for different
geometries.
4. Draw Layout: Use a layout editor to draw the layout and verify DRC and LVS.
5. Extract Parasitics: Perform post-layout simulations and compare with pre-
layout results.
6. Tabulate Results: Summarize the observations in a table.

Exp10

Part (a): Two-Stage Operational Amplifier Design and

Analysis

1. Construct the Schematic

A two-stage operational amplifier typically consists of:

1. First Stage: Differential amplifier.

2. Second Stage: Common-source amplifier.

Schematic:

1. Differential Amplifier: Consists of a pair of NMOS transistors with a current

mirror load.
2. Common-Source Amplifier: Consists of an NMOS transistor with a PMOS
current mirror load.

2. Measure the Following Parameters

 Unity Gain Bandwidth (UGB): The frequency at which the gain of the
amplifier drops to 1.
  dB Bandwidth: The frequency range over which the amplifier maintains a
certain gain.
 Gain Margin and Phase Margin: Stability metrics of the amplifier with and
without coupling capacitance.

3. Use the Op-Amp in Inverting and Non-Inverting Configurations

 Inverting Configuration: Connect the input signal to the inverting terminal

and a feedback resistor network.
 Non-Inverting Configuration: Connect the input signal to the non-inverting
terminal and a feedback resistor network.

4. Study the Impact of Varying Transistor Geometries

 Vary the widths of the transistors in each stage and observe the impact on
UGB, 3dB bandwidth, gain, and power requirement.

Example of Tabulated Results

Geometry UGB (MHz) 3dB Bandwidth (MHz) Gain (dB) Power (mW)

W1 = 1µm, W2 = 1µm x.xx x.xx x.xx x.xx

W1 = 2µm, W2 = 2µm x.xx x.xx x.xx x.xx

W1 = 4µm, W2 = 4µm x.xx x.xx x.xx x.xx

Part (b): Layout Design and Post-Layout Analysis

1. Draw Layout

 Use a layout tool like Cadence Virtuoso to draw the layout of the two-stage
operational amplifier.
 Ensure the minimum transistor width is set to 300nm (or appropriate for the
selected technology).

2. Verify DRC and LVS

 DRC (Design Rule Check): Ensure the layout adheres to the design rules of
the selected technology.
 LVS (Layout vs. Schematic): Verify that the layout matches the schematic.

3. Extract Parasitics

 Extract parasitic capacitances and resistances from the layout.

4. Perform Post-Layout Simulations

 Run post-layout simulations including the extracted parasitics.

 Compare the results with pre-layout simulations to observe the impact of
parasitics.

Example of Observations

Parameter Pre-Layout Post-Layout

UGB (MHz) x.xx x.xx

3dB Bandwidth (MHz) x.xx x.xx

Gain (dB) x.xx x.xx

Power (mW) x.xx x.xx

Steps to Follow

1. Design the Schematic: Use a schematic editor to design the two-stage

operational amplifier.
2. Set Up Simulation: Configure the input signal and perform AC analysis.
3. Run Simulations: Measure UGB, 3dB bandwidth, gain, and power for
different geometries.
4. Draw Layout: Use a layout editor to draw the layout and verify DRC and LVS.
5. Extract Parasitics: Perform post-layout simulations and compare with pre-
layout results.
6. Tabulate Results: Summarize the observations in a table.

Demo Expts

Expt11

1. Write Verilog Description

Here's a basic Verilog description for a UART (Universal Asynchronous

Receiver/Transmitter):

module uart (
input wire clk,
input wire reset,
input wire rx,
output wire tx,
input wire [7:0] data_in,
output wire [7:0] data_out,
input wire write_enable,
output wire ready
);

// UART parameters
parameter BAUD_RATE = 9600;
parameter CLOCK_FREQ = 50000000; // 50 MHz
parameter BIT_PERIOD = CLOCK_FREQ / BAUD_RATE;

// Internal signals
reg [7:0] rx_buffer;
reg [7:0] tx_buffer;
reg [15:0] bit_counter;
reg tx_busy;
reg rx_ready;

// Transmit logic
always @(posedge clk or posedge reset) begin
if (reset) begin
tx <= 1'b1;
tx_busy <= 1'b0;
bit_counter <= 0;
end else if (write_enable && !tx_busy) begin
tx_buffer <= data_in;
tx_busy <= 1'b1;
bit_counter <= BIT_PERIOD;
end else if (tx_busy) begin
if (bit_counter == 0) begin
tx <= tx_buffer[0];
tx_buffer <= {1'b1, tx_buffer[7:1]};
bit_counter <= BIT_PERIOD;
end else begin
bit_counter <= bit_counter - 1;
end
end
end

// Receive logic
always @(posedge clk or posedge reset) begin
if (reset) begin
rx_ready <= 1'b0;
rx_buffer <= 8'b0;
bit_counter <= 0;
end else if (!rx_ready) begin
if (rx == 0) begin // Start bit detected
bit_counter <= BIT_PERIOD / 2;
end else if (bit_counter == 0) begin
rx_buffer <= {rx, rx_buffer[7:1]};
 bit_counter <= BIT_PERIOD;
if (rx_buffer[0] == 1'b1) begin // Stop bit detected
rx_ready <= 1'b1;
end
end else begin
bit_counter <= bit_counter - 1;
end
end else if (rx_ready) begin
data_out <= rx_buffer;
rx_ready <= 1'b0;
end
end

assign ready = !tx_busy && rx_ready;

endmodule

2. Verify the Functionality using Test-bench

Here's a simple test-bench to verify the UART functionality:

module uart_tb;

reg clk;
reg reset;
reg rx;
wire tx;
reg [7:0] data_in;
wire [7:0] data_out;
reg write_enable;
wire ready;

// Instantiate the UART module

uart uut (
.clk(clk),
.reset(reset),
.rx(rx),
.tx(tx),
.data_in(data_in),
.data_out(data_out),
.write_enable(write_enable),
.ready(ready)
);

// Clock generation
always #10 clk = ~clk;
initial begin
// Initialize signals
clk = 0;
reset = 1;
rx = 1;
data_in = 8'h00;
write_enable = 0;

// Reset the UART

#20 reset = 0;

// Transmit data
#100 data_in = 8'hA5;
write_enable = 1;
#20 write_enable = 0;

// Wait for transmission to complete

wait (ready);

// Receive data
#100 rx = 0; // Start bit
#1040 rx = 1; // Data bits
#1040 rx = 0;
#1040 rx = 1;
#1040 rx = 0;
#1040 rx = 1;
#1040 rx = 0;
#1040 rx = 1;
#1040 rx = 0;
#1040 rx = 1; // Stop bit

// Wait for reception to complete

wait (ready);

// Check received data

if (data_out == 8'hA5) begin
$display("Test Passed");
end else begin
$display("Test Failed");
end

$stop;
end

endmodule
3. Synthesize the Design

To synthesize the design, you can use a tool like Synopsys Design Compiler or
Cadence Genus. Set the area and timing constraints according to your target library.

4. Tabulate the Area, Power, and Delay

After synthesis, you can use the synthesis report to tabulate the area, power, and
delay. Identify the critical path from the timing report.

Example Table

Metric Value

5000
Area
gates

Power 10 mW

Delay 5 ns

Path
Critical Path
details

Expt12

Designing and characterizing a 6T SRAM cell involves several steps. Let's

break it down:

1. Design the 6T SRAM Cell

A 6T SRAM cell consists of six transistors: two NMOS and two PMOS
transistors forming cross-coupled inverters, and two NMOS access
transistors.

2. Characterize the SRAM Cell

To measure the Read Time, Write Time, Static Noise Margin (SNM), and
Power, you can use simulation tools like Cadence Virtuoso or HSPICE.

Read Time

 Apply a read operation and measure the time it takes for the bitline to
discharge to a certain voltage level.

Write Time
 Metric Value

 Apply a write operation and measure the time it takes for the cell to
flip its state.

Static Noise Margin (SNM)

 Use the butterfly curve method to determine the SNM, which is the
maximum noise voltage that can be tolerated without flipping the cell
state.

Power

 Measure the power consumption during read and write operations.

3. Draw the Layout of 6T SRAM

Use a layout editor like Cadence Virtuoso to draw the layout. Ensure to follow
optimum layout methods to minimize area and parasitics.

4. Verify for DRC & LVS

 DRC (Design Rule Check): Ensure the layout adheres to the

foundry's design rules.
 LVS (Layout vs. Schematic): Verify that the layout matches the
schematic.

5. Extract Parasitics

 Extract parasitic capacitances and resistances from the layout using

tools like Calibre.

6. Perform Post-Layout Simulations

 Run post-layout simulations to include the effects of parasitics and

compare the results with pre-layout simulations.

7. Record Observations

 Tabulate the results for Read Time, Write Time, SNM, and Power from
both pre-layout and post-layout simulations.

Example Table

Metric Pre-Layout Value Post-Layout Value

Read Time 2 ns 2.5 ns

 Metric Value

Write Time 3 ns 3.5 ns

SNM 200 mV 180 mV

Power 1 mW 1.2 mW

Layout Example

Here's a simplified layout example for a 6T SRAM cell:

+-------------------+
| |
| PMOS PMOS |
| | | |
| | | |
| NMOS NMOS |
| | | |
| | | |
| NMOS NMOS |
| |
+-------------------+

This is a high-level overview. For detailed steps, you would need access to
specific EDA tools and foundry PDKs (Process Design Kits). If you have any
specific questions or need further details on any step, feel free to ask!