SHEET 8

Consider extending the MIPS architecture with the instruction below, which adds three registers
together and stores the result in a register.

add3 rd, rs, rt, ru # rd = rs + rt + ru

This will use the same format as R-type instructions where the shamt field is used to hold ru.
The multicycle datapath from lecture appears below. Show what changes are needed to support add3.
You should only add wires and muxes to the datapath.
Draw the finite state machine diagram for the add3 instruction. Make sure to include any control
signals that you added. Your diagram should also support R-type, lw, sw, and beq instructions.

Show how can the add3 instruction be used in place of two dependent add instruction. What is the
percentage increase/decrease in the performance due to the use of add3 instead of 2 add instructions?

2 add instructions no. of cycles = 4+4=8

One add3 instruction no. of cycles = 5
percentage increase in performance = 8/5= 1.6
RegSrcB=0
Assume that the ALU can perform the max2 operation (i.e., return the greater of 2 inputs):
alu_result = (A_input>B_input) ? A_input :B_input;
if A_input > B_input
max = A_input
else
max= B_input
ALUOp for this instruction is MAX2.
Implement the max4 instruction that writes into register rd the largest value of 4
max4 rs, rt, rd, rm # rd = max (rs, rt, rd, rm)
This will use the same format as R-type instructions where the shamt field is used to hold rm. The
multicycle datapath appears in Figure 2. On the Figure show what changes are needed to support
max4. Draw the finite state machine diagram for the datapath.
The (imaginary) jump memory (jmem) instruction is like a jump-and-link (jal) instruction, except both
the target is loaded from memory and the return address is saved to memory. The i-type format is
used.

jmem (rt), offset(rs) # Memory[R[rs]+offset] = PC+4;

# PC = Memory[R[rt]]
On the figure show the changes needed to support jmem.
Draw the finite state machine diagram for the jmem instruction. Make sure to include any control
signals that you added. Your diagram should also support R-type, lw, sw, and beq instructions.
You are to add support for a new instruction, swap that exchanges the values of two registers to the
MIPS multicycle datapath.

swap $rs, $rt #R[rs] = rt and R[rt] = R[rs]

Add any necessary datapaths and control signals to the multicycle datapath. . Find a solution that
minimizes the number of clock cycles required for the new instruction without modifying the register
file.
Draw the finite state machine diagram for the swap instruction. Make sure to include any control
signals that you added. Your diagram should also support R-type, lw, sw, and beq instructions.

Cycle 3 : Cycle 4:
A→ rt B → rs
Regwrite=1 RegWrite = 1
MemtoReg=2 MemtoReg = 3
RegDst=0 RegDst = 2
 1. Using the multicycle datapath from the lecture implement a register-memory addition
instruction addm as follows.
addm rd, rs, rt # rd = rs + Mem[rt]
In other words, register rt contains a memory address which is read to produce the ALU's operand.
The instruction should use the same format as R-type instructions. On the figure show the changes
needed to support addm.
Draw the finite state machine diagram for the addm instruction. Make sure to include any control
signals that you added. Your diagram should also support R-type, lw, sw, and beq instructions.
Sub → cycle 3 (execution)
For the following code segment, complete the Table 2 indicating the values for the control signals at
the following cycles when executed on a multi-cycle processor?
addi $s0, $zero, 800 4 s0 = 800
sub $s1, $zero, $zero 4 s1 = 0
L1: lw $t0, 0($a0) 5 t0 = content of add a0
add $s1, $s1, $t0 4 s1 = s1 + t0
add $a0, $a0, 4 4 a0 = a0 +4
addi $s0, $s0,-1 4 s0 = s0 -1
bnẹ $s0, $zero, L1 3 if s0 != 0 go to L1
add $s1, $s1, $s1 4
Mem Mem ALUSrc ALUSrc
PCWrite IorD IRWrite RegDst MemToReg RegWrite ALUOp PCSrc
Read Write A B

7th cycle

sub 0 X 0 0 0 X X 0 1 0 sub X
execution

26th cycle

Instr. 1 0 1 0 1 X X 0 0 1 add 0
fetch

33'rd
cycle
0 X 0 0 0 0 1 1 X X X X
Lw write
back

Assume that the operating time for major functional units is as follows:
Memory Units: 200 ps, ALU and Adders: 180 ps, Register File (R or W): 100 ps
Complete the table to compare between the single cycle and a muti-cycle implementations of the
above code in terms of number of clock cycles and total execution time

No. of clock cycles Total execution time

Single-cycle 4003 3.122 µs
Multi-cycle 16012 3.202µs

No. of instructions= 3+800(5) = 4003

Single-cycle CPU execution time= CPI*longest instruction time* no. of instructions
Longest instruction is lw = instruction memory + register file read + ALU execution + data memory +
register file write = 200+100+180+200+100=780 ps
Execution time = 1*780*10-12*4003=3.122 µs
Multi-cycle CPU execution time= no. of cycles*longest cycle time
No. of cycles= 4+4+4+800(5+4+4+4+3)=16012
CPU execution time=16012*200*10-12=3.202µs

Instr. Reg file read Execution Data memory Reg file write time
Memory 100 (ALU) 180 200 100
200
R-type ✔ ✔ ✔ -------------------- ✔ 580
Sw ✔ ✔ ✔ ✔ ------------------- 680
Lw ✔ ✔ ✔ ✔ ✔ 780
Beq ✔ ✔ ✔ ------------------- ------------------- 480
Jump ✔ ------------------ -------------------- -------------------- ------------------- 200
For the following code segment, complete the table below indicating the values for the control signals
at the specified cycles when executed on a multi-cycle processor?

addi $t3, $zero, 100 4

add $t4, $zero, $zero 4
loop: lw $t5, 0($t1) 5
add $t4, $t4, $t5 4
lw $t6, 0($t2) 5
sub $t4, $t4, $t6 4
addi $t3, $t3, -1 4
bne $t3, $zero, loop 3

Mem Mem ALUSrc ALUSrc

PCWrite IorD IRWrite RegDst MemToReg RegWrite ALUOp PCSrc
Read Write A B

14'th
cycle
1 0 1 0 1 X X 0 0 1 add 0
Instr.
fetch

36’th
cycle
0 X 0 0 0 X X 0 0 2 add X
Lw
execution