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Comparison of Power Estimation in Different Stages of An ASIC Design Stages

Power Analysis

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25 views19 pages

Comparison of Power Estimation in Different Stages of An ASIC Design Stages

Power Analysis

Uploaded by

GoobeD'Great
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Niklas Persson

Comparison of Power Estimation


in Different Stages of an ASIC
Design Cycle
Niklas Persson
ASIC Design Engineer
VIA Technologies (Sweden) AB
Niklas Persson 2

Agenda

• Introduction to power estimation


• Case study flows
• Capacity of different flows
• Quality of results
• Conclusions
Niklas Persson 3

Case Study Introduction

• DSP system
– DSP Core
– Very large on-chip SRAM
– Part of a larger SoC
• Aggressively clock-gated design style
• Clock shutting techniques used
• Chip aimed for battery driven devices
Niklas Persson 4

Why power estimation?

• Power optimization of the design


• System designers need to know the power
consumption
• Marketing wants to have specs
• SoC designers need to choose the correct IP
Niklas Persson 5

What do we estimate

• Average power consumption


• What do we want to estimate in our battery driven
scenario?
– Stand by power consumption
– Real life application
Niklas Persson 6

Power estimation flow


requirements
• Good correlation with final silicon
• Possible to run early in the design cycle
• Very high capacity
– Millions of clock cycles needed for our full application test
cases
– No need to create special test cases emulating the toggle
of an application
• Short runtimes
Niklas Persson 7

Flows used

• Flow A: VCD flow


– Netlist simulation
– VCD activity file
• Flow B: SAIF flow
– Netlist simulation
– SAIF activity file
• Flow C: RTL – SAIF flow
– RTL simulation
– SAIF activity file
Niklas Persson 8

Switching Activity Formats

• Value Change Dump (VCD)


– Output from a simulator
– Contains all changes of values of signals
– Contains the time of each change
• Switching Activity Interchange Format (SAIF)
– Output from a simulator
– Contains the average switching activity of signals
– Has no information of the time of each change
Niklas Persson 9

Flow A: VCD flow

• Gate level netlist


simulation
• VCD file for switching
activity
• Advantages
– Accurate flow
– Possible to estimate part of
the VCD file
• Disadvantages
– Long runtime for the netlist
simulation
– VCD file can be huge
Niklas Persson 10

Flow B: SAIF flow

• Gate level netlist


simulation
• SAIF file used for
switching activity
• Advantages
– Accurate
– SAIF files are always small
• Disadvantages
– Long runtime of netlist
simulation
– Not possible to estimate
part of the SAIF file
Niklas Persson 11

Flow C: RTL – SAIF flow

• RTL simulation
• SAIF file used for
switching activity
• Advantages
– Fast RTL simulation
– Small SAIF file
• Disadvantages
– Not as accurate
– Not possible to estimate
part of the SAIF file
Niklas Persson 12

Test cases

• IDLE
– DSP at full clock speed with large parts of the DSP
system turned off
• AVG
– A mix of DSP core operations and memory access
• MAX
– DSP core and memory activity for max power
Niklas Persson 13

Operating conditions

• All tests were run with typical PVT


• The netlist used was the post-route netlist
implemented on the chip
• Extracted parasitics were back annotated
in the power estimations
Niklas Persson 14

Capacity – Switching
Activity File Sizes
• Two test cases that run
File Sizes (MB)
for 50k and 500k
simulation cycles 10000 6200

• The VCD file is too


1000
large to read into
PrimePower 100
RTL SAIF
Netlist SAIF
• Could not generate a 13.8 14 Netlist VCD

500k Netlist VCD file 10 4.7 4.8

• There exists flows that


1
pipes the VCD directly 50k 500k

to PrimePower
Niklas Persson 15

Capacity – Simulation Runtime

Runtime (minutes)
• RTL simulations are 90
more than 25 times 80
faster than gate level 70

simulations 60
50
• All simulations ran on a RTL
40 Netlist
3.2 GHz server 30
20
10
0
50k 500k
Niklas Persson 16

Power Measurement on
Actual Silicon Prototype
• Difference between the 40
different test cases 35
• Very good correlation 30
between prototype
25
measurements and VCD
VCD flow
flow (within 5 %) 20
Prototype
15

10

0
IDLE- AVG- IDLE-
AVG MAX MAX
Niklas Persson 17

Comparison of flows at DSP


system level
• DSP system including 50
memories 45
• Power estimations shows a 40
Netlist
good correlation between the 35 VCD
different flows. Especially 30 Netlist
between the netlist VCD and 25
SAIF
SAIF flows RTL SAIF
20
• The silicon prototype 15 Prototype
measurements have a small
10
negative offset due to chip
5
characteristics
0
IDLE AVG MAX
Niklas Persson 18

Comparison of flows at DSP


core level
• DSP core power estimations 14
without memories 12
• Netlist VCD and SAIF flows
have good correlation 10
Netlist
• RTL SAIF flow has some 8 VCD
reduced accuracy in the Netlist
SAIF
IDLE test case due to the 6
RTL SAIF
heavily clock-gated clock
4
network
2

0
IDLE AVG MAX
Niklas Persson 19

Conclusions

• Correlation between VCD flow and real life power


measurements are very good
• In this design the VCD flow is not feasible for long test
cases
• Precision of a SAIF flow is very close to the
corresponding VCD flow
• The difference in power consumption between test
cases with different levels of chip activity can be huge
• The RTL – SAIF flow is fast and has an accuracy
close to the netlist flows
• The most important factor for a flow is to have the
capacity for a real life application test case

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