Design and Verification of Low Power SoCs:

An Application Oriented Approach

John Biggs, ARM Ed Huijbregts, Magma

Juergen Karmann, Infineon Stephen Bailey, Mentor
Gary Delp, LSI Yi-Kan Cheng, TSMC
Organizer: Yatin Trivedi

Agenda

• 14:00-14:05 Introduction
Stephen Bailey, Director, Verification Products, Mentor Graphics
• 14:05-14:30 Low Power Challenges in Automotive Applications
Juergen Karmann, Senior Staff Engineer Design Methodology,
Automotive, Industrial & Multimarket, Infineon Technologies
• 14:30-14:55 Low Power Challenges for Storage SoC Design and Verification
Dr. Gary Delp, Distinguished Engineer, LSI Corp
• 14:55-15:20 Requirements and Solutions for Low Power Processor Cores
John Biggs, Consultant Engineer, ARM
• 15:20-15:45 Process-aware Low Power Design Ecosystem
Dr. Yi-Kan Cheng, Department Manager, Reference Design Flow
Development, TSMC
• 15:45-16:05 Low Power Flow for Design and Verification
Dr. Ed Huijbregts, Vice President, Design Implementation Products,
Magma Design Automation
• 16:05-16: 50 Deploying Low Power Design Flows
A Multi-Vendor Collaborative Solution – Synopsys, Mentor, Magma
• 16:50-17:00 Roundtable and Wrap-up

Low Power Workshop - 2

1
Everyone Knows… Low Power is a Problem for Portable Devices

It’s all about

battery life

Low Power Workshop - 3

Low Power Challenge – Not Limited to Hand-held Devices

System
Packaging & Cooling Facilities

Computing
1
0.9
0.8
0.7
Reliability

0.6
0.5
0.4
0.3 Graphics
0.2
0.1
0
0 20 40 60 80
Temperature

Reliability Networking Cost

Low Power Workshop - 4

2
Design Techniques for Low Power

Constant Variable
Throughput/Latency Throughput/Latency

Design Time Non-Active Modules Run Time

Logic
Dynamic or
Re-Structuring,
Dynamic & Adaptive
Logic Sizing Clock Gating
Short Circuit Frequency &
Reduced VDD Multi-
Voltage Scaling
VDD

Sleep Transistors
Stack Effect
Leakage Multi-VDD Variable VTH
+ Multi-VTH
Variable VTH

Source: J. Rabaey, UCB 2005

• Problems and solutions for some of the applications

• How do we implement these techniques?
• How do we verify the implementation?
Low Power Workshop - 5

Each Step in Flow Requires Power Intent

Verify retention plus power up/down cycles

RTL Verif
Add low power elements wherever needed and optimize for
multi-voltage, multi-vth operation, plus test Synthesis

Verify RTL vs gates, plus low power rules

Pre-Verif
Implement optimal power grid, floorplan & switches, P&R with
power grid & layout intent/constraints Layout

Verify final design vs. RTL, validate low power structures

Post-Verif

Signoff on power grid integrity, timing, power Signoff

Finished
GDSII

Low Power Workshop - 6

3
Unified Power Format (UPF) – Addressing Power Intent Throughout the Flow

• Open standard / Interoperability UPF

UPF
HDL/
HDL/
• Accellera open standards development RTL
RTL

Simulation, Logical Equivalence Checking, …

• Multiple donations
• All members participated on equal basis
Synthesis
• IEEE P1801
• UPF copyright assigned to IEEE with the
right to create derivative works
UPF
UPF
• All members have an equal vote
Verilog
Verilog
• No member has veto control over UPF (Netlist)
(Netlist)

P&R

UPF
UPF
Verilog
Verilog
(Netlist)
(Netlist)
Low Power Workshop - 7

UPF Benefits

• Productivity
• Same intent used throughout entire low power RTL Verif
flow
• Interoperability and productivity with mixed EDA
Unified Power Format

Synthesis
flows
• High Quality Results Pre-Verif
• Consistent intent throughout flow = better
checking and convergence Layout
• IEEE P1801 approach enables successive
refinement Post-Verif

• Simple IP Reuse
Signoff
• Supports IP specification and use
• No changes needed to golden HDL Finished
GDSII

Low Power Workshop - 8

4
Agenda

• 14:00-14:05 Introduction
Stephen Bailey, Director, Verification Products, Mentor Graphics
• 14:05-14:30 Low Power Challenges in Automotive Applications
Juergen Karmann, Senior Staff Engineer Design Methodology,
Automotive, Industrial & Multimarket, Infineon Technologies
• 14:30-14:55 Low Power Challenges for Storage SoC Design and Verification
Dr. Gary Delp, Distinguished Engineer, LSI Corp
• 14:55-15:20 Requirements and Solutions for Low Power Processor Cores
John Biggs, Consultant Engineer, ARM
• 15:20-15:45 Process-aware Low Power Design Ecosystem
Dr. Yi-Kan Cheng, Department Manager, Reference Design Flow
Development, TSMC
• 15:45-16:05 Low Power Flow for Design and Verification
Dr. Ed Huijbregts, Vice President, Design Implementation Products,
Magma Design Automation
• 16:05-16: 50 Deploying Low Power Design Flows
A Multi-Vendor Collaborative Solution – Synopsys, Mentor, Magma
• 16:50-17:00 Roundtable and Wrap-up

Low Power Workshop - 9

Low Power Challenges in

Automotive Applications
DAC 2008, Sunday June 8, 2-5 p.m.

Juergen Karmann, Senior Staff Engineer Design Methodology,

Automotive, Industrial & Multimarket Business Group
Infineon Technologies, Munich, Germany

5
 Semi-conductor enabled functions of a typical car

Body & Convenience

Xenon Light, Seat Position,
Powertrain Climate Control, Dashboard
Engine Control Climate Control
Transmission Control
Battery Management Airbag Night Vision Park Distance
Steering Control
Transmission
Hybrid Dashboard
Engine Blindspot
Cooling Detection Suspension
FAN TPMS
Mirror Door Brake
Light Battery
Management Central Lock ABS ESP
Adaptive
Cruise Control

Safety Chassis

Airbag, ABS Brakes, Active Suspension,

Adaptive Cruise Control Power Steering
Page 11
Nico Kelling (IFJ AIM MC)

The Future has arrived …

Powertrain Î More performance

Engine Control Î Higher ambient temperature
Transmission Control
Battery Management Î But low power budgets

Body & Convenience

Î More features at higher complexity
Xenon Light, Window Lift,
Î Limited space in the car
Climate Control, Dashboard Î CMOS and Smart Power Technology
on a single die
Safety & Chassis
Î Smaller technology nodes
Airbag, ABS Brakes,
Adaptive Cruise Control Î High variability
Power Steering
Î But high reliability

… with complex low power systems in automotive applications

Page 12

6
Some Challenges

Electro Magnetic Compatibility (EMC)

Î “Be Reliable”

Complex low power designs to meet standby requirements

Î “Cope with Complex Power Intent”

Mix of the “Smart Power Technology” (SPT) and low power CMOS
Î “Adding Brain to Power”

Page 13

EMC Modeling
Chip

Real Layout Abstraction via Own Tool Netlist

Package

e.g., Peak Power Reduction EME Simulation

to enabled by

Î Smooth Implementation Design Flow

Î Proper Verification Design Flow

Page 14

7
Complex low power designs to meet power
budgets

1. Very limited power budget for contact less sensor

2. Voltage just right for required operation

3. High complexity of power supply system

to be addressed by : Î Formal Power Intent Specification

Î Smooth Design Flow for Implementation

Î Proper Verification Design Flow

Page 15

Integration of Low and High Power

Current Product (MCM):

Power-Chip µ-
Controlle
r

and the Challenges :

1. New coupling effects (parasitic) Ù full chip power aware AMS simulation

2. Diverging Current Ranges (µA Ù some A)

3. Shared power supplies among low power CMOS and ‘Smart Power’ domains

4. Digital / Analogue / High Voltage Co-Design

5. ......

to be addressed by : Î Formal Power Intent Specification

Î Interoperability of EDA Tools

Page 16

8
Integration of Low and High Power
horizontal integration
Next Step: (based on IFX 130nm node)

and the Challenges :

1. New coupling effects (parasitic) Ù full chip power aware AMS simulation

2. Diverging Current Ranges (µA Ù some A)

3. Shared power supplies among low power CMOS and ‘Smart Power’ domains

4. Digital / Analogue / High Voltage Co-Design

5. ......

to be addressed by : Î Formal Power Intent Specification

Î Interoperability of EDA Tools

Page 17

Cost
Pressure

Demands:
Î High Productivity
Î First Time Right

How can IEEE P1801 help ?

Page 18

9
Power Aware Design Flow

Productivity Improvement Power Source

File(s)
HDL/
Consistent Design Flow RTL

……
Interoperability in a multi vendor

Checking,
design flow

EquivalenceChecking,
Synthesis
Synthesis

smooth iteration loops for

Logical Equivalence
power and reliability optimization Power Source
Power Source
File(s)
File(s)
Verilog
Verilog
(Netlist)
(Netlist)

Simulation,Logical
First Time Right

Single power intend specification

Simulation,
P&R
P&R

Power and reliability

addressed already at RTL Power Source
Power Source
File(s)
File(s)
Verilog
Empowered by … Verilog
(Netlist)
(Netlist)

Page 19

Formal Power Intent Specification

Data model
XSD
„ UPF provided as XML structure (XSD)
„ Power intent specified by XML based on XSD Design Spec
XML
„ UPF derived from XML specification
Power Source
„ Equivalence check of power implementation HDL/
File(s)
Simulation, Logical Equivalence Checking, …

against power intent in specification RTL

Synthesis

Î higher verification coverage (first time right)

Î higher productivity
Power Source
File(s)
Verilog
(Netlist)

UPF 1.0 enables XML by under laying DAG, but P&R

with explicit element names

IEEE P1801 provides symbolic names Power Source
File(s)
Verilog
(Netlist)
Page 20

10
Basics about Power Intent Specification

Objects in a power domain to be supplied:

Power domain

Isolation Level Retention Other

shifter Elements

Requirements for XML specification of power intent:

„ Identifier for objects to be supplied by power
„ Power supplies
„ Explicit supply net names must be avoided
„ Relation of states for power supplies
Î Power State Table (PST)
Î With legality: ok, never, unspecified
„ Transition between power states
Page 21

IEEE P1801: ‘supply_set’ & ‘supply_functions’

„ Objects might be power domains or functional blocks in a design

„ Objects are supplied by ‘supply_set’
„ A ‘supply_set’ is grouping ‘supply_function’ like
† power, ground
† nwell, pwell, …
„ A ‘supply set’ can be associated with a predefined or user defined
‘supply set handle’
† primary
† default_isolation, default_retention
„ Symbolic reference
† PD1.ssh@default_isolation
Î reference for the supply set connected to all isolation cells within PD1, if
not specified differently
† [email protected]@ground
Î reference to the primary ground, which supplies standard cells without
special function in PD2

Page 22

11
IEEE P1801: Power State Table (PST)

PD_REC.primary PD_TRANS.primary PD_TRANS.default_isolation

Sleep 0.0 V 0.0 V 1.5 V
Receive 1.5 V 0.0 V 1.5 V
Transmit & Receive 1.5 V 1.5 V 0.0 V

Symbolic reference name enables power intent specification in a power

state table definition without explicit supply net names.

Page 23

Conclusion

„ IEEE P1801 helps to address challenges in automotive design

† Quality
† Productivity
† First Time Right
„ By Enabling
† Formal power intent specification above RTL
† Interoperability in a multi vendor design flow
† Power aware design verification already at RTL

Page 24

12
Agenda

• 14:00-14:05 Introduction
Stephen Bailey, Director, Verification Products, Mentor Graphics
• 14:05-14:30 Low Power Challenges in Automotive Applications
Juergen Karmann, Senior Staff Engineer Design Methodology,
Automotive, Industrial & Multimarket, Infineon Technologies
• 14:30-14:55 Low Power Challenges for Storage SoC Design and Verification
Dr. Gary Delp, Distinguished Engineer, LSI Corp
• 14:55-15:20 Requirements and Solutions for Low Power Processor Cores
John Biggs, Consultant Engineer, ARM
• 15:20-15:45 Process-aware Low Power Design Ecosystem
Dr. Yi-Kan Cheng, Department Manager, Reference Design Flow
Development, TSMC
• 15:45-16:05 Low Power Flow for Design and Verification
Dr. Ed Huijbregts, Vice President, Design Implementation Products,
Magma Design Automation
• 16:05-16: 50 Deploying Low Power Design Flows
A Multi-Vendor Collaborative Solution – Synopsys, Mentor, Magma
• 16:50-17:00 Roundtable and Wrap-up

Low Power Workshop - 26

13
 Storage and Networking
Challenges for power
efficiency management:
DAC Low Power Workshop
Dr. Gary Delp
[email protected]

Distinguished Engineer, Office of the CTO, LSI

VP & Technical Director, The SPIRIT Consortium
Vice Chair, IEEE P1801
Architect, Si2 Low Power Coalition

Purpose
• Provide motivation for LSI’s profound interest in power efficiency
• Importance of Equity preservation
• Importance of ability to improve – refine design
Agenda
• The storage and networking landscape
• Achieving power efficiencies
• Equity preservation
• Crisp and Consistent Semantics in description languages
– IP Reuse
– State description
• Corruption
• Optimization
• Equivalence and Consistency
• Call for interoperability
– Call for openness

28

14
The Digital World: The Good,

• Web commerce, social networking, telecommuting, tele-presence, tele-

education

29
29

The Digital World: The Good,

The Bad
• Web commerce, social networking, telecommuting, tele-presence, tele-
education
• Information explosion, 24x7 availability,
wireless access, infrastructure limits (power, cooling, space)

30
30

15
The Digital World: The Good,
The Bad and the Ugly
• Web commerce, social networking, telecommuting, tele-presence, tele-
education
• Information explosion, 24x7 availability,
wireless access, infrastructure limits (power, cooling, space)
• Spam, malware, intrusion, spyware, data theft, unauthorized access
(internal and external)

31
31

The Digital World: The Good, The Bad and the Ugly

“In all, data on 25 million of Britain’s 60 million

citizens were on the disks.”
- Daily Telegraph, UK, 30 November 2007

32
32

16
Today’s Storage Environment

Internet
Internet JBOD

Workstation
PCs
Ethernet Switch

Server Server Server

Blade Portable
Servers “Pocket”
PCI
Drives
RAID
HBA
FC Switch
Shared
DAS Portable
JBOD Storage Thumb
System Drives
SAN
Storage
System

As storage scales up, increasing vulnerability

must be addressed

33
33

Why Encrypt Data-At-Rest?

• Data spends most of

its life at rest

• Disk drives are mobile

• Loss of customer data

requires disclosure

• Majority of US states
have safe harbors
for encryption

34

34

17
Storage Encryption Today

• Selective Encryption:
– Can’t afford to encrypt everything
– Performance/scalability concerns
• Data Classification
– What to encrypt?
– How to sort through
mountains of data?
– Was some data missed?

35
35

Full Disk Encryption Basics

Drive Powers Up
Security Session is Established
Initiator Authenticates with the Drive
Normal Read / Write Access
Write
We The Wepqk5td
The
People of the qwsgcn723x1qs
People of the
United States dxldfe94nhbv
United States
of America Read 4ruMkzwdjg
of America

• Data on drive is always encrypted

• Encrypted data (cipher text) never leaves the drive
• Data protected from loss, theft, disclosure
• Applications work transparently with FDE drives
• Little system performance impact due to encryption

36
36

18
Storage Encryption Tomorrow

• Everything is encrypted
– End-to-end encryption
– No performance penalty
– No need to classify data
– Transparent to end user
• Realm-based security
– Best solution for each threat model
– Holistic, comprehensive approach
• Unified key management
– Works with all types of storage devices
• Standards-based
– Multiple sources, interoperable 9 Increased Processing
9 No increase in power budget

37
37

The Storage Environment:

Today…
Internet
Internet JBOD

Workstation
PCs
Ethernet Switch
Disk Drive

Server Server Server

Portable
Blade “Pocket”
Servers Drives
PCI
RAID
HBA
FC Switch
Shared Portable
DAS Thumb
JBOD Storage Drives
System
SAN
Storage
System

38
38

19
The Storage Environment:
Tomorrow…

Internet
Internet JBOD

Workstation
PCs
Ethernet Switch
Disk Drive

Server Server Server

Portable
Blade “Pocket”
Servers Drives
PCI
RAID
HBA
FC Switch
Shared Portable
DAS Thumb
JBOD Storage Drives
System
SAN
Storage
System
9 Increased Processing
9 No increase in power budget

Data-at-Rest problem addressed by FDE

39
39

Today’s Network Environment

Radio Mobile
Access Device
Network
VoIP Laptop
Phone
VoIP
Phone

Gateway
Ethernet
Switch

Wireless Backbone
Access Point
Router
Enterprise Telecomm
Gateway Gateway

Enterprise
Gateway Media
Gateway

Laptop PC PC

PCs

Complexity is rising with multiplicity of access points

and increased sophistication of threats and attacks
40
40

20
Sophisticated Threats Require Complex Responses

Content Blended Attack

Processing Corporate

Anti-X Espionage

Identity Theft
Firedoor
Keyboard Loggers
Anti-Spyware
Image Spam

Anti-Spam Spyware

Text Spam
Web-Filtering Indecent Content

IDS/IPS Trojans
Content
Worms
Based
Cost

Anti-Virus
Viruses

Stateful Firewall Intrusions

VPN
Connection Defacement
Firewall Based File Deletion

Padlock Theft
Moat Physical Siege
41
41

Content Processing Today

• Content Processing technology can

detect sophisticated attacks
– Mix of software-only and hardware solutions
• Software-only approach is limited
– Cannot check all data -- threats
remain undetected
– 10x throughput reduction while
inspecting content
– Requires dedicated appliances or
high-end CPUs
– Does not scale
– Cannot deploy throughout the network

New solutions needed for high-performance response

to increasing threat complexity

42
42

21
Content Processing Defined

Increasing levels of power required for processing

Where does the Who does it go to & What does the

message need to go? who is it from? message contain?
• Routing • Data Routing • Anti-Virus
• Load Balancing • Data Filtering • Advanced IPS
• Basic Filtering • Basic IPS • Anti-Spam
• Port Blocking • Compliance

Content (Deep Packet) Inspection

Stateful Inspection Application Aware Inspection
IP Address Port Options URL Cookies <Envelope> <Body><Order><Part>

Layer 3-4 Layer 5-7

Threats demand comprehensive deep packet inspection,

hardware acceleration needed for line-rate performance

43
43

Content Processing Tomorrow

• Hardware-Accelerated
– Full inspection of all data
– Full network throughput
– Dramatically lower cost
– Significantly reduced
power and cooling
• Greater Deployment
– More threats captured
– Every link protected

44
44

22
The Network Environment:
Today…
Radio Mobile
Access Device
Network
VoIP Laptop
Phone
VoIP
Phone

Gateway
Ethernet
Switch

Wireless Backbone
Access Point
Router
Enterprise Telecomm
Gateway Gateway

Enterprise
Gateway Media
Gateway

Laptop PC PC

PCs

45
45

The Network Environment:

Tomorrow
Radio Mobile
Access Device
Network
VoIP Laptop
Phone
VoIP
Phone

Gateway
Ethernet
Switch

Wireless Backbone
Access Point
Router
Enterprise Telecomm
Gateway Gateway

Enterprise
Gateway Media
Gateway

Laptop PC PC

9 Increased Processing
PCs 9 No increase in power budget

46
46

23
 Key Takeaways
• Many Threat Models to Combat
– Prioritize and break into Trojan Horses Data Theft
manageable chunks to Data Loss
address greatest risks first
• Interoperability is Critical
– Standards leadership and
collaborations
Spyware Intrusions Viruses
IEEE P1619.3
TCG
T10/T13
Worms Spam Malware
IPSec
FC-SP
INCITS
DH-CHAP
47

47

Key Takeaways
• Comprehensive security solution
requires multiple technology We The
uq25td
approaches People of the
jwsgcn923 1qs
United States
– Evaluate FDE to address
Data-at-Rest security lxldfe3vnhbv
of America
– Evaluate Content Processing 4rpMkzwdjg
for threat mitigation
9 Increased Processing
9 No increase in power budget

48

48

24
A three dimensional view of design closure

schedule

Timing
optimal

Area
w er
Po

49

Opportunity for Power Utilization

Improvements

100%
Architectural
80%
Synthesis
Gate
60%
Layout
40%

20%

0%
Power Optimization Potential

50

25
General principles
Interfaces and systems:
• Things should be as simple as they can be,
and no simpler Albert Einstein
• Be conservative in what you provide,
and liberal in what you accept Jon Postel
Standards
• The wonderful thing about Standards
is that there are so many to choose between
• Of all the ways to do it,
that is one. Mike Eneboe
• 90% of success is just showing up
Woody Allen

51

IP Reuse EDA Standards Listing

– not complete – but helping drive consistency
• IEEE IEEE-SA – LSI Corporate membership
– P1685: IP-XACT: XML Meta data and Tool Interfaces
– P1734: QIP – IP Quality Metrics
– P1735: IP Encryption
– P1801: Low Power Design Intent
• Accellera – UPF then P1801
• Open SystemC Initiative (OSCI)
– SystemC
– TLM (Transaction Level Modeling
• Silicon Integration Initiative (Si2)
– Design Technology Council (DTC)
– Low Power Coalition (LPC)
– Open Access Coalition (OAC)
• The SPIRIT Consortium
– IP-XACT
– SystemRDL – register description language
– Debug, verification, Documentation working groups
– Interworking with: OASIS, Eclipse, Si2, Low Power
• Virtual Socket Interconnect Alliance (VSIA) – finished!
– Transferred to IEEE, The SPIRT Consortium, OCP, and the Public Domain
52

26
Key messages – all about equity preservation
• Current tools allow us to manipulate:
– logical constraints and directives – The circuit will do what we want
– Physical shape reuse and analysis – We can build the design
– Static timing analysis – the design will run as fast as we want
• Cannot describe or predict power consistently
– Spice – full analog analysis
– If you don’t write it down, it didn’t happen
– If you can’t fit it on a screen, you can’t get it right
• Power Intent Goals
– Scalable transportable methodology for describing and reasoning from:
• Power Domains
• Power Supplies
• Switches
• Acceptable and forbidden Power Modes or States
• Isolation, Level shifting, retention
– Support Reuse and transport of design equity
• Identification and Constraints – The Platinum Source
• Refinement and Configuration – The Golden Source
• Implementation and analysis – The Silicon Source

53

Power management Structures: The Data Objects

• Power Domain
– The collection of design
objects that share common
power attributes
• Power States
– Controlled by Switches
– Memories may require
Retention
– States may require
sequencing info
– States will effect simulation
• Relations & Connections
between Domains
– Level shifters
– Isolation logic
– “Gas Stations”
alternate supply
• Identify elements
• Manage
• Implement
• Analyze
• Reuse
54

27
Power Management Source & Flow
Power
PowerSource
Source
• The traditional Synthesis flow File(s)
File(s)
– Is augmented with Power HDL/
HDL/
RTL
RTL

• Power source files are part of the

design source.

Simulation, Logical Equivalence Checking, …

– Combined with the RTL, the power files Synthesis
are used to describe the intent of the
designer.
– This collection of source files is the input
to several tools, e.g., simulation tools,
Power
PowerSource
Source
synthesis tools, and formal verification File(s)
File(s)
tools. Verilog
Verilog
(Netlist)
(Netlist)
• Multiple source files may be prepared
specifically to enable reuse.
• The details of the “What” and the P&R
“How” are often produced by different
parties.

Power
PowerSource
Source
File(s)
File(s)
Verilog
Verilog
(Netlist)
(Netlist)

55

IP Reuse and transport

– The same interface definition is used:
• To represent the “Black Box” of a Module
• To validate the design of the module
– Provide consistent interface descriptions
• Set port related supply set
• Feed through definitions
• States on domains (define corruption)

– Support Reuse and transport of design equity

• Identification and Constraints – The Platinum Source
• Refinement and Configuration – The Golden Source
• Implementation and analysis – The Silicon Source

56

28
Power State Table – Intent

DSP & Control Processor:

Clock for timestamp
Power Dom ains

Power Controller
Radio receiver:

Power supply
Sensor Logic

Transmitter
Frequency

Memory
Power State
Off Off Off Off Off Off Off Off Off Off
Initialize On Off high high On Off Off On On
Timed Sleep On Off vlow HB retain Off Off On On
Wait for sounds On On vlow HB retain - - On On
Process sound input On On low low On - - On On
Check for Radio On - low low On Mon Off On On
Receive Radio On - high high On On Off On On
Transmit Data On - high high On Off On On On
Full power On On High high On On On On On

57

Power State Table – Intent

Power
PowerStates
States(UPF)
(UPF)ororPower
Powermodes
modes(CPF)
(CPF)
Defined,
Defined,named,
named,andandthen
thendecorated:
decorated:
••With
WithSAIF
SAIF
••With Libraries
With Libraries
••With
WithLegality
Legality––enabling
enablingoptimization
optimizationand
andchecking
checking
••Corruption of the simstate
Corruption of the simstate
••Clock
ClockPeriod
Perioddependency
dependency
••Transient duration
Transient duration
Enabling
Enablingpreservation
preservationof ofthe
the Logical
Logicalverification
verificationequity
equity

Enables
Enablesoptimization
optimizationand
andconsistent
consistentsimulation
simulationcorruption
corruption

58

29
 Power States & Transitions
Off
• Power states
– Static analysis
– Isolation / Clamp requirements
– Level shifting requirements Full
Initialize
Power
• State Transitions
– There are more transitions
than states
(in all interesting designs)
– Dynamic analysis
Timed
• Inrush requirements Wait
Sleep
• Cross talk
• Isolation requirements
• Level shifting requirements
• ESD issues
Transmit Process
Data Sounds
Or Radio

59

The Low Power Standards “Program”

(you can’t tell the players without “The Program”)

This slide is Power Common

included Cadence Forward Power
to group the Initiative Format
acronyms
Low
so that the Common
SI2 Power
format Power
Coalition
comparison Format
can be Unified
understood Accellera Power
in context Format
IEEE CPF P1801
IEEE 1801
NESCOM & Study Working
Standard
DASC Group Group

60

30
Key Takeaways
• Power Intent Goals
– Scalable & transportable methodology for describing and reasoning from:
• Power Domains
• Power Supplies
• Switches
• Acceptable and forbidden Power Modes or States
• Isolation, Level shifting, Retention
– Support Reuse and transport of design equity
• Identification and Constraints – The Platinum Source
• Refinement and Configuration – The Golden Source
• Implementation and analysis – The Silicon Source
• Two to choose from
– CPF: Cadence, …
– UPF: Synopsys, Mentor, Magma, …
– Potential Unity in IEEE
• Use the defined subset -> expand as tools converge.

61

References and Conclusions

• UPF 2007 is available from accellera.org
• P1801 will be ready for company review June 2008
– IEEE Ballot to follow ~August
• CPF 2007 is available from Si2.org
– CPF 1.1 is in review / rewrite to support interoperablity

• Users goals are to enable interoperability.

• Provide feedback to our vendors that convergence is
important:
– Correlation between intent and implementation is critical
• Crisp semantics will enable this
– We are sacrificing capability for portability
– Interoperability (subset translation) is very high on our acceptance
criteria

62

31
Agenda

• 14:00-14:05 Introduction
Stephen Bailey, Director, Verification Products, Mentor Graphics
• 14:05-14:30 Low Power Challenges in Automotive Applications
Juergen Karmann, Senior Staff Engineer Design Methodology,
Automotive, Industrial & Multimarket, Infineon Technologies
• 14:30-14:55 Low Power Challenges for Storage SoC Design and Verification
Dr. Gary Delp, Distinguished Engineer, LSI Corp
• 14:55-15:20 Requirements and Solutions for Low Power Processor Cores
John Biggs, Consultant Engineer, ARM
• 15:20-15:45 Process-aware Low Power Design Ecosystem
Dr. Yi-Kan Cheng, Department Manager, Reference Design Flow
Development, TSMC
• 15:45-16:05 Low Power Flow for Design and Verification
Dr. Ed Huijbregts, Vice President, Design Implementation Products,
Magma Design Automation
• 16:05-16: 50 Deploying Low Power Design Flows
A Multi-Vendor Collaborative Solution – Synopsys, Mentor, Magma
• 16:50-17:00 Roundtable and Wrap-up

Low Power Workshop - 63

Requirements and Solutions for

Low Power Processor Cores

John Biggs
ARM R&D

Confidential 64

32
The Necessity of Low Power

ƒ World’s 2.3Bn mobile phones can be ƒ World’s 1Bn PCs are on for 9 hours*
kept charged with100 Mega-Watts per day requiring 95,000 Mega-Watts
ƒ Equivalent to 2 large wind-farms ƒ Equivalent to ~100 large coal-fired
power stations

* US PCs are on for 9.2 hours per day - www.itfacts.biz

65

What Consumers Care About

ƒ Users want more features in their mobile devices:
ƒ MP3, Camera, Video, GPS...

ƒ But also need long battery life

ƒ Convenient form factor, affordable price

ƒ Battery technology is not evolving fast enough!

ƒ Need to manage power consumption

66

33
Low Power Is A System Problem

ƒ Operating System with Software Policies

ƒ Managing the entry and exit to and from system sleep states
ƒ System Level Control IP
ƒ Architectural design partitioning, hardware control
ƒ Sleep transition protocol management
ƒ Library Level Support
ƒ Comprehensive low power components (ISO, Switch, Retention)
ƒ EDA Software
ƒ Comprehensive automation yielding ultra low power design with optimal QoR
ƒ Power Supply Management
ƒ External power supply control, power supply tolerances, etc.
ƒ Process Technology
ƒ Trade-off between a high performance and low leakage process

67

Power Dissipation
t
E = ∫ (CV 2 DD f c +VDD I leak ) dt
0
Total
TotalPower
Total
Total Power
Power
Power
Dissipation
Dissipation
Dissipation
Dissipation

t t

∫ VDD I leak dt ∫ CV
Leakage
Static
Leakage Power
StaticPower
Power Switching
Dynamic Power
SwitchingPower
Power 2
Power
Dissipation
Dissipation
Dynamic Power
Dissipation
Dissipation DD f c dt
Dissipation
Dissipation Dissipation
Dissipation
0 0

Ileak
Minimize Ileak by: Iswitch Minimize Iswitch by:
ƒ Reducing operating voltage ƒ Reducing operating voltage
ƒ Fewer leaking transistors ƒ Less switching cap
ƒ Reduce transistor leakage ƒ Less switching activity

68

34
Dynamic Power Optimization
ƒ Dynamic Frequency Scaling (DFS)
ƒ Reduce operating frequency if possible
ƒ Reduces average power (but not task energy)
ƒ Eliminates NOPs

ƒ Dynamic Voltage & Frequency Scaling (DVFS)

ƒ Requires DFS
ƒ Reduces voltage if frequency is reduced
ƒ Reduces task energy
ƒ Based on characterized frequency – voltage pairs (lookup table)

ƒ Adaptive Voltage Scaling (AVS)

ƒ Closed loop optimization of VDD at run-time
ƒ Can save energy even at fixed frequency

69

ARM IEM Principles

ƒ Batteries have finite amounts of energy stored in them
ƒ Running fast and then idling wastes energy

Voltage
Reduce
Reduce
Voltage
Voltage
Reduce
Reduce Energy
Voltage
Voltage
Energy
Saved

Reduce
Reduce Energy
Voltage
Voltage
Run
Run Task
Task in
in
Available
Available Time
Time
Run
Run Task
Task Slow
Slow
as
as Possible
Possible
Time
Task 1 Idle Task 2 Task 3

Only
Onlyneed
needto
torun
runjust
justfast
fastenough
enoughto
tomeet
meetthe
theapplication
applicationdeadlines
deadlines

70

35
ARM IEM Technology
Hardware
Hardwareand
andsoftware
softwaresolution
solutionfor
forenergy
energymanagement
management
Dynamic
Dynamic control of voltage and frequencyscaling.
control of voltage and frequency scaling.

Apps
Apps IEM
IEMsoftware
software Required
Intelligent
Intelligent
Required Energy
Performance Energy
Performance Controller
Policy Evaluation Controller
Apps
Apps
OS
OS Stack
Volts, MHz
Policy
Policy
Policy
Policy Dynamic Dynamic
Dynamic Dynamic
Apps
Apps Voltage
Voltage
Clock
Clock
Policy
Policy Controller Generator
Controller Generator

ƒIEM software connects to OS kernel and collects data.

ƒMultiple policies categorize the software workload.
ƒPrediction of future performance requirement is made.
ƒSuitable operating point (Voltage and Frequency) is set.
71

ARM IEM System Implementation

72

36
Trends In Power Dissipation

ƒ Static power dissipation can no longer be ignored

ƒ It is significant at 90nm and dominant at 65nm
ƒ Leakage currents are rising fast
ƒ Must be controlled by circuit design and optimization tools
73

Leakage Currents
ƒ Transistors are not perfect switches – they always “leak”
ƒ Especially the high performance (low Vt) ones

ISUB: Sub-threshold Leakage

Source Gate Drain
IGATE: Gate Leakage
N+ N+
ISUB IGIDL: Gate Induce Drain Leakage

Psub IGATE IGIDL IREV IREV: Reverse Bias Junction Leakage

Total Leakage = ISUB + IGATE + IGIDL + IREV

ƒ Currently sub-threshold leakage dominates

ƒ Multi-threshold and Power Gating most effective
ƒ However gate leakage is becoming significant
ƒ Can be mitigated by high K dielectric material

74

37
Leakage Mitigation Techniques

Critical Path
VDD SLEEP
A
3x B Y
Virtual VDD
C

VDD

A
1x B
Y Virtual VSS
C
Low Vt nSLEEP
VSS High Vt

Lower Operating Voltage Cell sizing Dual Vt Power Gating

VDDB
A Z
A Z

VSSB

Non minimum size gate lengths VTCMOS Stack Effect

75

Power Gating: Coarse vs. Fine Grain

ƒ Fine grain: one switch per cell VDD

Weak
ƒ Simple to implement PMOS
Pull Up

ƒ Large area overhead on cells

ƒ Switch adds 2-4x area of original cell NSLEEP
NMOS
“Footer”

ƒ PMOS clamps needed in every cell Switch

ƒ Effect on timing easy to characterise

ƒ Coarse grain: distributed switches shared by many cells

ƒ More complex to implement VDD
PMOS

ƒ Small(er) area overhead

SLEEP “Header”
Switches

ƒ Switches are shared – so can be smaller

Virtual VDD

ƒ Clamps only needed at macro cell outputs

ƒ Effect on timing hard to characterise
ƒ Less Performance impact

76

38
State Retention Considerations
ƒ Three possible approaches to state retention
ƒ Software based state save and restore (OS driven)
ƒ Hardware based state save and restore via scan structures (via AMBA)
ƒ Hardware based local state retention with retention registers

ƒ Choice of retention scheme dependant on a number of factors:

ƒ Area overhead of retention registers and size of state space to be maintained
ƒ Performance impact of retention registers
ƒ Energy cost for save and restore when saving state externally
ƒ Real time cost for save and restore when saving state externally

Approach Standby Leakage Area Overhead S/R Energy Cost

Power Gating Only Power Switches & AO Logic Power Switches & AO Logic Complete Reset Required

Power Gating with Power Switches & AO Logic Power Switches & AO Logic State Restore via Software
Software Based Retention
Power Gating with Power Switches & AO Logic Power Switches & AO Logic State Restore via Scan Shift
Scan Based Hibernation From Memory
Power Gating with Power Switches, AO Logic, Power Switches, AO Logic, Minimal as state maintained
Local State Retention Retention Registers Retention Registers locally

Confidential
77

Key Implementation Challenges

ƒ Performance
ƒ Maintain performance requirements of processor while enabling
aggressive low power techniques – optimize cache access
ƒ Ensure operation within characterized timing windows
ƒ For performance scaling – identification of the worst case corner
ƒ Power
ƒ Minimize dynamic power – limit active state leakage currents
ƒ Start with optimal leakage solution – then power gate
ƒ State Integrity
ƒ Manage In-rush current to avoid loss of state at power-up
ƒ Careful identification and optimization of always-on logic
ƒ Design For Test
ƒ Active devices in our power mesh – how do we test these switches ?

78

39
 ARM R&D Low Power
Technology Demonstrators

Confidential 79

Series of Low Power Technology Demonstrators

ƒ DVS926 - TSMC130G – 2003/4
ƒ IEM/DVFS Technology Demonstrator
ƒ Artisan libraries, Synopsys tools,
ƒ Performance scaling 25/50/75/100% of 240MHz
ƒ Operating range 0.7v - 1.2v

ƒ ULTRA926 (UMC130um) – 2004/5

ƒ IEM/DVFS Technology Demonstrator
ƒ Artisan libraries, Synopsys tools,
ƒ Performance scaling 50/67/83/100% of 288MHz
ƒ Operating range 0.7v – 1.2v

ƒ ATLAS926 (TSMC65LP) – 2005/6

ƒ IEM/DVFS Technology Demonstrator with Leakage Mitigation
ƒ TSMC “Fine Grain” power gating libs (Implemented by TSMC)
ƒ Performance scaling 20/40/60/80/100% of 240MHz
ƒ Operating range 0.8v – 1.2v
ƒ CPU supports 4 “depths” of leakage management
ƒ Halted / SRPG / Scan-Hibernation / Shutdown
ƒ SRPG Savings of 85% measured on the testbench

80

40
SALT: Synopsys ARM Leakage Technology Demonstrator

ƒ Joint development with Synopsys to address

EDA implementation
ƒ ARM926EJS based SoC in TSMC90G
ƒ Leakage mitigation technology demonstrator
ƒ Based on R&D Library, Synopsys MV tools
ƒ Performance scaling:
ƒ 33/67/100/133% of 300MHz
ƒ CPU supports 3 “depths” of leakage
management
ƒ State Retention Power Gating
ƒ Scan-Hibernation
ƒ Shutdown
ƒ Support for back/forward bias VTCMOS
ƒ Retention integrity diagnostics

81

SALT In-Rush Current Management

ƒ Closed loop, sequenced power-up of the design
ƒ Combination of regular and ‘starter’ switch columns
ƒ Schmitt Trigger for the Virtual-VDD supply rail. Generate a “Ready”
signal when voltage reaches 90%
ƒ Power-up sequence analysis
ƒ Rush current, wake-up time calculation and IR drop analysis
Header col 5 with start-up
Header col 1 Header col 4 devices

x30 x30 x30 x30 x3 x27

x30 x30 x30 x30 x3 x27

x30 x30 x30 x30 x3 x27

x30 x30 x30 x30 x3 x27

VVDD

Shaded regions represents double-

height layout cells for normal columns
and starter columns

Schmitt These buffers

Buffer placed in bottom
header cell
NSleep

StartIn StartOut (to col 15)

StartIn

82

41
SALT Scan Based Hibernate
ƒ Bus transaction based save and restore to memory
ƒ Bus master implements CRC-32 on the fly
ƒ Diagnostic check for “soft errors” whilst power gated

Extra registers
31
to balance chains On
OnChip
Chip
RAM
RAM

AHB
ARM CPU
Bus
Bus
0 Master
Master Off
OffChip
Chip
SDRAM
SDRAM

83

SALT Silicon Measured Results

Leakage 98%
Reduction High Vt devices
97%
leak more at high
96% temperatures

95%
94%
Over 96% savings
Gate leakage starts across normal mobile
93%
to dominate at low operating range
temperatures 92%
91%
90%
-40°C -20°C 0°C 20°C 40°C 60°C 80°C 100°C 120°C
Temeperature

ƒGraph shows leakage reduction due to power gating over temperature

(compared to mission mode with clocks stopped)
ƒExcellent thermal leakage profile for hand held mobile devices!

84

42
 Low Power Intent
An IP Providers Perspective

Confidential 85

Extent of Soft IP Provider’s Low Power Intent

A Soft IP provider need only declare declare four things:

1. The "atomic" power domains in the design

ƒ these can be merged but not split during implementation

2. The state that needs to be retained during shutdown

ƒ with out prescribing how retention is controlled

3. The signals that need isolating high/low

ƒ with out prescribing how isolation is controlled

4. The legal power states and sequencing between them

ƒ with out prescribing absolute voltages

86

43
 Successive Refinement of Low Power Intent
1 IP Creation 2 IP Configuration 3 IP Implementation

RTL
RTL RTL
RTL RTL
RTL
Constraint
Constraint Constr’nt
Constr’ntUPF
UPF
UPF
UPF
Soft IP Config’n
Config’nUPF
+ Golden Source UPF
Constraint
Constraint
+
UPF
UPF Configuration
Configuration +
UPF
UPF Impl’tion
Impl’tionUPF
UPF

…
Checking, …
Equivalence Checking,
Synthesis

LogicalEquivalence
IP Provider: IP Licensee/User:
ƒ Creates IP source ƒConfigures IP for context Impl’tion
Impl’tionUPF
UPF
ƒ Creates low power ƒValidates configuration Netlist
Netlist
implementation ƒFreezes “Golden Source”

Simulation,Logical
constraints
ƒImplements configuration
ƒVerifies implementation

Simulation,
P&R
against “Golden Source”

Impl’tion
Impl’tionUPF
UPF
Netlist
Netlist

87

Successive Refinement Example

1. UPF Constraints
ƒ IP provider needs to "identify" what is to be isolated with out prescribing how:
set_isolation my_iso -domain my_pd \
-clamp_value 0

2. UPF Configuration
ƒ System Level simulation guy needs to configure the logical power controls with out
having to specify the power supplies:
set_isolation -update my_iso -domain my_pd \
-isolation_signal CLAMP -isolation_sense high

3. UPF Implementation
ƒ Finally the details of power supplies are then added during implementation
set_isolation -update my_iso -domain my_pd \
-isolation_power_net VDDG -location parent

Or specify it all at the same time:

set_isolation my_iso -domain my_pd \
-clamp_value 0 \
-isolation_signal CLAMP -isolation_sense high \
-isolation_power_net VDDG -location parent

88

44
 In conclusion:
ƒ Power dissipation is the #1 limiter of design performance
ƒ Can be mitigated with advanced circuit design and optimization tools

ƒ Power management is a system problem

ƒ Power management strategy must be carefully considered from architecture to silicon

ƒ Need to ease adoption of advanced low power techniques

ƒ Develop low power IP, tools & techniques (ARM’s IEM & PMK)

ƒ UPF enables portability of low power intent

ƒ Provides ability to to compare and contrast a variety of implemention strategies
ƒ Portable across EDA tools and supported by commercial low power libraries
ƒ Low power overlay to existing processor IP from ARM

Transistors
Transistors(and
(andsilicon)
silicon)are
arefree.
free.Power
Powerisisthe
theonly
onlyreal
reallimiter.
limiter.
Optimizing
Optimizingfor
forfrequency
frequencyand/or
and/orarea
areamay
mayachieve
achieveneither.
neither.
Pat
PatGelsinger,
Gelsinger,Intel
Intel(DAC2004
(DAC2004Keynote)
Keynote)

89

Did I mention the book?

ƒ 49% of surveyed customers* identified power management as major concern

ƒ “How do I describe my power requirements?”
ƒ “Which advanced techniques are worth the effort?”
ƒ “I know the concepts, but I don’t know how to implement them”

ƒ ARM & Synopsys partnering to develop solutions to address these concerns

ƒ Many years of joint investment in advanced low power programs
ƒ Driving technology into products: processors, libraries & EDA tools
ƒ Capturing best practise in the Low Power Methodology Manual

http://www.lpmm-book.org

ƒ Free PDF download:

ƒ http://www.arm.com/lpmm
ƒ http://www.synopsys.com/lpmm

* Source: 2007, Synopsys LPMM customer survey

90

45
 Agenda

• 14:00-14:05 Introduction
Stephen Bailey, Director, Verification Products, Mentor Graphics
• 14:05-14:30 Low Power Challenges in Automotive Applications
Juergen Karmann, Senior Staff Engineer Design Methodology,
Automotive, Industrial & Multimarket, Infineon Technologies
• 14:30-14:55 Low Power Challenges for Storage SoC Design and Verification
Dr. Gary Delp, Distinguished Engineer, LSI Corp
• 14:55-15:20 Requirements and Solutions for Low Power Processor Cores
John Biggs, Consultant Engineer, ARM
• 15:20-15:45 Process-aware Low Power Design Ecosystem
Dr. Yi-Kan Cheng, Department Manager, Reference Design Flow
Development, TSMC
• 15:45-16:05 Low Power Flow for Design and Verification
Dr. Ed Huijbregts, Vice President, Design Implementation Products,
Magma Design Automation
• 16:05-16: 50 Deploying Low Power Design Flows
A Multi-Vendor Collaborative Solution – Synopsys, Mentor, Magma
• 16:50-17:00 Roundtable and Wrap-up

Low Power Workshop - 91

Security C –
TSMC Secret

Process-aware
Low Power
Design Ecosystem

Yi-Kan Cheng
TSMC

P. 92 © 2008 TSMC, Ltd

46
 TSMC Low Power - Security C –
TSMC Secret

Process and Design Technologies

z Process Technology Innovation
„ Transistor architectures
„ New dielectric and gate oxide materials
„ Strain engineering to enhance performance
„ Low K interconnect dielectric to reduce
capacitance

z Design Technology Innovation

„ TSMC low power IP
„ TSMC low power methodology
„ Low power implementation and verification
automation

P. 93 © 2008 TSMC, Ltd

Integrated Process+IP+Methodology Security C –

TSMC Secret

Solution
Low Power Automation – UPF/CPF Library & Flow
Adaptive Voltage Power gating
Source+Back Bias
Scaling (AVS) switch optimization
Hierarchical Voltage with Power gating
Power Trim Solution
Dual Power SRAM data retention
Dynamic Voltage Coarse-grain
Voltage Scaling
Freq. Scaling (DVFS) Power Gating

Power Shutdown Back Bias Power Shutdown

Fine-grain
CLK Gating & Low Power CTS Muti-Vt Device
Power Gating

Dynamic Power Active Leakage Standby Leakage

Low Power Methodologies

Low Power Low Power
Lib SRAM

New in Ref Flow 9.0 Low Power Process

P. 94 © 2008 TSMC, Ltd

47
 Security C –

Agenda TSMC Secret

(Advanced Process for Power Reduction

z Low Power Interoperability
z Power Trim Solution
z Low Power Automation

P. 95 © 2008 TSMC, Ltd

Process Evolution – Security C –

TSMC Secret

Metal Scheme Scaling

N90 N65 N40

Vdd(V) 1.2V 1.2V 1.1V

Drawn Width (um) 0.14 0.1 0.07

Drawn Space (um) 0.14 0.1 0.07

Metal Thickness (um) 0.325 0.22 0.14

Thickness Reduction
93% 68% 64%
Ratio

Unit Cap Reduction Ratio 87% 95% 83%

P. 96 © 2008 TSMC, Ltd

48
 Dynamic Power Reduction Trend Security C –
TSMC Secret

ARM 11 Core - Dynamic Power (mW/M Hz)

1.20
1.00 SV T
0.80 LV T
HV T
Ratio

0.60
0.40
0.20
0.00
90G 65GP 40G
SVT 1.00 0.49 0.25
LVT 1.00 0.64 0.30
HVT 1.00 0.54 0.28
Process Node

P. 97 © 2008 TSMC, Ltd

Major Standby Leakage Reduction Security C –

TSMC Secret

Design Methods
Low Power Design Fine Grain Coarse Grain Coarse Grain
Methods Footer Header Footer
Header/ footer switch, mother-
TSMC low power library & Cell with footer, daughter switch, switch for
IP retention FF always_on row, retention FF,
isolation cell

Active leakage reduction 5-10X 30-60X 60-120X

Area overhead 5-15% 4-6% 2-3% + DNW

Performance penalty 2-4% 2-4% 2-4%

Data retention/ Yes/ Retention Yes/ Retention Yes/ Retention

Special conditions FF (HVt) FF extra PG FF extra PG

P. 98 © 2008 TSMC, Ltd

49
 Security C –

Agenda TSMC Secret

z Advanced Process for Power Reduction

(Power Trim Solution
z Low Power Interoperability
z Low Power Automation

P. 99 © 2008 TSMC, Ltd

Power Trim Solution for Active Leakage Security C –

TSMC Secret

z Effects of Gate-Length Biasing

„ Exponential leakage reduction

Leakage Current

PMOS (W=150nm) Drawn biased

Biased

480

430

380
Bias to Significant
330
new rule leakage reduction
Ioff (nA)

280

230

180

130

80

30
95 100 105 110 115 120
L (nm)

P. 100 © 2008 TSMC, Ltd

50
 Power Trim Solution – Security C –
TSMC Secret

Achieve through Gate-Length Biasing

Example
Transistor on critical path
Ö use no bias (0nm)

Transistor on nearly critical path

Ö use minimum bias (+2nm)

Transistor on non-critical path

Ö use maximum bias (+6nm)

z Small increase in gate length delivers large reduction

in leakage power
z Tiny gate-length changes (within foundry-qualified
bounds) implemented during OPC

P. 101 © 2008 TSMC, Ltd

Power Trim Solution – Flow Security C –

TSMC Secret

Preparation Optimization Annotation

.BSIM .GDS .SPEF .DEF
.SPI .LEF .V .SDC .LEF .GDS

PowerTrim PowerTrim PowerTrim

.GDS’ .GDS’ .DEF’

.SPI’ .LEF’ .V’
D IF F U S IO N

Golden Cell Golden

Characterization Signoff STA POLY1

Annotation
.LIB’ (Layer number, data type)

z Generate “virtual variants” z Advantages of gate- z Adds marker layers to GDS database
z length biasing
Views generated z Foundry OPC flow processes the
„ LEF, annotated GDSII, z Optimization engine marker layers to extract the CD target
extracted SPICE tuned for “rich” for each transistor
libraries
netlists z Designer does not do any additional
layout

P. 102 © 2008 TSMC, Ltd

51
 Sample Power Trim Results Security C –
TSMC Secret

Process Library Cell Reduction at

Type Count Block/Chip Level
65nm LP Multi Vt 100,000 30%
65nm LP Multi Vt 200,000 20%
65nm G Multi Vt 100,000 30%
65nm G Multi Vt 1,000,000 25%
90nm G Multi Vt 200,000 30%
90nm LP Multi Vt 2,000,000 15%
90nm LP Multi Vt 90,000 20%
90nm LP Multi Vt 1,000,000 20%
90nm G Single Vt 80,000 30%
90nm G Single Vt 200,000 30%

P. 103 © 2008 TSMC, Ltd

Agenda Security C –
TSMC Secret

z Advanced Process for Power Reduction

z Power Trim Solution
( Low Power Interoperability
z Low Power Automation

P. 104 © 2008 TSMC, Ltd

52
 TSMC Low Power Library Security C –
TSMC Secret

z Support Liberty 2007.03 Low Power Attributes

„ Power and Ground Pins for standard cells and low power cells
„ Level Shifter and Isolation Cells in Multi-Voltage Design
„ Power Switch Cells and Retention Flip-Flops
library (tcbn45gsbwpwc) { cell (LVLLHCD4BWP) {
/* library head: tcbn45gsbwp */ area : 9.1728;
technology (cmos) ; cell_footprint : "lvllhcd1";
delay_model : table_lookup ; is_isolation_cell : true;
date : "Wed Apr 9 2008 " ; is_level_shifter : true;
comment : "Copyright TSMC" ; level_shifter_type : LH;
revision : 100 ; input_voltage_range (0.72, 1.1);
simulation : true ; output_voltage_range (0.72, 1.1);
nom_process : 1 ; /* SS SS_18 */ dont_touch : true;
nom_temperature : 125; dont_use : true;
nom_voltage : 0.81; pg_pin (VDD) {
voltage_map(COREVDD1, 0.81); pg_type : primary_power;
voltage_map(COREVDD2, 0.72); voltage_name : COREVDD1;
voltage_map(COREGND1, 0.0); std_cell_main_rail : true;
operating_conditions("WC0D720D81COM"){ }
process : 1; /* SS */ pg_pin (VDDL) {
temperature : 125; pg_type : primary_power;
voltage : 0.81; voltage_name : COREVDD2;
tree_type : "balanced_tree"; }
… pg_pin (VSS) {
… pg_type : primary_ground;
… voltage_name : COREGND1;
}
………

P. 105 © 2008 TSMC, Ltd

Single UPF for Synopsys & Magma Security C –

Implementation Flow TSMC Secret

SE #--- Power Domain Definition

SE_FE create_power_domain TOP
create_power_domain PD_FE -elements {SE_FE0}
Domain : TOP •••
VDD_0d9 Domain : PD_FE #--- Power Domain Supply Ports
create_supply_port VSS
Always ON VDD_0d9 create_supply_port VDD_0d9
Always ON •••
#--- Power Supply Nets
create_supply_net VSS -domain TOP
create_supply_net VSS -domain PD_FE -reuse
create_supply_net VDD_0d9 -domain TOP
create_supply_net VDD_SW_0d8 -domain PD_ME
•••
#--- Connect Supply Nets to Ports
connect_supply_net VSS -ports VSS
connect_supply_net VDD_0d9 -ports VDD_0d9
•••
#--- Connect Supply Nets to Power Domain Cells
SE_PE SE_ME set_domain_supply_net TOP \
-primary_power_net VDD_0d9 -primary_ground_net VSS
Domain : PD_PE Domain : PD_ME •••
#--- Level Shifter Settings
VDD_1d0 VDD_SW_0d8 set_level_shifter TOP2PE –location self \
Always ON Power ON/OFF -domain PD_PE -applies_to inputs -rule low_to_high
•••
#--- Isolation Settings
set_isolation PD_ME_iso_output -domain PD_ME \
-isolation_power_net VDD_0d9 \
-isolation_ground_net VSS \
-clamp_value 1 -applies_to outputs
set_isolation_control PD_ME_iso_output -domain PD_ME \
z Isolation Control : -isolation_signal SE_ME_iso_n \
-isolation_sense low -location parent
„ SE_ME_iso_n #--- UPF Power Switch Definitions
create_power_switch PD_ME_sw -domain PD_ME \
-input_supply_port {TVDD VDD_0d8 } \
z Power Gating Control : -output_supply_port {VDD VDD_SW_0d8} \
-control_port {NSLEEPIN2 SE_ME_on_2 } \
„ SE_ME_on_2 -ack_port {NSLEEPOUT1 SE_ME_on_ack_1} \
-on_state {state_on TVDD {NSLEEPIN2} }

z
#--- Power State Definitions
Power Gating Ack : add_port_state VDD_0d8 -state { wc_0d8 0.72 }
add_port_state VDD_0d9 -state { wc_0d9 0.81 }
„ SE_ME_on_ack_1 add_port_state VDD_1d0 -state { wc_1d0 0.90 }
add_port_state PD_ME_sw/VDD -state { wc_0d8 0.72 } \
-state { OFF off }

P. 106 © 2008 TSMC, Ltd

53
 UPF Interoperability for Security C –
TSMC Secret

Low Power Implementation

Magma Synopsys
Talus Power Pro DC/ICCompiler
Voltage Island Definition
create_power_domain 9 9
create_supply_port 9 9
create_supply_net 9 9
connect_supply_net 9 9
set_domain_supply_net 9 9
Level Shifter Rule Definition
set_level_shifter 9 9
Isolation Rule Definition
set_isolation 9 9
set_isolation_control 9 9
Power Gating Definition
create_power_switch 9 9
set_retention 9 9
set_retention_control 9 9

P. 107 © 2008 TSMC, Ltd

Security C –

Agenda TSMC Secret

z Advanced Process for Power Reduction

z Low Power Interoperability
z Power Trim Solution
(Low Power Automation – UPF Flow

P. 108 © 2008 TSMC, Ltd

54
 TSMC Reference Flow 9.0 –
Synopsys UPF Low Power Flow Security C –
TSMC Secret

RTL
RTL Low
Low Power
Power Simulation
Simulation MVSIM / VCS
Power
Power management
management logic
logic simulation
simulation

Low
Low Power
Power Synthesis
Synthesis
ISO/Level
ISO/Level Shifter
Shifter Insertion
Insertion Design Compiler / DC Graphical / Power Compiler
Retention
Retention Flip-Flop
Flip-Flop Synthesis
Synthesis

Low
Low power
power DFT
DFT DFT MAX

Low
Low Power
Power Floorplan
Floorplan
Voltage
Voltage Island
Island Floor
Floor Planning
Planning IC Compiler PrimeRail PrimeTime PX
Low
Low Power
Power Power
Power Planning
Planning

Low
Low Power
Power Implementation
Implementation
Multi-voltage
Multi-voltage MCMM
MCMM placement
placement optimization
optimization IC Compiler
Low
Low Power
Power CTS
CTS
Multi-voltage
Multi-voltage MCMM
MCMM Route
Route &
& optimization
optimization
Gate
Gate Level
Level Low
Low Power
Power Simulation
Simulation
Power
Power management
management logic
logic simulation
simulation MVSIM / VCS
Multi
Multi SDF
SDF back-annotation
back-annotation for
for DVFS
DVFS simulation
simulation

Resistivity
Resistivity analysis,
analysis, power
power &
& IR
IR signoff
signoff PrimeRail PrimeTime PX HSIM / NanoSIM

Timing
Timing Signoff
Signoff PrimeTime Suite
Multi-voltage
Multi-voltage Multi-scenario
Multi-scenario timing
timing signoff
signoff
Power
Power domain
domain OCV
OCV analysis
analysis
MVSIM / VCS Formality MVRC
Power
Power checker
checker &
& functional
functional verification
verification
Multi-voltage
Multi-voltage DRC
DRC // LVS
LVS Hercules

P. 109 © 2008 TSMC, Ltd

TSMC Reference Flow 9.0 – Security C –

TSMC Secret

Magma UPF Low Power Flow

Low
Low Power
Power Synthesis
Synthesis Talus®
ISO/Level
Talus® Design
Design
ISO/Level Shifter
Shifter Insertion
Insertion
Retention
Retention Flip-Flop
Flip-Flop Synthesis
Synthesis
Talus®
Talus® Power
Power Pro
Pro
Low
Low Power
Power Floorplan
Floorplan
Voltage
Voltage Island
Island Floor
Floor Planning
Low
Low Power
Power Power
Planning
Power Planning
Planning
Talus®
Talus® ACC/ HydraTM
ACC/ Hydra TM

Talus®
Talus® Vortex
Vortex
Low
Low Power
Power Implementation
Implementation
Multi-voltage
Multi-voltage MCMM
MCMM placement
placement optimization
optimization
Talus®
Talus® Power
Power Pro
Pro
Multi-voltage
Multi-voltage CTS
CTS QuartzTM
Quartz TM Rail
Rail
Multi-voltage
Multi-voltage MCMM
MCMM Route
Route &
& optimization
optimization

Resistivity
Resistivity analysis,
analysis, power
power &
& IR
IR signoff
signoff Talus®
Talus® Vortex
Vortex
Static/Dynamic
Static/Dynamic Power
Power Analysis
Analysis
Static/Dynamic
Static/Dynamic IR
IR Drop
Drop Analysis
Analysis
Talus®
Talus® Design
Design
Coarse-Grain
Coarse-Grain Analysis
Analysis QuartzTM
Quartz TM Rail
Rail

P. 110 © 2008 TSMC, Ltd

55
Agenda

• 14:00-14:05 Introduction
Stephen Bailey, Director, Verification Products, Mentor Graphics
• 14:05-14:30 Low Power Challenges in Automotive Applications
Juergen Karmann, Senior Staff Engineer Design Methodology,
Automotive, Industrial & Multimarket, Infineon Technologies
• 14:30-14:55 Low Power Challenges for Storage SoC Design and Verification
Dr. Gary Delp, Distinguished Engineer, LSI Corp
• 14:55-15:20 Requirements and Solutions for Low Power Processor Cores
John Biggs, Consultant Engineer, ARM
• 15:20-15:45 Process-aware Low Power Design Ecosystem
Dr. Yi-Kan Cheng, Department Manager, Reference Design Flow
Development, TSMC
• 15:45-16:05 Low Power Flow for Design and Verification
Dr. Ed Huijbregts, Vice President, Design Implementation Products,
Magma Design Automation
• 16:05-16: 50 Deploying Low Power Design Flows
A Multi-Vendor Collaborative Solution – Synopsys, Mentor, Magma
• 16:50-17:00 Roundtable and Wrap-up

Low Power Workshop - 111

UPF Tool Flow

UPF
UPF
HDL/
HDL/
RTL
RTL
Simulation, Logical Equivalence Checking, …

Synthesis

UPF
UPF
Verilog
Verilog
(Netlist)
(Netlist)

P&R

UPF
UPF
Verilog
Verilog
(Netlist)
(Netlist)
Low Power Workshop - 112

56
Design Implementation – An Example Flow

Talus Design
• Domain Definition Talus Power Pro
• Power domains
• Supply rails Synthesis

Unified Power Format

• Domain Relationship
• Power state tables Talus Vortex
Talus Power Pro
• Special Cells
Layout
• Retention
• Isolation
• Level shifters
• Switches Quartz Rail

Signoff

Low Power Workshop - 113

UPF + RTL Provide a Complete Low Power Design Specification

• Power Domains UPF

UPF
• Power Distribution Network RTL
RTL

• Switches and Supply Nets

Simulation, Logical Equivalence Checking, …

• Power State Synthesis

• Level Shifting UPF

UPF

• Isolation Netlist
Netlist

• Retention
P&R
• Switching Activity
UPF
UPF
GDSII
GDSII

Low Power Workshop - 114

57
Power Aware Design Implementation

Dynamic Power Reduction Leakage Power Reduction

MTCMOS BACK BIAS
MVDD Low Power CTS Vdb
MTCMOS 1.08v
Stand-by
Vdd
Domain Constant
Active
LS

Bias
Lines

Active
IC Always-ON Buffers
Clock Gat e Enable
Control Vss
Register
Vsb Stand-by

DVFS MULTI-VT
Low VT Nom VT High VT

… …
Dynamic
Dynamic
Voltage Vdd
Voltage
Supply RTL Synthesis
Supply RTL Synthesis
Circuit
Circuit Vdd
Physical Synthesis
Physical Synthesis
Ref
CTS
CTS
Vss
Place & Route
Place & Route
Gnd

Power Analysis & Distribution

Power Grid MTCMOS
Transient Analysis
Power & IR Drop
Thermal Analysis Rail EM
Synthesis Analysis

Low Power Workshop - 115

Advanced Low Power Techniques for Mobile Devices

Imaging & ASIC

2D/3D
ARM11 Video Domain 3
TMS320C55x Graphics
+ VFP Accelerator
DSP Accelerato
(IVA) RAM
r
Domain 3
Domain 1

L3 Interconnect
DSP
L4 Interconnect

LCD ASIC/Clocks
Peripherals

I/F Domain 2
Security

Camer Memory Internal

Video Controller SRAM
a I/F
Out RAM
Domain 3
*

•• Clock
Clock Gating
Gating •• MTCMOS
MTCMOS •• Multi-VDD
Multi-VDD
•• Power
Power aware
aware CTS
CTS •• Isolation
Isolation cells
cells
•• DVFS
DVFS
•• Level
Level Shifters
Shifters
•• Retention
Retention flop
flop •• Back-Bias
Back-Bias •• Multi-Vt
Multi-Vt
synthesis
synthesis (VTCMOS)
(VTCMOS)

* TI OMAP2
Low Power Workshop - 116

58
Defining Domains and Electrical Conditions

Logical Æ Electrical Æ Physical

UPF Commands
0.8 1.0

Domain0 switched
Domain1 v v
create_power_domain
constant
LS add_domain_element
PM connect_supply_net
ctrl
logic
IS
create_supply_net
Diagram from Andrew O

create_supply_port
LS
get_supply_net
merge_power_domains
set_domain_supply_net
Domain2
Constant
0.8
v

Low Power Workshop - 117

Level Shifters in MVDD flows

Level shifter considerations: VDD 1.1v

• Pick a power domain or a set of elements VDD1

0.9v

• Select input ports, output ports, or both

• Tolerate a voltage difference threshold
• UP shift or down SHIFT rule VDD2
1.5v

• Location (self, parent, sibling, fanout,

auto)
• Insert or not insert
VDD 1.3v
VDD1
1.1v S

VDD2
1.1v C

Low Power Workshop - 118

59
Level Shifter insertion using UPF

UPF Commands

set_level_shifter
1.2v
Constant
map_level_shifter

User Defined
Regions

Isolation
• Automatic rule based insertion
Cell
0.9v • Length dependant and IR drop
Switched dependent Insertion
1.08v
Constant • Electrical Rule Checks to identify
domain relationships
Supply Type • Well spacing rules honored
••Constant
Constant
••Variable
Variable
• Switchedconstant
• Switched constant
••Switched
Switchedvariable
variable

Low Power Workshop - 119

Isolation Cells for Shut Down Domains

UPF Commands
1.0v set_isolation
set_isolation_control
Domain0 switched

map_isolation_cell

PM ctrl
logic
• Automatic placement close to
domain boundary
ISOLATION
• Options for clamp “0” or “1”

Low Power Workshop - 120

60
Retention Flops in Shut Down Domains

UPF Commands
1.0v set_retention
set_retention_control

Domain0 switched
map_retention_cell

PM ctrl • Maintains state of domains that

logic
are powered down
ISOLATION
• Automatic placement and power
RETENTION
connectivity

Low Power Workshop - 121

Switch Cell inference using UPF

UPF Commands
create_power_switch SW1 -domain pdA
1.2v
200Mhz -input_supply_port {inp PR}
Switched VDD -output_supply_port {outp RET}
Switched VDD
MTCMOS

200Mhz
1.6v

set_domain_supply_net pdA
1.4v -primary_power_net PR
200Mhz
Constant VDD -primary_ground_net VSS

Lp1 Ln1
Ln3
Ln2 Lp3
Distributed MTCMOS Lp2

Fine Grain spAOn

PR RET

Global SW1
SW1

Standard cell specific Module A pdA

Grid based insertion
Logic

Low Power Workshop - 122

61
Enable Line Stitching

• Automatic enable line stitching MTCMOS 1.08v

Constant
• Enable line treated as high fan-out net (special Domain
Flow
buffers needed)
• Single and dual enable controls supported
• Daisy chain support for switches with built-in
buffers
• Incremental enable line stitching supported

Enable
Control

Always-ON
Daisy Chain Modes Buffers

o
switch switch switch switch switch switch switch switch switch switch switch switch switch switch switch switch
o o o o o o o o o o o o o u o o o
in u in u in u in u in u in u in u in u in u in u in u in u in u int u in u in u
switch t switch t switch t switch t switch t switch t switch t switch t switch t switch t switch t switch t switch t switch t switch t switch t
o o o o o o o o o o o o o o o o
in u in u in u in u in u in u in u in u in u in u in u in u in u in u in u in u
switch to switch to switch to switch to switch to switch to switch to switch to switch to switch to switch to switch to switch to switch to switch to switch to
in u in u in u in u in u in u in u in u in in in u in u in in in u in u
u u u u
t t t t t t
Delay
t t t t t t t t t t
controlled
enable

Low Power Workshop - 123

Power State Table

• A power state table defines the legal combinations of states for different
domains
• create_pst command creates a PST, using a specific order of supply nets
during operation of the design
• Each row defines a valid combination of supply states
• Power states enable optimization and verification
• Infer or verify level shifters and isolation gates

UPF Commands

create_pst
add_pst_state

Low Power Workshop - 124

62
Full Catalog of UPF Products

Low Power Workshop - 125

UPF Benefits

• Productivity
• Same intent used throughout entire low power RTL Verif
flow
• Interoperability and productivity with mixed EDA
Unified Power Format

Synthesis
flows
• High Quality Results Pre-Verif
• Consistent intent throughout flow = better
checking and convergence Layout
• IEEE P1801 approach enables successive
refinement Post-Verif

• Simple IP Reuse
Signoff
• Supports IP specification and use
• No changes needed to golden HDL Finished
GDSII

Low Power Workshop - 126

63
Conclusion

• User community is actively guiding UPF

• All leading users enthusiastically participate
• Concepts are production proven
• EDA community is strongly behind UPF
• Supported by 9 out of 10 leading vendors
• Interoperability is the key to success
• IEEE P1801 standardization On Track
• World-wide adoption
• Broad education effort to follow

Low Power Workshop - 127

Agenda

• 14:00-14:05 Introduction
Stephen Bailey, Director, Verification Products, Mentor Graphics
• 14:05-14:30 Low Power Challenges in Automotive Applications
Juergen Karmann, Senior Staff Engineer Design Methodology,
Automotive, Industrial & Multimarket, Infineon Technologies
• 14:30-14:55 Low Power Challenges for Storage SoC Design and Verification
Dr. Gary Delp, Distinguished Engineer, LSI Corp
• 14:55-15:20 Requirements and Solutions for Low Power Processor Cores
John Biggs, Consultant Engineer, ARM
• 15:20-15:45 Process-aware Low Power Design Ecosystem
Dr. Yi-Kan Cheng, Department Manager, Reference Design Flow
Development, TSMC
• 15:45-16:05 Low Power Flow for Design and Verification
Dr. Ed Huijbregts, Vice President, Design Implementation Products,
Magma Design Automation
• 16:05-16: 50 Deploying Low Power Design Flows
A Multi-Vendor Collaborative Solution – Synopsys, Mentor, Magma
• 16:50-17:00 Roundtable and Wrap-up

Low Power Workshop - 128

64
Low Power Solutions a Year Later

David Peterman of TI receives UPF 1.0 on behalf of User community

from Accellera Chairman Shrenik Mehta at DAC 2007
Low Power Workshop - 129

UPF Solutions – Live in Action!

• Synopsys – Eclypse Low Power Platform

• Mentor – Questa and Formal Pro
• Magma – Talus Power Pro

Low Power Workshop - 130

65