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Advanced Computer Architecture Summer 2012: 2/6/2012 ACA Spring 2012 Shaftab Ahmed 1

This document summarizes lecture notes on computer architecture from a course. It introduces key concepts like CPU, memory, registers, and I/O. It then reviews the architecture of early Intel processors like the 8088 and 8086. It discusses memory organization techniques used over time, from real mode to protected mode. Finally, it covers memory addressing schemes in modern processors like Pentium using page tables and virtual memory.

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Dkjshlgulhuiawperhfjfg Hassan
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41 views23 pages

Advanced Computer Architecture Summer 2012: 2/6/2012 ACA Spring 2012 Shaftab Ahmed 1

This document summarizes lecture notes on computer architecture from a course. It introduces key concepts like CPU, memory, registers, and I/O. It then reviews the architecture of early Intel processors like the 8088 and 8086. It discusses memory organization techniques used over time, from real mode to protected mode. Finally, it covers memory addressing schemes in modern processors like Pentium using page tables and virtual memory.

Uploaded by

Dkjshlgulhuiawperhfjfg Hassan
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Advanced Computer Architecture Summer 2012

Week #1 Lecture 1&2 Introduction

2/6/2012

ACA Spring 2012

Shaftab Ahmed

Introductory lecture
Computer Architecture
CPU, Memory, I/O, Secondary Storage Registers cache memory ( static / dynamic ) secondary storage Timing and control (IO / Memory Read / Write cycles) Size of register address space Clock Speed of execution Use of temporary registers, Stack etc

2/6/2012

ACA Spring 2012

Shaftab Ahmed

8086 / 8088 Architecture

2/6/2012

ACA Spring 2012

Shaftab Ahmed

Timing Diagram Bus Read 8088

2/6/2012

ACA Spring 2012

Shaftab Ahmed

Intel 32 bit Processors 80486-Pentium

2/6/2012

ACA Spring 2012

Shaftab Ahmed

Key concepts in State of Art Computer Architecture

Processor + Ram + Busses + I/O Devices


Processor Internal ALU / No of ALUs and Types Number of Registers General Purpose / Special Pipelining Register Aliasing Caching / Re-Ordering Memory Management External Busses / Hierarchy -- System / Special / Input Output DMA -- Direct Memory Access Multiprocessor connectivity Peripheral connectivity

2/6/2012

ACA Spring 2012

Shaftab Ahmed

Intel Processors review


AX, BX,CX,DX (Accumulator, Base, Count, Data) Useable as AX AH and AL SP Stack Pointer BP Base address of an array DI Destination index used with string manipulation instructions SI Source Index used with string manipulation instructions CS, DS, ES,SS Segment Registers Flag register containing status information after an instruction 80386 Onwards CPUs have 32 bit Arithmetic Registers (EAX .. ) FS GS are two more segment registers available to programmer 32 bit Flag register, Stack pointer and special registers
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2/6/2012

ACA Spring 2012

Shaftab Ahmed

Significance of Flag Register


8088 /8086 CPU C P A Z S T I D 80286 CPU O IOP NT 80386 CPU RF VM 80486 CPU AC Pentium CPU VIF VIP ID Carry Parity 0 Odd 1-- Even Auxiliary carry used for BCD addition 0 Result = Zero; 1 Result != 0 0 Result Positive 1 Result Negative Trap used to exploit on chip debug feature Interrupt enabled when set = 1; disabled when = 0 Direction D=1 Auto increment of SI or DI D=0 Auto decrement of SI or DI Overflow Used to indicate error in signed ADD, SUB instructions (Input Output Privilege Level) Range from 00 to 11 It determines I/O verses program priority Nested Task

Resume Virtual Mode

Alignment check

Virtual Interrupt Flag used in multi tasking Virtual Interrupt Flag Pending used in multi tasking Indicates that P4 CPU support CPUID instruction

2/6/2012

ACA Spring 2012

Shaftab Ahmed

Intel Processors Memory Organization


Real mode
8088 / 8086 use Segment registers to support addressing in the range 1Mbyte of memory. Real memory is divided into System area, Transition Program Area (TPA) and Interrupt Vector table (IVT) etc.

Protected mode
It was introduced to address memory beyond 1MB LDT, GDT are used for Memory Access beyond 1M Memory interleaving was used in 80286 processor onwards to reduce memory latency Subsequent slides show the progressive transition in memory organization schemes used

2/6/2012

ACA Spring 2012

Shaftab Ahmed

Intel Processors Memory Organization

2/6/2012

ACA Spring 2012

Shaftab Ahmed

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Transient Program Area

Interrupt Vector Table

2/6/2012

ACA Spring 2012

Shaftab Ahmed

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Interface logic
Interrupt vector table
There are 256 software interrupt vectors. First 32 vectors are reserved the remaining may be used by the programmer Interrupt vector is a 4 byte number stored in the first 1K bytes of memory (0 3FF). Address of interrupt vector is derived by 4*interrupt number

For protected mode the vector table is replaced by interrupt descriptor table that uses 8 byte entries for each descriptor

2/6/2012

ACA Spring 2012

Shaftab Ahmed

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Interrupts
Hardware interrupt sources are NMI and INT Mask able Interrupt INT is expanded to 8 hardware interrupts in XT and 16 hardware interrupts in AT architecture Software interrupts may be generated by:
INT INT3 INTO Two byte instruction codeinterrupt number One byte instruction used to set trap Interrupt on overflow

All the interrupts use the same Vector table

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ACA Spring 2012

Shaftab Ahmed

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System Area

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ACA Spring 2012

Shaftab Ahmed

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Expanded Memory Windows

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ACA Spring 2012

Shaftab Ahmed

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Descriptor Tables for Protected Mode


In protected mode the segment register contains a selector number to use a Descriptor There are 8192 Local Descriptors and 8192 Global Descriptors available to a Task. The Global Descriptors are available to all tasks and the Local Descriptors are available to a particular application or Task

2/6/2012

ACA Spring 2012

Shaftab Ahmed

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Example of GDT to Physical Address

2/6/2012

ACA Spring 2012

Shaftab Ahmed

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Program Invisible Registers of P4


Descriptor cache is a set of program invisible set of registers Corresponding to the segment registers They describe the physical location of the segment in the memory

Task Register Local Desc. Task Register Global DTR Interrupt DTR

2/6/2012

ACA Spring 2012

Shaftab Ahmed

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Virtual Memory Addressing in Pentium

2/6/2012

ACA Spring 2012

Shaftab Ahmed

19

Page Directory and Page Table Entry


Linear address

Page Table Entry

2/6/2012

ACA Spring 2012

Shaftab Ahmed

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8088-8086-80386 and 80486 Memory

8088

8086, 80286 etc.

80386, 80486 etc.

2/6/2012

ACA Spring 2012

Shaftab Ahmed

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Pentium 4 Processor Memory

Pentium Pro to Pentium 4

2/6/2012

ACA Spring 2012

Shaftab Ahmed

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I/O Address Space

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ACA Spring 2012

Shaftab Ahmed

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