2CEIT507: Computer Architecture & Organization Practical-6

Practical-7

AIM: Design and testing of 4-bit CPU.

Theory:
At the top level a computer consists of a CPU (central processing unit), memory, I/O
components, with one or more modules of each type. These modules are interconnected in a
specific manner to achieve the basic functionality of a computer i.e. executing programs. At
the top level a computer system can be described as followes:

 describing the external behavior of each component i.e the data and the control signals
that ir exchanges with other components
 describing the interconnection structure and the controls required

We are considering the Von Neumann architecture. Some of the basic features of this
architecture are as follows:

 data and instructions are stored in a single read-write memory

 the contents of the memory are addressable by location
 execution occurs in a sequential manner (unless explicitly specified) from oneinstruction
to the next
Top level components and interactions among them:

 CPU exchanges data with memory. For this CPU uses two internal resisters.
Following is a block diagram of a basic computer system:

 Memory address register (MAR) which specifies the address for the next read or write
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 Memory buffer register (MBR) which contains the data to be written into memory or
receives the data read from memory
 I/O buffer (I/O BR) register is used for the exchange of data between an I/O module and
the CPU

A memory module consists of a set of a locations defined by sequentially numbered addresses.

Each location contains a binary number that cam be interpreted as either an instruction or data.

An I/O module transfers data from external devices to CPU and memory and vise versa

The basic function of a computer is to execute a program which consists of a set of

instructions stored in the memory. Processing required for a single instruction is called an
instruction cycle which consists instruction fetch and instruction execute. A register called
program counter (PC) holds the address of the next instruction. Unless told otherwise the
processor always increments PC after each instruction fetch so that the next instruction is
fetched in sequence. The fetched instruction is fetched into a register called instruction
register (IR).

After fetching an instruction, processor execute the instruction by doing some processing on
the data which may involve arithmetic and logic unit (ALU), specified by the instruction, then
processor writes back the result (if any) to the memory.

Procedure:
Procedure to perform the experiment:CPU Design
1. Start the simulator as directed.This simulator supports 5-valued logic.

2. To perform the experiment on the given modules, we need the CPU, the working memory
with a program and data loaded, a clock input, Bit switch(to give input,which will toggle its
value with a double click), Bit displays(for seeing output), wires.

3. Load memory: click on the load memory button in the left pane. you can either load the
memory by filling the form or you can directly load the program form a text file. The memory
provides 4-bit address space and 12 bit data word, thus providing 16 memory address starting
from 0000 to 1111. For loading from file, the file should contain only binary values, it must
contain 16 lines, each line containing the content to be stored in the corresponding memory
address. For example, content of first line will be loaded to the 0000 address of the memory,
similarly, the second line will correspond to the 0001 address and so on, finally the content of
last line will be fed to the 1111 address. The progrm should use self loop for halting, for
example, the instruction stored at address 1010 will cause self loop execution, if it content of a
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has -1 in binary format (in 2'scomplement), the content of b has 0 and c is 1010, then once the
execution reaches to this 1010 address, it will finally point to itself.

4. Instantiating the memory: after loading the memory, click on the memory component from
the computer design drawer in the palette of the simulator then click on the position of the
design editor where you want to put the component(no drag and drop, simple click will serve
the purpose).

5. The pin configuration of the component is shown whenever the mouse is hovered on any
canned component of the palette or pressing the show pin configuration button on the toolbar
will show it constantly in the left pane. Pin numbering starts from 1 and from the bottom left
corner(indicating with the circle) and increases anticlockwise.

6. Pin configuration of the memory module:

 Input pins (upper terminals): memory enable : 30, R/W' : 29, address : 25-28, data : 13-24
(13 is LSB)
 Output pins(lower terminals): data output : 1-12 (1 is MSB)

7. Instantiate the CPU from the computer design drawer in the palette of the simulator then
click on the position of the design editor where you want to put the component.

8. Pin configuration of the CPU:

 Input pins (upper terminals): data input : 20-31 (20 is MSB) ,clock input : 19
 Output pins(lower terminals): memory enable : 1, R/W' : 2, address : 3-6( 3 is MSB), data
output : 7-18 (7 is MSB)

8. To connect any two components select the Connection menu of Palette, and then click on
the Source terminal and click on the target terminal. According to the following diagram
connect all the components. Connect the memory outputs to the input terminals of the CPU,
specified datapath outputs to the inputs of the controller, the clock input, Bit switches with the
inputs and Bit displays component with the outputs (from Display and Input drawer of the
pallet,if it is not seen scroll down in the drawer). After the connection is over click the
selection tool in the pallete.

9. Start clock and observe the behavior of the CPU.See the content of memory by clicking
show memory button in the left pane. Observe how the program is executing sequentially and
modify the data content as per the program.
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Objective:
Our main objective for this experiment is to show the basic top level functionality,
organizationand architecture of a computer.This top level structure and function of a basic
computer isimportant because of its explanatory power in understanding the nature of a
computer. A graspon these basic structure and functionality will provide insight into system
bottolnecks,alternative pathways. Because in many cases, requirement of greater system
power and failsafecapabilities are achieved by changing the system design rather than
changing the speedand reliability of individual components. So we have designed a single
instruction CPU whichcontains a controller. A working memory has been given to examine
the behavior of the CPU.The memory will contain the program in binary format which will be
executed by the CPU.Through this, students can observe the behavior of a basic CPU and as
well as a computer. The I/O modules have not been included in the system for the purpose of
symplicity.

Recommended learning activities for the experiment:

Leaning activities are designed in twostages, a basic stage and an advanced stage.
Accomplishment of each stage can be selfevaluatedthrough the given set of quiz questions
consisting of multiple type and subjectivetype questions. In the basic stage, it is recommended
to perform the experiment firstly, on thegiven encapsulated working module, secondly, on the
module designed by the student, havinggone through the theory, objective and procuder. By
performing the experiment on the workingmodule, students can only observe the input-output
behavior. Where as, performingexperiments on the designed module, students can do circuit
analysis, error analysis in additionwith the input-output behavior. It is recommended to
perform the experiments following thegiven guideline to check behavior and test plans along
with their own circuit analysis. Thenstudents are recommended to move on to the advanced
stage. The advanced stage includes theaccomplishment of the given assignments which will
provide deeper understanding of the topicwith innovative circuit design experience. At any
time, students can mature their knowledge base by further reading the references provided for
the experiment.
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Test plan :
Load the memory according to the following figure, then start clock and observe the behavior
of the CPU. See the content of memory by clicking show memory button in the left pane.
Observe how the program is executing sequentially and modify the data content as per the
program.
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2) Loading Memory :
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