CPU Components:

● ALU (Arithmetic Logic Unit): Performs arithmetic and logical operations, such as
addition, subtraction, AND, OR, etc.
● Control Unit (CU): Directs the operation of the processor by interpreting and
executing instructions. It coordinates the flow of data within the CPU.
● Registers: Small, fast storage locations used to hold data temporarily during
computation. Common registers include the Program Counter (PC), Accumulator
(AC), Instruction Register (IR), and Status Register (SR).

2. Clock:

The clock provides a timing signal that synchronizes the operations of the CPU and other
components. It determines the speed at which instructions are processed.

3. Instruction Cycle:

The basic sequence in which the CPU processes an instruction:

1. Fetch: The instruction is fetched from memory.

2. Decode: The fetched instruction is decoded to determine what action to take.
3. Execute: The action specified by the instruction is carried out.
4. Store (optional): Results of the execution are written back to memory or a register.

Control Signals Generation:

● Based on the decoded instruction, the control unit generates appropriate control signals to instruct
various parts of the CPU.

Types of Control Signals:

1. ALU Control Signals:

○ These signals specify what operation the ALU should perform (e.g., addition, subtraction, AND,
OR).
○ For example, for an addition operation, the ALU control unit would generate a signal telling the
ALU to add the two operands.
2. Register Control Signals:
○ These control signals manage the reading and writing of data to and from registers.
○ For example, a signal to load data from a register or to store a result into a register.
3. Memory Control Signals:
○ These signals control data transfer between the CPU and memory.
○ Examples include signals to read from or write to memory.
4. Control Signals for I/O:
○ These signals manage communication between the CPU and peripheral devices.
○ For example, signals to control input and output operations, such as reading data from a
keyboard or sending data to a display.
5. Clock Signals:
○ These synchronize the actions of different components, ensuring that operations occur in the
correct sequence.
4. Using the Control Signals:

Once the control signals are generated, they are sent to various parts of the CPU to execute the instruction:

● ALU Operations: The control signal tells the ALU what operation to perform.
● Data Movement: Control signals direct the movement of data between registers, memory, and other
components. For example, they may specify whether data should be written to a register or read from
memory.
● State Transition: Some control signals may trigger a state change in the control unit, for example,
advancing the program counter to the next instruction or handling branching in conditional
instructions.

5. Example:

Consider an example where an instruction like ADD R1, R2, R3 (Add contents of R2 and R3 and store the
result in R1) is executed:

● Instruction Fetch: The CU generates signals to fetch the ADD instruction from memory.
● Instruction Decode: The CU decodes the ADD opcode and generates signals to specify:
○ Read values from registers R2 and R3.
○ Perform addition using the ALU.
○ Write the result back to register R1.

HARDWIRED CONTROL

● Hardwired control is a type of control unit that generates control signals through fixed logic
gates and circuits
● These Logic circuits are designed to perform specific tasks based on the instruction set of the
CPU
● Design of the control unit is predefined and dont change durin operation and hence faster
execution

ADVANTAGES

● Because of the use of combinational circuits its fast

● It doesnt require control memory
● Simple design and implementation

DISADVANTAGES

● Complexity of design increases as we require more control signals

● Difficult to modify
● Difficult to test and correct mistakes
Here's an organized comparison of Hardwired Control Unit and Micro-programmed Control Unit:

Aspect Hardwired Control Unit Micro-programmed Control Unit

Implementation Fixed set of logic gates and circuits Microcode stored in memory

Flexibility Less flexible, difficult to modify More flexible, easier to modify

Instruction Set Supports limited instruction sets Supports complex instruction sets

Complexity of Design Simple design, easy to implement Complex design, more difficult to
implement

Speed Fast operation Slower operation due to microcode

decoding

Debugging and Difficult to debug and test Easier to debug and test
Testing

Size and Cost Smaller size, lower cost Larger size, higher cost

Maintenance and Difficult to upgrade and maintain Easier to upgrade and maintain
Upgradability

RISC REDUCED INSTRUCTION SET ARCHITECTURE

Main idea is to simplify hardware using an instruction set composed of a basic few steps for operations

KEY POINTS

1. Simpler instruction hence simple instruction decoding

2. Instructions are smaller than one word size
3. Instruction takes a single clock cycle to get executed
4. Has simple addressing modes
5. Pipeline can be achieved
6. Uses fewer data types
7. Has more general purpose registers

ADVANTAGES

1) RISC uses Simple smaller set of instructions making them easier to decode
2) Faster execution of RISC due to the small size of instruction
3) RISC uses lower power than CISC
DISADVANTAGES

1) Requires more number of instructions to perform complex tasks

2) RISC uses more memory to store additional instructions needed to perform complex tasks
3) Developing and manufacturing RISC is costlier than CISC

CISC COMPLEX INSTRUCTION SET ARCHITECTURE

The main idea is that a single instruction will do all operations contrast to RISC that uses simple smaller sets
of instructions to perform tasks

KEY POINTS

1. Complex instructions leading to complex decoding

2. Instructions are larger than one word size
3. Instruction may take more than single clock cycle to get executed
4. Less number of general purpose registers as operations are performed in the memory itself
5. It uses complex addressing modes
6. Uses more data types

ADVANTAGES

1. Reduced code size as CISC uses complex instructions that can perform multiple operations reducing
the amt of code needed to perform the task
2. Its more memory efficient as they require fewer instructions to perform more complex tasks

DISADVANTAGES

1. Slower execution due to complex instructions and time required to decode them
2. Difficult to design and implement due to complex instruction sets
3. Higher power consumption
 Feature RISC CISC

Instruction Set Smaller, simpler instructions Larger, more complex instructions

Instruction Length Fixed length Variable length

Execution Time Typically one clock cycle May take multiple clock cycles

Addressing modes Simple and uses limited addressing Complex and uses more addressing
modes modes

Number of Registers More registers Fewer registers

Complexity of Simple, one operation per instruction Complex, multiple operations per
Instructions instruction

Power consumption Consumes low power Consumes more power

Pipelining Easier to implement More difficult to implement

Performance Generally higher performance Performance can vary

Code Size Larger code size Smaller code size

 CONTROL SIGNALS
1. Read/Write Control Signals:

● Read Signal: Indicates that data should be fetched from a specific memory location or I/O device.
● Write Signal: Tells the system that data should be written to memory or an I/O device.

2. Clock Signal:

● The clock provides a timing pulse that synchronizes the operation of the CPU and other components.
The clock signal determines the pace at which instructions are fetched, decoded, and executed.

3. Memory Read/Write:

● Memory Read: This signal tells the memory unit to read data from a specific location in memory. It’s
typically activated when the CPU needs to retrieve data.
● Memory Write: Activates when the CPU needs to write data to a memory location.

4. Enable Signals:

● Register Enable: Allows a particular register to accept data from the data bus. The Control Unit
activates this signal when data needs to be stored in a register.
● Bus Enable: Controls whether the data bus is enabled to transfer data between components (e.g.,
from memory to the ALU).

5. ALU Control Signals:

● ALU Operation (ALU Op): Specifies the operation the Arithmetic Logic Unit (ALU) should perform,
such as addition, subtraction, AND, OR, etc.
● ALU Select (ALU Sel): In some architectures, this signal selects the input for the ALU (for example, it
may choose between two different registers or data sources).

6. Interrupt Control Signals:

● Interrupt Request (IRQ): Signals that a device or external source is requesting attention from the
CPU. The Control Unit may temporarily halt its current task to process the interrupt.
● Interrupt Acknowledge (IAK): Acknowledges the receipt of an interrupt signal and typically triggers
the start of interrupt handling.

7. Clock Pulse and Timing Signals:

● Clock Pulse (Clock or CLK): This signal synchronizes the execution of instructions by providing a
consistent timing reference. It ensures that the processor operates in a predictable manner.
● Timing Signals: These are used to define the exact timing of operations, such as the start and end of
a read or write operation, based on the clock cycle.

8. Control Signals for Data Path Components:

● Multiplexer Control: Many CPU systems use multiplexers (MUX) to select data paths. Control signals
direct which input is selected for the MUX, enabling the flow of data between registers, memory, or
the ALU.
 ● Shift Register Control: In processors that use shift operations, these control signals manage whether
data is shifted left or right within the register.

9. Condition Flags:

● Some CPUs use status flags (often part of the Status Register (SR)) to set or clear based on the
outcome of arithmetic or logical operations. These flags are used to control branching decisions, such
as:
○ Zero Flag (ZF): Set if the result of an operation is zero.
○ Carry Flag (CF): Set if there is a carry-out from the most significant bit.
○ Sign Flag (SF): Indicates if the result of an operation is negative

10. Branch Control Signals:

● Branch or Jump Signals: Control whether the program counter (PC) should change to a new address
(branching/jumping). These signals are often based on conditions (like the outcome of a comparison)
and affect program flow (e.g., conditional jumps).

11. IO Control Signals:

● Input/Output Read: Used when the CPU wants to read data from an I/O device.
● Input/Output Write: Used when the CPU wants to write data to an I/O device.
● I/O Enable: Enables or disables communication with an I/O device.

12. Program Counter Control Signals:

● PC Enable: Allows the Program Counter (PC) to be updated with the next instruction’s address, either
sequentially or based on a jump or branch operation.
● PC Load: Controls when the Program Counter is loaded with a new address, for example, during a
jump or an interrupt.