Fall 2024 CA Lab-11

Namal University, Mianwali

Department of Electrical Engineering
EE-459L – Computer Architecture (Lab)

Lab -11

RISC-V Pipeline Processor Design: Part-2

Student’s Name

Roll No.

Date Performed

Marks Obtained

Course Instructor: Lab Instructor:

Dr. Tassadaq Hussain Engr. Majid Ali

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Document History
Rev. Date Comment Author
1.0 23/10/2023 Initial draft Engr. Maria Rehman
1.1 06/10/2024 Modified Engr. Majid Ali

Instructions

 Read the manual carefully before start of any tasks / experiments.

 Carefully handle all equipment available in the lab.
 Carefully write your particulars at first page on the manual.
 In case of simulation at PC, try to avoid opening of unnecessary tabs.
 Submit PDF report of each lab at Q-OBE, attach all findings in report properly.
 Write precise conclusion of every lab.
 Submission time is end of respective lab session for each manual, late submission of
manual is not acceptable.
 Fill manual individually even in case of group work.
 Plagiarism will be dealt with strict consequences.

Objectives
1. Understand the transition from single-cycle to pipelined processor architecture.
2. Implement the ID/EXE & EXE/MEM stages of the RISC-V pipeline:
3. Simulate and verify the functionality of the implemented pipeline stages.

Learning Outcomes
This lab satisfies the following learning outcomes of the course:
 CLO2: Assembles components of microprocessors using various tools.
 CLO3: Present concise and comprehensive technical reports.

Equipment & Components

 Computer with Ubuntu OS installed.
 Icarus Verilog for simulation.
 GTKWave for waveform analysis.

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Introduction
In modern processors, pipelining is a fundamental technique used to improve instruction
throughput by overlapping the execution of multiple instructions. Unlike single-cycle
processors, where each instruction is executed in a single clock cycle, pipelining divides the
instruction execution process into multiple stages. Each stage handles a specific part of the
instruction execution, allowing several instructions to be processed simultaneously, one in
each stage.

The RISC-V pipeline consists of the following main stages:

1. Instruction Fetch (IF): The instruction is fetched from memory using the Program
Counter (PC).
2. Instruction Decode (ID): The fetched instruction is decoded, and necessary control
signals are generated. Registers are also read in this stage.
3. Execution (EX): Arithmetic or logical operations are performed, and the effective
address is calculated for memory operations.
4. Memory Access (MEM): Data is read from or written to memory for load and store
instructions.
5. Write-Back (WB): The results of the instruction are written back to the register file.

In this lab, we begin the transition from a single-cycle processor to a pipelined design by
implementing the instructions decode and execution stage (ID/EXE) and execution and
Memory stage (EXE/MEM)..

Lets first understand the analogy of pipelining:

Laundry Example

Aisha, Bilal, Fatima and Hamza

Each has one load of clothes to wash, dry, fold, and put away.

 “Washer” takes 30 minutes

 “Dryer” takes 30 minutes
 “Folder” takes 30 minutes
 “Putter” takes 30 minutes

Total time for one load: 120 minutes

This example demonstrates how tasks can be completed

sequentially versus in parallel. Each person (Aisha, Bilal,
Fatima, Hamza) has one load of laundry that requires
washing, drying, folding, and putting away, each taking
30 minutes. Sequential execution for one load takes 120
minutes. However, with pipelining (overlapping tasks),
the overall time can be significantly reduced for all loads
combined.

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Fig.1: The laundry analogy for pipelining

Aisha, Bilal, Fatima and Hamza each have dirty clothes to be washed, dried, folded and put
away. The washer, dryer, folder and storer each take 30 minutes for their task. Sequential
laundry takes 8 hours for four loads of washing, while pipelined laundry takes just 3.5 hours.

We illustrate the pipeline stages of different loads over time by showing copies of the four
resources on this two-dimensional timeline, though in reality, we have just one of each
resource.

Pipelined Laundry: Overlapping Execution

 Parallelism improves performance.

 For four loads of laundry:
o Speedup = 8 / 3.5 = 2.3
o For non-stop laundry:
 Speedup = 2n / (0.5n + 1.5) ≈ 4
 (where n is the number of stages).

Important Notes

 Each load of laundry still takes 120 minutes to complete.

 The improvements are in the throughput for 4 loads.
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 Pipelining becomes more complicated if stages take different amounts of time.

Pipeline Stages with Representation

1. IF: Instruction Fetch from Memory
 A box represents the Instruction Memory (IM).
 The right-half shaded section indicates usage of the IM during the second half of the
cycle.
2. ID: Instruction Decode & Register Read
 A box represents the Register File.
 The right-half shaded section shows the register being read during the second half of
the cycle.
3. EX: Execute Operation or Calculate Address
 The shaded region represents the execution of the operation or address calculation.
4. MEM: Access Memory Operand (Only for Load/Store)
 A white background indicates no usage (e.g., for an add instruction).
5. WB: Write Result Back to Register (Only for Load and AL Instructions)
 A box represents the Register File.
 The left-half shaded section shows the write to the register happening during the first
half of the cycle.

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Fig.2: Pipelined datapath

Task 1: Design the Instruction Decode and Execution (ID/EXE) Stage.

Task 2: Design the Execution and Memory (EXE/MEM) Stage.

Conclusion

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 CLO2: Assembles components of microprocessors using various tools.

 CLO3: Present concise and comprehensive technical reports.

Domain Criteria Excellent (10) Good (8-9) Satisfactory (6- Improvement(4-5) Marks
7) Obtained
Successfully Successfully Had difficulty Did not complete tasks
Building completed tasks with completed tasks completing tasks and and struggled with lab
Psychomotor Processor understanding and but with some used lab equipment equipment
(P4) (CLO-2) good use of understanding with errors.
equipment. gaps
Presented outstanding Presented Provided basic Unable to answer
Report and detailed reports. comprehensive answers in reports questions and had
Writing
reports with some with limited significant knowledge
Affective (A2)

(CLO-3)
minor gaps. knowledge gaps. gaps.

Answered questions Answered Answered questions Unable to answer

confidently and questions with basic questions and was not
Lab Viva showed exceptional comprehensively understanding and confident.
(CLO-3) knowledge and and exhibited limited knowledge.
comprehension. strong knowledge

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