Announcements

I Regular class tomorrow

I Tutorial session on Friday, 11 March, 2016
Outline

Internal Architecture of 8085

Specifications of 8085

I 40-pin
I 8-bit CPU (8-bit data)
I 16-bit address bus - Max. addressable memory : 64KB
I Clock speed - 3 MHz or 5 MHz
I 12 addressable 8-bit registers
I 6 (8-bit) or 3 (16-bit) general purpose registers
I Accumulator (8-bit), flags (8-bit)
I Program counter (16-bit), Stack pointer (16-bit)
I Interrupts - 4 maskable and 1 non-maskable
Functional block diagram of 8085

What would constitute such a processor ?

Functional block diagram of 8085
Hardware components

Data path
I Arithmetic logic unit (ALU)
I Instruction register and decoder
I Register array
Control path
I Timing and Control unit
I Interrupt control
I Serial I/O control
ALU

I Performs arithmetic and logic computations

I Accumulator, temporary registers, flags
I Arithmetic and logic circuits
Timing and Control unit

I Synchronizes microprocessor operations with the clock

I Generates control signals for communication between CPU
and peripherals (RD , WR)
I Following some communication protocol
Instruction Register and Decoder

I Fetched instruction is loaded in the instruction register

I Decoder decodes and establishes sequence of events to follow
I Microprogramming
I Not programmable by user
Register array

I Temporary registers - W and Z - to hold 8-bit data during

certain instruction execution, internal and not available to user
I General purpose, programmable registers (GPR) -
B, C , D, E , H, L - 8-bit each
I These can be combined pairwise as BC , DE , HL for 16-bit
operations
I When used as pair - C , E , L contain the low-order byte
I In instructions M representing memory refers to memory
address in HL
Accumulator - A

I Most frequently used register

I 8-bit register A, part of ALU
I Implicit destination or source register for several operations
I PSW - program status word - [Accumulator Flags]
Flags register

Flags reflect the data conditions in the accumulator (A) - except

Z flag which is modified depending on results in any register
I S - sign flag
I set if bit D7 is 1 after execution of arithmetic or logic
operation, applicable for signed numbers
I Z - zero flag
I set if ALU operation results in 0
I modified by results in A as well as other registers
I AC - auxiliary carry flag
I set if during an arithmetic operation a carry is generated by
D3 and passed to D4
I internally used for BCD operations
I cannot be used by programmer
Flags register

I P - parity flag - after an arithmetic or logic operation

I set to 1 if the result has even number of 1s (even parity)
I set to 0 if the result has odd number of 1s (odd parity)
I CY - carry flag - after arithmetic operation
I set to 1 if the operation results in a carry
I set to 0 if the operation results in No carry
I ’borrow flag’ in case of subtraction
Program Counter (PC )

I 16-bit register to hold memory address

I Points to the memory address from which next byte is to be
fetched
I When a byte is fetched, the PC is incremented by 1 to point
to the next memory location
I CPU uses this to sequence the execution of instructions
Stack Pointer (SP) and Stack

Stack pointer
I 16-bit register, whose content points to beginning of stack
I Decremented by two during PUSH or POP instructions
Stack
I a LIFO memory location in read/write memory
I used to store temporary information (address or data) during
program execution
I Storage starts in address one-less than that address in the SP
register
I Data bytes from register-pair (Rp) can be stored in the stack
in reverse order
I Used by both user and CPU
Pinout Diagram of 8085

Source: Intel data sheet

Buses and Signals

Buses
I Address bus - 16 bits wide
I AD7 − AD0 - bidirectional, data and address
I AD8 − AD15 - unidirectional, address
I Data bus - 8 bits wide
I AD7 − AD0 - bidirectional, data and address
I AD7 − AD0
I Carries address bits during the early part of the operation
I Carries data bits during the later stage of execution
I Address bits are saved ( latched) before they become data bits
Buses and Signals

Signals
I Control signals
I RD & WR - active-low signals, indicating selected I/O or
Memory device to be read or written
I Status signals
I IO/M - Distinguish between I/O & Memory operations
I S1, S0 - Distinguishes type of operations (eg., read or write)
I Special signal
I ALE - Address Latch Enable - used to enable a latch to save
the low-order address from the multiplexed bus
I ALE positive going pulse - indicates that bits AD7 − AD0 are
address bits
Buses and Signals

Clock and frequency control

I X 1, X 2 - input pins connected to a crystal that generates a
clock signal
I Frequency of internal clock is half the frequency produced by
the crystal
I CLK OUT - Output signal, to be used as system clock for
connected devices
Serial I/O Ports
I SID - serial input data
I SOD - serial output data
Buses and Signals

Interrupts
I We will look at this later
Other externally initiated signals
I RESET IN - CPU is reset, PC is set to zero, buses are
tri-stated
I RESET OUT - indicates CPU is being reset, used to reset
other devices
I HOLD - peripheral is requesting use of address and data bus
I HLDA - acknowledge HOLD request
I READY - signal used to delay the microprocessors read or
write cycles - used by a slow-responding peripheral device -
microprocessor will be in WAIT state until this signal goes
high
Fetching an Instruction from Memory

To fetch instruction (DB) from memory location 3090

I PC is set to 3090
I The address 3090 is next placed on the address bus - 30 on
A15 − A8 and 90 on AD7 − AD0
I Next ALE signal goes high to indicate AD7 − AD0 is carrying
the low-order address
I The IO/M goes low to indicate this is a Memory operation
I Next the RD low signal is sent to Memory
I Memory places DB on AD7 − AD0
I After this RD goes high
I Instruction decoder decodes DB for necessary operation
Fetching from Memory

AD15−AD8
AD15−AD8

8085 ALE

EN

AD7−AD0 Memory
LATCH

WR RD IO/M

RD WR
MEMR

MEMW

Multiplexed bus (Address/Data)

Address bus

Data bus
Fetching from Memory

AD15−AD8
AD15−AD8

8085 ALE

EN

AD7−AD0 Memory
LATCH AD0−AD7

WR RD IO/M

RD WR
MEMR

MEMW

Multiplexed bus (Address/Data)

Address bus

Data bus
Fetching from Memory

AD15−AD8
AD15−AD8

8085 ALE

EN

AD7−AD0 Memory
LATCH AD0−AD7

WR RD IO/M
D7−D0
RD WR
MEMR

MEMW

Multiplexed bus (Address/Data)

Address bus

Data bus
Do you know ?

I What is the maximum memory size accessible by 8085 uP?

I List all the 16 bit registers 8085 uP has.
I By increasing the clock rate (MHz), we will improve
performance ? T / F
I User Applications will be written as microprograms ? T / F
Instruction Set Architectures (ISA)

Types of architecture
I Accumulator arch.
I Extended accumulator or special-purpose register arch.
I Intel’s 8085 and 8086
I General-purpose register arch.
I register-memory, e.g., AMD64
I load-store or Register-register, e.g., MIPS, SPARC, Intel IA-64
I memory-memory, DEC (Digital Equip.) - not very popular
I Stack architecture, e.g., Calculators (HP)
Registers: Assembly Variables

I Similar to variables in high-level languages

I Registers are operands in assembly instructions
I Fixed number of registers
I Keep the hardware simple
I Registers are fast when compared to general memory
Levels of Representation

I Highlevel language (ex., C, C++, Python, Matlab, etc.)

I HLL to assembly language - compiler
I Assembly language (mnemonics - symbolic Code)
I Mnemonics to binary - assembler
I Hex to binary using ’monitor’ program in lab
I Machine language (binary)

I Machine Interpretation and Architecture Implementation

Performing Operations - High-level

I Decide on operation/algorithm
I Outline the algorithm Flowchart, Pseudocode, etc.,
I High-level language to implement the algorithm
I Compile, assemble, link to generate machine language
program
Performing operations - 8085 processor

Use assembly language

I Low-level language using mnemonics
I assembler translates mnemonics to binary - machine specific
I Hand assembly - write hex code from instruction set look-up
I ’execute’ the program by starting from a specific memory
location
Microprogramming

I This deals with the control path

I How a binary string controls ALU, Registers, Clock, etc. ?
I We will not concentrate on the control path, but mainly look
at the data path
Program Format

Mem. addr. Machine code Label Mnemonics Comments

2007 DB READ: IN 07H ; Read Port#
2008 07
Memory Address
I 16 bit addresses of the user R/W memory in the system,
I Points to location of the machine code
Machine Code
I Written as Hexadecimal code by programmer
I Binary code stored in the microprocessor
I Represents the operation and operands
Assembly Instructions

Instructions (as mnemonics) have two (mostly) parts

Opcode Operand
Opcode
I Indicates the operation or function
Operand
I Specifies arguments/items to be processed - one or two (in
8085)
I 8-bit/16-bit data, a register, or a memory address
I May be absent - implicit
Comments and Label

Comments
I Documentation for a program
I Separated by a ’;’ from the instruction on the same line
Label (optional)
I Pseudo-Operand
I 5 characters, 1st character must be character,@ or ?
Endianess (Byte Order)
Numbering bytes within a word - byte with the lowest number is
either the leftmost or rightmost one
Little endian
I Increasing significance with increasing memory address
Byte #
3 2 1 0
MSB LSB
I In 8085, a 16-bit data 2007H, will be stored as
Address Data
3000 07
3001 20

Big endian
I Decreasing significance with increasing memory address
Byte #
0 1 2 3
MSB LSB
Data Formats

I ASCII
I 7-bit alpha numeric code
I To represent decimal numbers, alphabets, special characters
I Recently - 8-bit extended ASCII
I BCD
I Binary-Coded Decimal - decimal numbers 0 to 9
I need four bits to represent each digit
I Signed Integer
I +ve or -ve number.
I Largest +ve number 7FH, Smallest -ve number FFH
I Unsigned Integer
I No sign bit
I Largest number FFH, smallest number 0H
Instruction Size
One byte - just the Opcode
Mnemonic Opcode
MOV A, B; 78H
DCX SP ; 3BH
RRC ; 0FH
Two bytes - Opcode followed by 8-bit (byte) data

Mnemonic Opcode
MVI A, 8-bit ; 3E, 8-bit
ADI 8-bit ; C6, 8-bit
Three bytes - Opcode followed by 16-bit addr. or data
Mnemonic Opcode
LXI B, 16-bit(data) ; 0A, 16-bit
JNZ 16-bit(addr.) ; C2, addr.
CALL 16-bit(addr.) ; CD, addr.
Addressing Modes

Constant following the opcode as

Immediate part of the mnemonic. MVI R, Data
Operands are stored in the regis-
Register ters. MOV Rd, Rs
Memory location of operands is
Direct provided. LDA 16bit addr.
Memory location of operand is
Indirect specified by a register-pair. LDAX B
Addressing Modes

I Immediate addressing - MVI R, Data

I Register addressing - MOV Rd, Rs
I Direct addressing - IN Port#, LDA 16−bit addr.
I Indirect addressing - LDAX B
I Other approaches (not applicable to 8085)
I Indexed
I Relative
I Implied
Addressing Modes

Why different addressing modes ?

I To include short address as part of instruction (less memory
space)
I Easy access to large amount of memory
I To vary the actual value within the address without changing
instructions
I Fast or simple addressing methods
I Handling different types of data - constants, variables, or
arrays